JPS6053328B2 - Multiplication rounding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention has the advantage of rounding the multiplication results of the DFT (discrete Fourier transform) employed for signal detection in, for example, a digital MFC (multiple station frequency signal) receiver, thereby improving the efficiency of the receiver for low input levels. This invention relates to a multiplication and rounding circuit that improves the ambiguity range between moving and unimpressing levels.

Traditionally, circuits of this type have been designed to discard the multiplication results of the DFT used for signal detection, but this type of circuit design reduces the sensitivity of the receiver to low input levels. The drawback is that the level of emotion is highly ambiguous. FIGS. 1 and 2 show an example of a conventional multiplication circuit that truncates the result of multiplication using 4-bit data, its peripheral circuits, and the input/output timing of signals in its main parts.

Before explaining the specific operation of the circuit configuration, the multiplication data X, Y
and the multiplication result Z (=XY) is as follows.

x■-1+ Σ2-nxn(xn■0 or 1)n■1
...(1) Y=-23y0+ Σ23-nyn(y
n ■ 0 or 1) n ■ 1 ... (2) Z=XY=-
2'Xyo+2Xy juice 2Xy.

+Xy32'Xyo+2''Xy, +2Xy2+Xy.(
yo■ 0)...(3)1+2'Xy.

+2Xy, +2Xy. +Xy, (yo■1) However, X represents the negative logic of X. Now, to explain the specific operation, parallel data 1
1. It is applied to the strobe terminal G of the 2-1 selector 2 via the inverter 5.

As a result, the set output from D-type flip-flop 1,
Gating the reset outputs to 23Xyn. 7f''
Since the calculation of Xyn is performed and the signal B3 is input to the select terminal S of the 2-1 selector 2, when n=o,
When 'XyO is n=1 to 3, the calculation output of 23Xyr1 is output from the 2-1 selector 2. Next, this output Fxy
rl (or 23'X/n) is D in 4-bit full adder 3.
2 to the previous bit addition result from type flip-flop 4.
The value multiplied by -1, ``+123+n? It is added to KXyk. At this time, the gate output Y of AND gate 6. 4
It is input to the carry input terminal C of the bit full adder 3, and the formula (
Y shown in 3). Addition of 1 when =1 is performed.
When all the additions are completed, the multiplication results are taken in parallel to the parallel-to-serial converter 7 by the signal [, and then converted into serial data. At this time, the multiplication result latched in the D-type flip-flop 4 by the clock pulse CP is the reset signal R.
It is cleared and prepared for the next multiplication.
On the other hand, the multiplication result as serial data from the parallel-to-serial converter 7 is added to the previous accumulation result from the input terminal 112 in the adder 8, and the accumulation result from this addition is added to the output terminal 1.
A D-type flip-flop 9 provided nearby is used to hold the carry output from the addition until the carry input of the next bit. The basic operation of conventional multiplication and accumulation circuits is as described above, but in this example, since the multiplication result is limited to 4 bits, the set output of the D-type flip-flop 4 is combined with 4-bit total addition. One bit is truncated when inputting the data to the device 3.

However, in the case of two's complement representation, truncation of this bit affects the negative side regardless of whether the data is positive or negative, so the average value of the error due to truncation is -0.5, which causes a DC deviation to be added to the multiplication result. becomes. For example, assuming that the multiplication results are accumulated N times, the average value of this DC deviation is -0.
．． 5N, so if the value of the multiplication result itself is small, it cannot be ignored. Therefore, in order to eliminate DC deviation and minimize the influence of errors, it is essential to round the multiplication 4 results, but if you want to add a rounding function to the multiplier, you must add 1 by rounding. Since the carry input of adder 3 is already used even though it should be, there is a drawback that another adder has to be added, which complicates the circuit configuration. An object of the present invention is to configure the function of rounding multiplication results using a small amount of hardware means, and to economically reduce the influence of errors associated with multiplication and accumulation of finite bits.

For this purpose, the present invention adds a rounding function for multiplication results to the adders belonging to the accumulator, thereby making it possible to perform additions of 1゜゜1゛ by rounding without increasing the number of adders. It is characterized by its configuration.

The present invention will be explained below with reference to FIG.

FIG. 3 shows part of a series-parallel multiplier followed by an accumulator.

The series-parallel multiplier 14, shown as a rough block in this figure, has the same configuration as the one shown in FIG. That's what happened. As shown in FIG.
The least significant bit data 18 of the four outputs corresponds to the value of the first decimal place of the multiplication result, and after these least significant bit data 18 are sequentially latched into the D-type flip-flop 15 at the rising edge of the signal B3, the signal BO During the output time, the signal is taken out from the NAND gate 16 and then inputted to the accumulating adder 8 via the NAND gate 17 as a negative OR together with the reset output of the D-type flip-flop 9.

That is, if the least significant bit data is “1”, “゜1” is added, and if it is “0”, “゜0゛” is added to the least significant bit of the multiplication result. A rounding operation is executed.Finally, a case will be described in which the present invention is applied to a DFT arithmetic circuit as an example.

The calculation of the absolute value IDFTl of DFT can be approximated by the following equation. However, Y1=COsn6)TlY2=S
innωTNX; transformed time function, ω = angular frequency, T;
is the sample interval time.

Here, if the truncation error in one multiplication is δA1 and the rounding error is δB, then the average value of the error of the cumulative result XA, IB
and the variance is as follows.

The result of the finite bit operation shown in equation (4)! DFT
1, the relationship with IDFTl is as follows.
心i &JI■1 However, Δ is the difference between the operation result in the case of infinite bits and that in the case of finite bits.

In the case of a truncation error, the calculation result has a variation of +2IN to 41Δ1〉, whereas in the case of a rounding error, it has a variation of 41ΔIΣ2
．． Since the variation remains at /j, the larger the value of N, the greater the effect of rounding, and the performance of the device that performs multiplication and accumulation is improved. As explained above, according to the present invention, the function of rounding the multiplication result is added to the adder belonging to the accumulator, and the multiplication and rounding circuit at that time can be realized with a simple logic circuit configuration. ``Addition of 1'' can be performed economically, thereby making it possible to economically reduce the influence of errors associated with multiplication and accumulation of finite bits.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a multiplication circuit and its peripheral circuits that truncate multiplication results according to the prior art, FIG. 2 is a diagram showing signal input/output timing in the main part of FIG. 1, and FIG. , is a diagram showing an example of a multiplication circuit to which a multiplication and rounding circuit according to the present invention is added and its peripheral circuits. 7... Parallel-serial converter, 8... Accumulation adder, 9, 1
5...D-type flip-flop, 14...1 series/parallel multiplier.

Claims (1)

[Claims] 1 2 in two's complement representation by bit-by-bit shift addition
A serial/parallel multiplier that performs multiplication of decimal data, a parallel/serial converter that converts the parallel multiplication results from the multiplier into series, and a link between the serial multiplication results from the converter and the previous accumulation results. In a circuit consisting of an accumulation adder that performs bit-by-bit addition, and a holding circuit that holds the carry output generated by the bit-by-bit addition from the adder as a carry input for the next bit addition, series-parallel multiplication is performed. A new holding circuit is installed to hold the rounded bit information of the parallel multiplication results in the accumulator to be given as a carry input when adding between the least significant bits in the accumulation adder, and the least significant bit information from this circuit is held as a carry output. A multiplication/rounding circuit characterized in that a carry output from a holding circuit for a multiplier is provided as a carry input to an accumulation adder via an OR circuit.