JPS6053472B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device provided with memory cells formed on a semiconductor substrate.

Conventionally, when forming memory cells on a semiconductor substrate,
Flip and flop circuits are often used in memory cells. The flip-flop circuit consists of two bipolar transistors (or MOS transistors) and two resistors.
It is composed of individual parts. Such flip and flop circuits are used in random access memories (hereinafter abbreviated as RAM). In addition, mask programmable, read, only, memory (MaskProgra
In the mmableReadOnlyMemory (hereinafter abbreviated as mask ROM), information is written using a contact mask, a wiring mask, etc.

As a result, it could only remember one type of information, and it was impossible to rewrite it. An object of the present invention is to provide a semiconductor memory device having both the functions of a mask ROM and a RAM.

Another object of the present invention is to provide a readable/writable semiconductor memory device that does not require the provision of a PN junction or special isolation region of an insulator between memory cells. To explain the present invention according to the drawings, in FIG. 1, a P-type semiconductor substrate 1 has a depth of 1.0 pTrL-15.0 μ
m) Selectively form an N-type emitter region 2 with a surface resistance of 30Ωl to 4000Ωl, and a P-type base region 3 with a depth of about 0, -7TL to 5.0PTrL in the emitter region 2.
, thus forming P-type channel stopper regions 4, respectively.

Next, in the P-type base region 3, there are N
An N* source region 6 conductive to the type emitter region 2 and an N* drain region 7 are formed in the P type semiconductor substrate 1 . 8
9 is a gate insulating film, and 9 is a field insulating film.

Next, an electrode wiring 10 is provided to connect the collector region 5 and the gate electrode 11 and connect it to the terminal A (a conceptual diagram is also used since this part only shows the connection state). Both base region 3 and drain region 7 are connected to terminal B, and source' region 6 is connected to terminal c. Terminals A and B are connected to terminal D via resistors 1 and R2, respectively (illustration of this portion is omitted). FIG. 2 is an equivalent circuit diagram of a unit memory cell of the semiconductor memory device of the present invention shown in FIG.

When a DC voltage is applied between terminals D and C, due to the difference in threshold voltage and switching speed between the bipolar transistor and MOS transistor, the bipolar transistor operates first and the potential of the collector terminal A decreases, resulting in N-channel enhancement. type MOS transistor is cut off) and the potential at terminal B remains high, so the base current of the bipolar transistor is supplied through resistor R2 and either terminal A or B is connected to the output of the memory cell. Since it is possible to write to a desired state using a wiring mask, a mask ROM can be formed using such a memory cell.

Next, when terminal A is held at low level and terminal B is held at high level, if a high level signal is applied to terminal A, MO
The S transistor becomes conductive and current flows from the drain to the source, and the terminal B becomes a low level, so the bipolar transistor becomes cut off and the terminal A remains at a high level.

When a high level signal is applied to terminal B, the bipolar ● transistor operates and terminal A maintains a low level. That is, it has a RAM function. Although it is theoretically possible to construct a readable/writable memory in the same way as the present invention by changing the characteristics or parameters of a flip-flop circuit using only one type of bipolar transistor or MOS transistor to make it unbalanced. Due to manufacturing variations in resistors and transistors, the state that is set when the power is turned on is highly probabilistic and cannot necessarily be determined uniquely. Increasing the imbalance would complicate the manufacturing process in the case of semiconductor integrated circuits and would also place restrictions on the degree of integration, which is not a good idea.

However, in the present invention, since both bipolar transistors and MOS transistors are used, the unbalance in characteristics becomes large and the operation is stable.

In addition, as in the case of using MOS transistors, insulation isolation between unit memory cells is required. An advantage of integrated circuits is that there is no need to provide special isolation areas for this purpose. This is the collector region of a vertical bipolar transistor.
This is because the structure is such that regions provided near the surface of the semiconductor substrate are directly connected. Next, another embodiment of the present invention will be described. In FIG. An N+ isolation region 13 is provided around the periphery to serve as the emitter region of the bipolar transistor.

Then, the P-type epitaxial layer 1'' surrounded by this emitter region is used as a base region.Other parts are similar to those in FIG. 1 and will not be described.The operation is the same as the embodiment shown in FIG. However, compared to using triple diffusion, the resistivity of the emitter region can be reduced, so bipolar
The current amplification factor of the transistor can be increased. Figure 4 shows
It is a cross-sectional view showing still another embodiment of the present invention, with a specific resistance of 0.
After forming an N-type epitaxial layer 15 with a specific resistance of about 0.1Ω-0 to 2.0Ω-0 on an N-type semiconductor substrate 14 with a resistivity of about 0.1Ω-d to 5Ω-d, a P-type base region 3 and a P-well 16 are formed.
, the channel stopper region 4 is formed, but the impurity concentrations of these three types of P-type regions may be different. Then N
An N+ type source region 6 is provided spanning both the + type collector 5, the N type epitaxial layer 15 (emitter region of a bipolar ● transistor), and the P well 16, and an N+ type drain region 7 is provided within the P well 16. It is clear that the equivalent circuit of this embodiment is also as shown in FIG. Note that in the P-type regions 3, 4, and 16, P-type impurities are diffused over the entire surface (or a P-type epitaxial layer is further formed on the N-type epitaxial layer 15), and then a P-type impurity is diffused from the surface to the lower N-type epitaxial layer. They may be formed separately from each other by forming N+ type regions that reach the same extent. This embodiment is particularly characterized by requiring a minimum number of steps. As described in detail above, according to the present invention, a readable/writable semiconductor memory device that operates reliably and has a high degree of integration can be obtained.
In addition, since information is written in a mask ROM using wiring, it is sufficient to stock the metal film at the stage where it is deposited over the entire surface, and then finally apply a wiring mask to complete the memory device. Another advantage is that the period from receiving an order to shipping is minimized.

[Brief explanation of the drawing]

FIG. 1, FIG. 3, and FIG. 4 are respectively cross-sectional views of the region structure (conceptual diagrams showing the wiring state) of the embodiments of the semiconductor memory device of the present invention.
, FIG. 2 is an equivalent circuit common to them. 1... P-type semiconductor substrate, 1''... P-type epitaxial layer, 2... N-type emitter region,
3...P type base region, 4...P type channel stopper region, 6...N+ type source region, 7...N+ type drain region, 8...・・・・・・
Gate insulating film, 9...Field insulating film, 10
... Electrode wiring, 11 ... Gate electrode,
12...N+ type buried area, 13...
N+ type isolation region, 15...N type epitaxial layer,
16...●●●P well.

Claims (1)

[Claims] 1 A bipolar transistor having a base region of another conductivity type formed in a semiconductor layer of one conductivity type, a collector region provided within the base region, and a source region of one conductivity type connected to the emitter region of the bipolar transistor. 1. A semiconductor memory device comprising a flip-flop circuit configured with an insulated gate field effect transistor.