JPS6053508B2 - television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a television receiver that can simultaneously display images of a plurality of channels on one screen.

Traditionally, the first new type of television receiver was
7-39273 (Japanese Unexamined Patent Publication No. 49-2419) etc., a device that simultaneously displays images of two channels, a main channel and a sub channel, on one screen has already been proposed and partially put into practical use.

However, such a television receiver can display only two images at the same time, and if more images are to be displayed simultaneously, a tuner must be added for the number of images.

Currently, in Japan, the number of broadcast stations that can be received in one area is nine at most, and if nine images are displayed simultaneously on one screen, it is possible to check all broadcast channels in that area at the same time. In this case, normally nine tuners and nine storage devices such as BBD or RAM are required.

The present invention provides a television receiver that can simultaneously display images of a plurality of channels on one screen using fewer tuners than the number of balloon images.

In particular, it is an object of the present invention to effectively shorten the tuning time interval when sequentially selecting a plurality of channels using one tuner in such a television receiver, and to obtain as continuous a video as possible. It is.

The present invention will be described below with reference to embodiments shown in the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and here, as shown in FIG. 2, one cathode ray tube is divided into nine parts, A, B, C, ..., I. , on which nine channels of images are simultaneously blown out. 1st
In the figure, 1 is an antenna, 2 is a tuner, 3 is a video intermediate frequency amplification circuit, 4 is a video detection circuit, 5 is a video amplification circuit,
6 is a video output circuit, 7 is a cathode ray tube, 8 is an audio detection circuit, 9 is an audio amplification circuit, 10 is a speaker, 11 is a synchronization separation circuit, 12 is a horizontal deflection circuit, 13 is a vertical deflection circuit, and 14 is a selection circuit. Station switch SW, SW2...
A channel selection operation unit has SW9, and 15 is a switching transistor TR.

, TR3...TR8, channel setting variable resistors VRI, VR2, VR3...VR9, and diodes D,,D. , D, . . . D9, which constitute a normal television receiver. In this embodiment, the television receiver configured with the above components is further equipped with a one-shot pulse generator 16, an electronic switching circuit 17, a 9-ary ring counter 18, a signal switching circuit 19, and an address counter 20.
, oil converter 21, storage device 22, AD9 converter 23, control signal generation circuit 2 sample hold circuit 25, oil converter 26, signal changeover switch 27, first storage circuit 28, second storage circuit 29, An upper bit comparison circuit 30, a sampling link clock generation circuit 31, a 112 frequency divider 32, a timing signal generation circuit 33, a trigger signal generation circuit 34 are added, and a multi-screen switch SWlO is provided in the channel selection operation section 14. It is.

Here, the one-shot pulse generator 16 generates a pulse signal for driving the 9-ary ring counter 18 based on the trigger signal from the trigger signal generation circuit 34.

If any one of the channel selection switches SW1 to SW9 of the channel selection operation section 14 is currently in the on state, the switching transistor TR1 of the channel selection circuit 15 corresponding to that switch is turned on, as in the operation of a normal television receiver. ~TR9 no 1
is turned on, the tuning voltage preset by the variable resistors VRl to VR, is supplied to the tuner 2 via the diodes D1 to D9, and the tuning switches SWl to SW9 are supplied to the tuner 2 via the diodes D1 to D9.
The corresponding channel is in reception status.

That is, at this time, the video signal received and processed by the tuner 2, the video intermediate frequency amplification circuit 3, the video detection circuit 2, and the video amplification circuit 5 is supplied to the cathode ray tube 7 via the signal switching circuit 19 and the video output circuit 6. Images of specific channels are projected on both sides. At this time, the audio intermediate frequency signal obtained from the video amplification circuit 5 is detected and amplified and then supplied to the speaker 10. The audio of the same channel is emitted from speaker 10. However, in this state, when desired, the multi-screen switch S of the channel selection operation section 14 can be pressed.
Wl.

If you turn on the channel selection switch SWl
-SW9- are all turned off, and at this time, the switching circuit 17 is turned on, the signal switching circuit 19 is switched on, and the amplification operation of the audio amplification circuit 9 is stopped. At the same time, a trigger signal is supplied from the trigger signal generation circuit 34 to the one-shot pulse generator 16, and at this time, the one-shot pulse generator 16 generates a clock pulse, and the clock pulse is transmitted via the electronic switching circuit 17. It is supplied to a 9-ary ring counter 18 and an address counter 20. In this way both counters 1
8, 20, 1 every time one clock pulse is input.
Step by step, the output is 1 → 2 → 3...9
→ 1 → 2, etc. are switched to L sequentially.

At this time, in the tuning circuit 15, the switching transistor T
Rl to M9 are turned on sequentially, and each variable resistor VRl to VR
, the tuning voltages set in tuner 2 are switched sequentially.
supplied to

As a result, in tuner 2, the variable resistor VRl~
Nine channels set by VR9 are sequentially and repeatedly selected and received. At this time, the video signals of each channel sequentially obtained from the video detection circuit 4 are converted into digital information by the AP converter 21 and supplied to the storage device 22.

Here, the storage device 22 is composed of a group of digital storage elements such as nine RAMs and has a storage capacity for nine screens, and the address counter 20 specifies the writing and reading positions thereof. In the storage device 22, the digital video information of each channel is extracted at a rate of one every three scanning lines based on the control signal from the control signal generation circuit 24, and one frame (one screen) is stored in the storage element at the designated address. Written in minutes.

Note that since the address counter 20 is driven by clock pulses in synchronization with the 9-ary ring counter 18, the video information of each channel is individually written into the same storage element. In other words, the video information of each channel written in each storage element is intermittently rewritten. Meanwhile, in the storage device 22, the address counter 20 specifies the video information of each channel from each storage element at a higher speed than the writing speed (in this case, three times the writing speed) based on the control signal from the control signal generation circuit 24. They are read out sequentially and repeatedly in the same order.

The digital video information of each channel read from the storage device 22 in this way is converted into an analog video signal by the DA converter 23, and then supplied to the cathode ray tube 7 via the signal switching circuit 19 and the video output circuit 6. As shown in FIG. 2, nine channels of images are displayed simultaneously on the cathode ray tube screen.

In this case, each image is intermittently switched to a new image, but the image remains a still image until it is switched. The inventors have confirmed through experiments that it is possible to fully understand the broadcast content of each channel with a still image of several seconds, although the video may have some strobe-like movement. Of course, it goes without saying that the shorter the interval between pulse outputs obtained from the one-shot pulse generator 16, the more natural the image will be. When the multi-screen switch SWlO is turned on in this way, the images of nine channels are displayed simultaneously on the cathode ray tube screen, and the viewer can easily watch the broadcast content of each channel without having to turn on the selection switches SWl to SW in sequence. can be known.

Note that in this case, since the operation of the audio amplifying circuit 9 is stopped, no audio is emitted from the speaker 10. After viewing the broadcast contents of each channel as described above, when the selection switches SW1 to SW9 of a desired channel are turned on, the multi-screen switch SW1 is turned on.

is turned off, the switching circuit 17 is turned off and the signal switching circuit 19 is switched back to its original state, and at this time the desired channel is continuously received and the image is displayed on the cathode ray tube screen. In the above embodiment, an example is described in which a digital storage element such as a RAM is used as the storage device 22, but of course an analog storage element such as a BBD may also be used.
It becomes possible to omit the 9 converter 23 and store the video signal obtained from the video detection circuit 4 directly in the storage element.

Further, in the above embodiment, the address counter 20 is stored in the storage device 2.
Although the address counters are used for specifying addresses when writing to and reading from 2, the address counters may be used individually for writing only and for reading only. In the present invention, in the above embodiment, the output signal of the one-shot pulse generator 16 for switching the output of the 9-ary ring counter 18 is effectively derived at as short an interval as possible in order to make the switching cycle of each image as short as possible. be. Now, in Fig. 3, each variable resistor VRl to VR9 has 1 Ch to
This figure shows an example of the relationship between each channel and the tuning voltage when the setting is such that each channel of 9 channels can be received.

Here, for example, by switching the output of the ring counter 18,
When switched from Ch to 2ch, variable resistor VR
Since there is not much difference between the tuning voltages set by VR2 and VR2, the tuning voltage supplied to tuner 2 reaches a predetermined value in a relatively short time and settles into a steady state, but after that,
When switched from Ch to 5Ch, variable resistor VR4
, VR5 is large, so it takes a considerable amount of time to settle down to a steady state. This is because the path for supplying the tuning voltage from each of the variable resistors (R1 to R9) to the tuner 2 has a time constant. Therefore, when driving the ring counter 18 with a clock pulse of a constant period, it is necessary to drive the ring counter 18 until it settles into the expected steady state when the displacement of the tuning voltage is the largest (in the example of FIG. 3, when switching from 5Ch to 6Ch). The period of the clock pulse must be determined by taking into account the time required for the ring counter 18 to complete one cycle. Therefore, in this embodiment, in order to improve this point, when channel switching is performed in the tuning circuit 15, if the change in tuning voltage is small, the channel is quickly switched to the next channel, and as a result, the image is displayed on the cathode ray tube. This is an attempt to switch the displayed still images as quickly as possible.

This operation will be explained below according to the embodiment shown in FIG.

FIG. 4 shows an example of the tuning voltage supplied to the tuner 2 in this embodiment, and shows that the time interval for channel switching is changed according to the change in the tuning voltage. There is. A part of the tuning voltage now obtained from the tuning circuit 15 is supplied to the sample and hold circuit 25,
The sample hold circuit 25 samples and holds the tuning voltage based on the clock signal from the sampling clock generation circuit 31, and the held tuning voltage is supplied to the pigeon converter 26. Ti, t2, in Figure 4
. . Ra . . . represents the time position at which sample and hold is performed. At this time, the digital output signal obtained from the AD converter 26 is transferred to the signal changeover switch 27.
The signals are supplied to the memory circuits 28 and 29 via the memory circuits 28 and 29, and are stored alternately in the memory circuits 28 and 29. Here, the signal changeover switch 27'Tf is alternately switched by a signal obtained by dividing the output signal of the ring clock generation circuit 31 by passing it through a 112 frequency divider 32. The respective digital signals stored in the storage circuits 28 and 29 are transferred to an upper bit comparison circuit 30, and a magnitude determination is made between the upper several bits of both digital signals. Here, to explain based on the operation explanatory diagram of FIG. 5, when switching from 1Ch to 2Ch, the tuning voltage changes from 9V to 10V, and the digital output of the two memory circuits 28 and 29 becomes 640100F.
and "60101σ1", and the comparison circuit 30 compares the binary codes of the upper bits corresponding to the weighting "°16-"8-"°4".

As can be seen from FIG. 5, in this case, the information in the upper 3 bits is the same and does not change, so in such a case, the output of the comparison circuit 30 drives the trigger signal generation circuit 34 with a critical time delay after channel switching. The one-shot pulse generator 16 supplies a one-shot pulse to the ring counter 18 . Also, when switching from 2Ch to 3Ch, the tuning voltage changes from 10V to 13V, so the digital outputs of the memory circuits 28 and 29 are '60V.
110r1 and ゜゜0101σ゛, and at this time, the code corresponding to the weighting ゜゜4゛ changes from 0 to 1.

In such a case, the trigger signal generation circuit 34 is driven with a time delay of channel switching π based on the output of the upper bit comparison circuit 30, and a one-shot pulse is supplied to the 9-ary ring counter 18. Next from 3ch to 4ch
When the switch is switched to , there is no code change in the upper 3 bits in the comparator circuit 30. Therefore, at this time, a one-shot pulse is derived from the one-shot pulse generator 16 with a time delay of π. Also, when switching from 4ch to 5ch, the tuning voltage changes relatively greatly from 15V to 26V. At this time, the code with weighting ゜16゛ changes from O to 1, and the code with weighting ゜4゛ changes from 1 to 0.

In this case, the trigger signal generation circuit 34 is driven with a certain time delay after channel switching, and the 9-ary ring counter 1
8 is supplied with a one-shot package. Similarly 5Ch
When switching from 6Ch to 6Ch, π, when switching from 6Ch to 7Ch, π, when switching from 1Ch to 8Ch, liver, 8C
A one-shot pulse is supplied to the 9-ary ring counter 18 with a time delay of π when switching from h to 9Ch for the first time, and 4T when switching from 9Ch to 1Ch. , π...4T
Channels are sequentially switched at predetermined time intervals of σ, and one cycle is performed at intervals of σ.

According to the television receiver of the present invention, as described above, the channel selection device uses an n-ary ring counter to sequentially select a plurality of channels at a constant period, and the video information of the plurality of channels B obtained in this way is transmitted to the plurality of channels. Since video information is written individually to memory elements such as R, AM, or BBD and read out sequentially at high speed corresponding to a predetermined position on the screen, the multi-screen switch can be turned on when desired. By simply doing so, the images of, for example, nine channels are simultaneously displayed on the cathode ray tube screen, and the viewer can instantly know the broadcast content of each channel without having to perform any channel selection operations, which is extremely convenient.

Furthermore, the television receiver of the present invention can be constructed using a smaller number of tuners than the number of images displayed on the cathode ray tube, so that the cost does not increase significantly and the size of the television receiver does not increase.

Furthermore, in the present invention, when switching channels, the change in the tuning voltage is compared and detected, and the interval of the pulse signal that drives the n-ary ring counter is changed according to this change, so each channel can be reliably received, and multiple channels can be received. As a result, the rewriting speed of multiple images simultaneously displayed on the cathode ray tube screen can be increased, making it possible to bring the image closer to a natural image.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the television receiver of the present invention, FIG. 2 is an explanatory diagram of a television screen displayed in the same embodiment, and FIGS. 3 and 4 are diagrams of the same embodiment. A tuning voltage characteristic diagram for explaining the operation, and FIG. 5 is an explanatory diagram of the operation of the same embodiment. 14...Tuning selection operation section, 15...Tuning selection circuit,
16... One-shot pulse generator, 18...
・Nine-adjustable ring counter, 19...Signal switching circuit, 20...Address counter, 21...AD converter, 22...Storage device, 23...D8 Converter, 24... Control signal generation circuit, 25...
・Sample hold circuit, 26...ADgi switch, 27...signal switching circuit, 28, 29...
... Memory circuit, 30 ... Upper bit comparison circuit, 31 ... Sampling clock generation circuit, 3
2... 1/2 frequency divider, 33... Timing signal generation circuit, 34... Trigger signal generation circuit.

Claims (1)

[Claims] 1. A channel selection means for sequentially selecting a plurality of channels at a fixed period, a storage means for individually writing and storing the video information of the plurality of channels obtained by the channel selection means, and a plurality of channels stored in the storage means. A television receiver comprising means for sequentially reading out video information corresponding to predetermined positions on the screen and capable of simultaneously displaying images of a plurality of channels on one screen, wherein the channel selection means includes an n-ary ring counter. 1. A television receiver characterized in that the ring counter is driven based on a pulse signal whose time interval changes according to a change in tuning voltage at the time of channel switching.