JPS6053898B2 - data processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing system, and more specifically, to a data processing system, and more specifically to data processing between a central processing unit (CPU) and a plurality of storage devices and input/output (I/0) devices. , a unidirectional bus or loop bus architecture for transferring instructions and other information.

Currently, what is called a microprocessor generally consists of three
It consists of four basic functional devices.

The first three are ROS (may be RAM) with hardware for incrementing, branching and linking.
A central arithmetic and logic unit (AL) with microinstruction address registers, associated registers, and a data bus.
U), and a device for addressing and transferring data to and from main memory (usually treated as an I/O unit and coupled with other system I/O devices). . In more advanced microprocessors, a fourth device is a separate section of the register and data bus for nested interrupt switching. This corresponds to an I channel. This channel may be configured to perform multimode or burst mode cycle stealing control (sometimes referred to as direct memory access or DMA). Current methods of configuring microprocessors can be divided into two with regard to the relationships between the above-mentioned functions and chips.

The first method divides each function into ALU chip, control chip, address chip, 1/0 chip and ROS/RAM.
A separate chip such as a chip (which may have an address control circuit built in) is responsible for the
The second method is to distribute processing functions to multiple identical chips. This second one is called the ``bit slicing'' method and generally requires a separate 1/0 control chip. Both schemes require a significant amount of wires to interconnect the chips, but the limited number of I/O pins available also limits the number of interconnect lines, thus limiting the number of interconnect lines. It is necessary to provide the same logical functions to the other chips.

Also, delays in off-chip drivers and receivers are a problem. If the data bus or address bus is bidirectional, between the driver and receiver of each chip,
No signal transfer occurs until the all-off state is set and then the all-on state is set;
Therefore, further delays will occur. Additionally, each bidirectional bus requires I/O pins and off-chip drivers, requiring a larger chip layout;
Furthermore, the power consumption in each chip also increases. In order to solve these problems, an architecture can be considered in which the address bus and the data bus are combined into one time division "unibus" and the delays of control and connection procedures (handshaking) are also combined into one. Therefore, optimal cost/performance requires a microprocessor architecture with a minimum number of drivers and receivers that can be packaged on a single chip with, for example, tin pin connections. Become.

The purpose of the present invention is to solve the above-mentioned problems.
For a computing system that includes a CPU local storage register unit (hereinafter referred to as LSR) with ALU related operand registers and an instruction decoding/execution unit, main memory, executable control storage, and one or more I/O devices. The purpose of this invention is to provide a new busbar architecture.

According to the present invention, only a few I/O line connections are required;
A loop bus architecture is thus achieved for a fully integrated microprocessor that can be packaged on a single integrated circuit chip.

The number of channel drivers required is minimized, but by allowing vibrating and overlapping operation,
Throughput is improved. The features of the present invention are summarized as follows. The present invention connects a unidirectional input bus for transferring instructions or data and a unidirectional output bus for transferring addresses or data inside a CPU,
It is characterized by a loop busbar configuration. According to the first aspect of the present invention, the input bus is connected to one input of an ALU provided inside the CPU, and its output is supplied to the output bus via the internal bus. By interposing the ALU in the middle of the loop bus in this way, input/output devices can share the ALU inside the CPU, and instruction execution can also be overlapped. According to the second aspect of the present invention, three storage devices are connected between the input bus and the output bus, and an extra auxiliary address bus is provided to address the third storage device (■ ball). provided.

The first storage device serves, for example, as a main storage device, and reads data to or writes data from the input bus in response to a first address on the output bus. The second storage device stores instructions to be executed by the CPU and reads the instructions to the input bus in response to a second address on the output bus. This may be ROS. A third storage device reads data received from the output bus to the input bus in response to a third address on the auxiliary address bus. The main function of this third storage device is as an LSR, but in the present invention, since there is no direct write bus from the CPU to the first storage device (main storage device), writing to the first storage device is not possible. This will be done via the third storage device. As described above, the present invention is characterized by the architecture of the loop bus, which allows the I/O of the chip on which the CPU is formed.
The number of pins and off-chip drivers can be reduced.

Furthermore, by controlling the read and write timings of various storage devices, overlap processing or vibe line processing becomes possible. Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIGS. 1A to 1C show the architecture of a computing system according to the present invention, which includes the following four steps.
Contains two major pieces of hardware.

(1) A CPU 9 including an ALU 22, channels (including input bus 10, output bus 20, auxiliary address bus 21, common ball bus 53, and control line 15), a plurality of registers, and control logic.

(2) LSRl4.

(3) Main storage device 12.

(4) Read-only storage (ROS) 16, also called executable storage or microprogram storage.

For example, the CPU 9 has 70 module I/0 pins.
A single LSI mounted in fewer packages than
It may be configured as a chip.

With current technology, such a CPU package is
16 module, an LSR 14 module (for example with 32 registers), 2 modules for the support drive 18 and an oscillator connected to line 59 (
(not shown) on one card. A portion of main memory 12 may also be mounted on this card, but given current circuit technology, main memory 12 will most likely be mounted on a separate card. . Data, instructions and I/0 commands are transferred between CPU 9 and other units by two unidirectional lines: I/0 common power bus 10 and I/0 common output bus 20.

Input bus 10 is connected to bus 1 from an I/0 device (not shown).
1 from the main memory 12 via the bus 17, RαI6
and from LSR14 via bus 13, respectively. Data on input bus 10 is sent to program register 30 and ALU 22. What is important here is that the CPU 9 only receives data and information from the input bus 10 and does not have a drive device for sending data to the input bus 10. In contrast,
The main storage device 12, LSRl4, and ROSl6 are equipped with a drive device for supplying data to the input bus 10, and the main storage device 12 is further equipped with a drive device for supplying data from the LSRl4 to the input bus 10 via the bus 13. data or I/
A device is also provided for receiving data supplied to the input bus 10 from the 0 device. I/0 common output bus 20 provides the contents of output buffer register 26 to ROS16, main memory 12, LSR14, and I/0 devices.

This common output bus 20 is connected to the ROS16 and the main storage device 1.
2, but acts as a data bus for LSR14 and I/0 devices. I/0
The device has six local storage code output (LCO) lines 2
Addressed by 1. These Ecchi lines or auxiliary address bus lines 21, in this embodiment, can store up to 64 local storage registers making up LSR14 or I/0 device 0.
It is now possible to directly address individuals. As previously mentioned, input bus 10 transfers data or microinstructions from I/O devices or storage devices. The sources and destinations for transfer via input bus 10 and output bus 20 are selected by a plurality of control lines 15 . Control line 15 is shown as control and clock line 19 after being driven by driver 18 . These control lines include the u-layer select line, the ROS select line, the main memory select line, the upper byte write line, the lower byte write line, and the like. I/0 device selection is accomplished by a combination of the valid device address on line 21 and the inactive R select output.
The timing for enabling data transfer via the output bus 20 is determined by one preceding clock pulse (one of the plurality of lines 15).
determined by the book). The validity of the LCO and selection code is indicated by the sample out signal. The sample in signal is a response to sample out or a command response from an I/O device to enable data transfer to CPU 9 via input bus 10. These 7 signals are! Together with Hold Clock In, which causes the /O device to prevent the CPU clock from advancing, the asynchronous 1/O
enable operation. 1/O interface line 10,1
9, 20, 21 and 53 are summarized below.

(1) Input bus 10: microinstruction from ROS16,
I/0 device and? 1PX.1 for transferring input data from Rl4 and input/output data of the main storage device 12. It consists of lines.

(2) Output bus 20: Consists of 1FSX lines for transferring data to the I/O device and LSR14 and supplying addresses to the main memory 12 and ROS16.

(3) Common ball bus line 53: Consists of 7 multi-cycle steal lines or 7 interrupt level request lines.

This will be explained in detail later. (4) LCO
Line 21: Addresses the location of LSRl4 up to the limit, informs the cycle steal level, or I/0
It consists of six lines for addressing up to six devices.

When the LSR selection line, which will be described later, is activated, the LCO
Addresses 0 to 63 specified by line 21 are LS
Address register locations 0 through 63 of Rl4, respectively. Register locations 16-23 are used for interrupts, register locations 24-31
is used for cycle steals. If the LSR select line is not asserted, addresses 1 through 63 on LCO line 21 address I/O devices 1 through 63, respectively. In this case, address 0 is reserved for the channel function. (5) Control and clock lines 19: This includes the following interface lines.

(a) Ball cycle - Steel output line 772 (one line) - By clearing the interrupt priority of the common ball bus 53, a cycle is made instead of an interrupt - A request is made to the steel ball common ball bus 53, and the cycle - Used to request steal priority.

(b) Selection output lines (5 lines) Includes each line for R selection, main memory selection, ROS selection, upper byte write, and lower byte write.

If a write is not specified, a read operation is implied.3.
be done. (c) Suncle/out line (1 line) Indicates that one command or E℃ signal is valid.

This occurs between clocks 3 and 4 and clocks 9-14, as discussed below.

4 ((d) Clock 1 or 9 output line (1 line) 1 Provides timing to validate the previous contents of the output buffer register 26 supplied to the output bus 20.

11 (e) Clock 6, 7 output or clock 14, 15 output line (
(for double cycle instructions) Gives the timing to display the end of one instruction.

(6) Oscillator input line 59: Provides a continuous square wave clock signal.

(7) Other interfaces Sample In (not shown) enable data provided by the selected device to the input bus 10 in response to Sample Out, or if the selected device specifies Contains one common line for responding to.

Cycle steal input line 68 is used by I/0 devices. The I/O device requests a cycle steal ball on the rising edge of the signal and indicates that its priority is valid on the common ball bus 53 on the falling edge. Interrupt input line 70 indicates that one or more devices have an interrupt pending on common ball bus 53. Its priority is common ball bus line 5
It is displayed as 3. A reset input (not shown) provides system reset and power-on reset. The upper byte store inhibit is generated from the I/O device to write only the lower byte to main memory 12. A low byte store inhibit is generated from the I/O device to write only the high byte to main memory 12. If both of these occur, a read operation of main memory 12 is implied. Storage data selection supplies data read from main memory 12 to input bus 10 . When this is inhibited, the I/O device can provide its data (which may be a main memory address) to the input bus 10 for writing to the LSR (Cycle Steal Address Register). ? R write control is used to chain data tables in main memory 12, or? Generated from the I/0 device to inhibit incrementing of the R address. Next, the CPU 9 will be explained.

In addition, the number j in the figure without a leader line has a poor number of bits. In the CPU 9, the input bus 11
to ALU 22 and program register 30? It is continued. The output of program register 30 is sent via line 33 to ALU 22 and instruction decoder:2. The address part of the instruction stored in the program register 30 (
6 bits) is passed through line 31 to the LSR control output (LCO
) register 40 and decrement register 38. The output of decrement register 38 is passed through line 39 to the program input signal.
The current condition code register 4 is returned to register 30.
8 and counting register 50. Counting register 50
The output of is passed through line 51 to decrement register 38 and LCO
It is sent to register 40. Current condition code register 48
The output of is sent to storage condition code register 4 through line 49.
Sent to 2. The outputs of current condition code register 48 and count register 50 are also sent to ALU 22 over line 43. The data flow of CPU9 is 16-bit 7
11d. U22 and two operand registers or line 3
5 via Al. Al. and an accumulation extension register 36 that can be gated on either side of U22.

Summing register 24 is the output buffer of ALU 22 and is loaded from bus 23.

Program register 30 holds microinstructions that are decoded and executed by decoder 62. The contents of program register 30 are also sent to ALU 22 over line 33. Furthermore, for address change and branch linkage operations,
The contents of microinstruction address register 32 may be gated to ALU 22 via line 29. Counting register 50 is used for counting shifts and indirectly addressing LSR14. The contents of count register 50 are transferred via line 43 to perform various operations to be described later.
can be gated to ALU 22. Output buffer register 26 holds data supplied to internal output bus 28. After this output bus 28 is driven by the drive device 18, it is treated as the I/0 common output bus 20. The contents of the output buffer register 26 are saved in location 0 of LSRl4 and input to the ALU 22 through the input bus 10 when required by specific instructions to be described below. The output (2 bytes) of the total register 24 is sent through the bus 25 under the control of the instruction decoder 62 to the microinstruction address register 32, the accumulation register 3, the extension register 36, and the error register 46 (lower byte). , interrupt mask register 44 (upper byte), count register 50
(lower byte), current condition code register 48 (higher byte), and output buffer register 26. The output of interrupt mask register 44 is on line 4.
5 and 43 to ALU 22 and further to interrupt gate (AND gate) 52 through line 45. The output of error register 46 is sent to ALU 22 over lines 47 and 43. The lower four bits of the output of summation register 24 may be gated through line 27 to the upper four bits of instruction address register 32 (used as page register 32a). Multiplexed cycle steal requests and interrupt requests on common ball bus 53 are sent to interrupt gate 52 and priority encoder 54 .

Cycle steals have higher priority than interrupts. The output of interrupt gate 52 is sent to priority encoder 54 over line 69. The output of priority encoder 54 is on line 5
5 to the current interrupt level register 56, upper level interrupt test circuit 58, and register 40. A signal on output line 63 of test circuit 58 forces a higher level interrupt. Current interrupt level●
The output of register 56 is passed through line 57 to upper level interrupt test circuit 58 and W. It is sent to the O register 40.
The clock signal provided on line 59 from the single phase oscillator is 4
It is sent to phase generator 60.

The output of the four-phase generator 60 is sent over line 61 to a clock device 66 and to an auxiliary clock device 64.

Both of these clock devices, in cooperation with the instruction decoder 62, control the operation of the CPU 9, such as bus gating to the various operand registers, time division of the various busses and registers, etc. Referring now to FIG. 5, the cycle steal/interrupt channel of a computing system according to the present invention will now be described.

Interrupt/Cycle Steel Ball Lines 530-53
6 constitutes a common ball bus line 53, which follows negative logic. Interrupt mask register 44 has output lines 450-456. Cycle steal ball dedicated latch 75 has a reset output line 80. The output of this latch 75 to reset line 80 is ANDed at interrupt gate 52 with the signal on line 450 corresponding to bit O of interrupt mask register 44.
gate 96), and then the result is NOR'd with the signal on line 530 representing bit position 0 of ball bus 53 (NOR gate 97). The output of NOR gate 97 is on line 52
0. Similarly, bits 1 through 6 of interrupt mask register 44 are output on lines 451 through 456, respectively.
is also ANDed with the signal on the reset line 80 of the cycle steal ball-only latch 75, and then the result is ANDed with the signal on the reset line 80 of the ball bus 53, corresponding to bit positions 1 through 6 of the ball bus line 53, respectively.
The signals on lines 31-536 are NOR'ed to provide the resulting outputs on lines 521-526, respectively. Line 520 connects to NOR circuits 86, 94 and 95; line 521 connects to NOR circuit 86,
90 and 95, line 522 to NOR circuit 86 and AND circuit 91, line 523 to NOR circuit 86 and 90, line 52
4 is connected to AND circuits 87 and 92, line 525 is connected to AND circuit 88 and NOR circuit 90, and line 526 is connected to AND circuit 93. The output of the NOR circuit 86 is passed through the most significant bit output line 544 of the priority encoder 54 to the AND circuits 87, 88 and 92, and the current interrupt code circuit 5.
A weight of 4 latch of 6 is sent to a test circuit 58 as well as an AND gate 82. The output of the NOR circuit 95 is sent through the middle bit output line 542 to the AND circuit 91, the weight 2 latch of the current interrupt code circuit 56, the comparison test circuit 58, and the AND♦ gate 82. The output of the NOR circuit 90 is sent to an AND circuit 93. In NOR circuit 95, the outputs of AND circuits 87 and 88 and lines 520 and 52
The signal above 1 is NORed. In the NOR circuit 94,
The outputs of AND circuits 91-93 and the signal on line 520 are NORed, and the output is passed through the least significant bit output line 541 to the weight 1 latch of current interrupt code circuit 56, comparison test circuit 58, and - Sent to gate 82. As is clear from the circuit configuration described above, the priority encoder 54
encodes a given level into a corresponding 3-bit code. The signal on the negative logic common cycle steal request line 68, which also serves as the bit position 47 of the cycle steal request, is inverted by the inverter N and then sent to the cycle steal ball latch 75? , set this.

The set output of latch 75 is cycled through line 77.
is sent to the steal response latch 76 and sets it.
The reset output of latch 75 provided on line 80 inhibits each AND circuit of interrupt gate 52 and also degates interrupt level switching latch 84. The output from interrupt level switching latch 84 to line 79 is used to control the new interrupt level load line 72 of positive logic and to set the current interrupt level setting line 73 of positive logic. A negative logic common cycle steal request line 68 is also connected to a cycle steal response latch 76 . The set output of cycle-steal response latch 76 is provided on line 55. This output is applied to the positive logic clock on line 85 in AND circuit 89. The result is passed through line 78 to AND gate 82 and L
Upper input bit lines 834 and 835 of CO register 40
sent to. Upper input bit lines 834 and 835 have
The output of AND gate 82 forces a predetermined code. The negative logic signal on the common interrupt request line 70 is sent to the cycle steal response latch 76, and after being inverted by the inverter N, the signal is sent to the interrupt level switching latch 84.
sent to.

The positive logic interrupt enable line 71 is connected to an interrupt level switching latch 84 . The positive logic lines 310 to 314 are the first
B represents the lower bit position of the address portion of program register 30, shown as line 31 in FIG.

The signals on lines 310-314 are individually ANDed with the signal on positive logic microinstruction set line 74 by AND gate 83 and then sent to register 40 through lines 831-835. The output of AND gate 82 is LCO
On the input side of register 40, line 8 in the lower bit position
31 to 833 are dot-ORed.

The three input lines of AND gate 81 are also connected to lines 831 to 8.
33 and are each dot-ORed. In AND gate 81, the output of current interrupt code register 56 provided on lines 561, 562 and 564 and the signal on current interrupt level setting line 73 are individually ANDed. The output of current interrupt code register 56 is also sent to comparison test circuit 58. Current interrupt code●The contents of register 56 are set to L.
The signal on current interrupt level setting line 73 that gates to the lower input line of CO register 40 is the same as the signal on line 78 to force a predetermined code onto upper input lines 834 and 835. However, this code is different from the forcing code by the signal on line 78, so output line 41 of LCO register 40 is provided with an address specifying a different register location in LSR14. As mentioned above, cycle stealing has a higher priority than interrupts, so the common cycle stealing request line 6
A signal on 8 sets the cycle steal ball-only latch 75, immediately canceling the interrupt polling that would normally be processed continuously, and alerting all 1/O devices to their cycle A request is made to provide steal priority to lines 530-536 of ball bus 53 and to cancel the interrupt request.

Deassertion of the signal on common interrupt request line 70 signals CPU 9 that all I/O devices have removed their interrupt priority bits from ball bus 53. When the common cycle steal request line 68 is deenergized and the cycle steal ball specific latch 75 is reset, the output lines 541, 54 of the priority encoder 54
2 and 544 are loaded into LCO address register 40 through AND gate 82 and lower input lines 831-833, while the cycle steal qualification bit on line 78 is loaded into LCO address register 40 through AND gate 82 and lower input lines 831-833; 835 into the LCO register 40. At this time, the cycle steal response latch 76 is set, so the cycle steal response (line 55) is
0 device is notified. Output line 41 of LCO register 40
The cycle steal register in u-plex 14, specified by the address supplied to bus 13, supplies the associated main memory address to bus 13.

This indirect address may be incremented by ALU 22 to retrieve or store I/0 data. The lowest priority cycle steal level requires no priority bits and its forced device address portion is set to 0 to allow all binary device addresses.
be made into At the beginning of a cycle steal operation,
The cycle steal ball private latch 75 is reset to resume continuous interrupt polling or sequential execution of microinstructions. The cycle steal ball-specific latch 75 only has to be reset first so that the I/O device can set the common cycle steal request line 68 again, so that sequential burst modes cycle steal If requested,
Latch 75 will be set again. Interrupt mask register 44 is degated whenever cycle steal ball private latch 75 is set. Asynchronous cycle stealing requests for 1/0 devices may be controlled by gating the microprocessor clock or by latching the common ball bus 53 to stabilize the priority circuitry.

Next, various components of the computing system according to the present invention will be explained in more detail.

1/0 unidirectional bus According to the present invention, when the unidirectional external input bus and external output bus are connected to form an internal closed loop centered on the ALU 22, without using an extra buffer register, By sharing the ALU and data buses with a minimal amount of control logic hardware, interrupt levels can be increased to handle internal processing, external 1/0 data changes, and more sophisticated multi-level interrupts and cycle stealing. Can switch and cycle ● steal ● address increment.

This is achieved by using unidirectional busbars for the input and output of the CPU chip 9.

Data and addresses are fed to the same output bus 20. The I/0 common power bus 10 is the only data input bus to the CPU chip 9. A main storage device 12, LSR14, and ROS16 are connected to this input bus/line 10. As described above, the input bus 10 is a unidirectional bus heading toward the CPU 9, but the main memory 12 stores the main memory address when the output bus 20 holds the main memory address.
Input) The bus 10 is used to read or write data. Input bus 10 also serves as an external input line connected to one input of ALU 22.

The output of ALU 22 is temporarily stored in summation register 24 . The summation register 24 is connected to one common output bus 25 that connects all the registers inside the CPU chip 9.
have. This bus 25 outputs the output to the CPU chip 9.
The bus 28 is connected to the bus 28 via an output buffer register 26 for supplying the driver 18 externally.
When it exits, it becomes the I/0 common output bus 20. In this embodiment, the I/O common output bus 20 is a 2-byte bus, and
Data is supplied to LSRl4 and a number of I/O devices (not shown). Output bus 20 also serves as a time-shared address bus for main memory 12 and ROS16 (which may be a writable control store in which instructions to be executed are stored). Thus, in a data processing system according to the invention, an input bus 1 for supplying data and instructions is provided.
A unidirectional bus architecture is used in a loop structure consisting of an output bus 20 supplying 0 and data and addresses. Although there is no data bus for directly supplying data from the CPU chip 9 to the main memory 12, this problem
C to selected register location in LSRl4
In addition to loading the results from the PU 9, the unidirectional input bus 10 is also used for data transfer in the opposite direction between the main storage device 12 and the I-SR14.
(indicated by a double dashed line in FIG. 1A).

Thus, each time an internal data modification microinstruction is issued, the resulting data on output bus 20 can be arbitrarily set into a selected local storage register of LSR14 without requiring any extra instructions or time. By doing so, the unidirectionality of the input bus 10 toward the CPU chip 9 is maintained. Such an arrangement allows vibrate and simultaneous operations on both buses, input bus 10 and output bus 20, while a previous microinstruction is being executed using data on input bus 10. , output buffer register 26 stores the next microinstruction in ROSl6
It can hold an address to retrieve from.
The output buffer register 26 is also used to directly access main memory 12, and between these two address modes for main memory 12 and ROS16, a separate narrow bit-width data window is provided. Data is transferred to the local storage register or 1/0 device addressed by the provided 6-bit mini-address bus 21. This data window also reports each cycle steal response and switches interrupt levels. By setting aside one of the 64 local storage registers as an output bus image register, the data flow within the CPU chip 9 can be organized around the common AL and U.

In this case, the summation register 24 provides all other internal data and addressing registers and external devices via the output register 26. In this way, any external I/O device, AL, U22
can be shared with devices for internal processing. The unidirectional outer loop bus allows direct memory channel accesses (cycle steals) to be performed by switching interrupt levels and automatically incrementing storage addresses over a common ALU and data bus. Internal transparency of the CPU chip is achieved.

The loop bus architecture allows for overlapping instruction execution and bi-line processing.

Here are some examples of this: In the first example, R.O.
Vibration processing occurs whenever an S instruction is on the input bus 10 (usually at the beginning and end of each microinstruction cycle), when the I/0 common output bus 20 is
Start sending data to the I/0 device.

In a second example, data is sent from the I/O device or disk 14 to the input bus 10, . An overlap operation is performed during internal processing using AL, U22. At this time, there is a ROS address on the output bus 20, and therefore the next instruction is being accessed. In the third example, the result of the previous instruction execution is stored in LSRl4, and
An overlap operation is performed when starting execution of a new instruction.

LSRl4 is loaded during clock 1 of the new instruction cycle, while execution of the new instruction begins at clock 0. The six output lines 41 of the LCO register 40 are
Depending on what type of instruction is being executed, the LS
It constitutes an auxiliary address bus 21 that is used to address up to eight I/O devices or sixty-four half-word locations of Rl4. By using this auxiliary address bus 21 in combination with the loop-structured input/output buses 10, 20, multiple operations can be performed during one cycle. During the execution of an instruction, an I/O device may supply data to the input bus 10 or receive data processed by the ALU 22 while being addressed via the auxiliary address bus 21. Arithmetic or logically modified data on the output bus 20 can be referenced. This is a simple I/O that does not involve ALU operation.
This is an advantage over conventional channels, which require three instructions to perform a data transfer. In a conventional channel I/0 data transfer, the processing unit first sends the common 1/O bus address, then the I/0 device
It responds to the processing device via an acknowledged interface to indicate that it recognizes the address.
Another instruction is required for the processing unit to issue a command. The I/0 device also responds to commands out from the processing device. Once this is done, the processing unit executes the third instruction, a read instruction or a write instruction, depending on which direction the data is to be transferred. The 1/0 common output bus 20 is multiplexed so that overlapping operations can be performed for all instructions to be executed.

Here, "overlap" means that while the processing unit is processing the current instruction internally, the next instruction is accessed from the instruction storage device, ROS16. For example, 5 clocks of an instruction cycle consisting of clocks 0 to 7 (8 clocks) R
This is done by addressing OSl6 and allowing the remaining three clocks to send data to LSRl4 or the I/O device. Main Memory 12 Main memory 12 is an addressable memory for storing data from both the microcomputer and the 1/0 device.

Data is transferred between main storage 12 and 1/0 common human power bus 10 via bus 11 in both read and write modes. Clock and control signals for main memory 12 are provided on line 19 and addresses are provided on I/0 common output bus 20. Whenever main memory 12 is accessed, extra cycles are added to make the instruction a double cycle instruction.

As explained later, in the first cycle,
Incrementing, decrementing, or other address changes are made to the main memory address pointer obtained from Rl4 or expansion register 36. (Even if continuous pointers are not used, the automatic increment/decrement system for addressing is as functional as continuous pointers, allowing continuous operations.) Main memory A read or write to device 12 is performed in the second cycle after the main memory address pointer has been updated to obtain a new effective address. This address is used in the second cycle (
It is held in the output buffer register 26 during the main memory memory cycles) and addresses the main memory 12 in eight clocks. The main storage device 12 operates in the Vibration system as follows.

During a main memory 12 fetch operation, data is sent from main memory 12 to input bus 10 and loaded into one internal register of CPU 9. This data is stored at the end of the fetch operation (clock 0).
When the next instruction cycle is about to begin, it is gated through AL, U 22 to the summation register 24 and then transferred to the output buffer register 26. When data is set in the output buffer register 26, the current main memory address is destroyed. ROSl6R
The OS16 (sometimes referred to as executable control storage) stores executable instructions that make up the microcomputer's control program. There is.

After these instructions are read to input bus 10, they are temporarily stored in program register 30 and subsequently decoded by instruction decoder 62. Instruction decoder 62 cooperates with timing circuits to control gates, registers, and manipulation circuits to execute various instructions. ROS16 also operates in a vibrating manner.

At clock 0, which is typically the beginning of each microinstruction cycle, input bus 10 to program register 3
The command is set to 0. At the same time, data is set in the output buffer register 26. Thus, R addressed by the address on output bus 20
The reception of data supplied from the OS16 to the input bus 10 and the destruction of the address on the output bus 20 are performed simultaneously. Inherent delays in the circuitry including drive circuits and logic circuits result in vibline processing such that these operations are performed simultaneously. LSRl4 LSRl4 contains multiple addressable and modifiable register locations.

When data is addressed via line 21,
It is written to the LSR14 from the output bus 20 or read to the input bus 10. The data read to the input bus 10 is sent to the main storage device 12 or the CPU 9. L.S.
Location 0 of Rl4 is reserved for storing data in output buffer register 26, under conditions described below. AL, U22 The ALU 22 is used to perform data processing, microinstruction address incrementation, displacement branches, subroutine concatenation, main memory addressing, address modification, data fetching or storage, interrupt handling, and cycle stealing operations. , shared in a time-sharing manner.

When an overflow occurs in ALU 22, line 6
An overflow signal is output to 5. Line 67 is supplied with a carry or borrow. Time-sharing use of ALU 22 is enabled by integrating address registers 32 and ALU data flow and by using LSR14.

Address register 32 (a non-incremental, simple polarity holding register) stores the ROS instruction address in increments or . is changed every half cycle. U22 is time-divided.
Positive or negative displacement branches and connections are AL
Simplified by a single data bus to U22. A
Since the output from LU 22 is sent towards output bus 20, the micro address is used as an interrupt return pointer.
S) May be stored in Rl4. Similarly, u ball 14
Data read from to input bus 10 is gated through ALU 22 to address register 32 so that a new interrupt routine pointer can be loaded or a previously interrupted routine pointer can be restored; Then,
An extensible priority interrupt structure can be included within the basic ALU data flow. ? One location of Rl4 (location 0) is used for storage and playback of the contents of the output buffer register 26. C.P.
U9 maintains the hand storage address from the selected register location of LSR14 or from an operand register, such as extension register 36, for simultaneous access and update. It then fetches data from main memory 12 and stores it in internal operand registers via input bus 10 and ALU 22. Microprocessor data to be stored in main memory 12 resulting from the execution of a previous microinstruction is first transferred to the selected register of LSR14 via output buffer register 26.
sent to location. Data stored in LSR14 is gated towards input bus 10 and then written to main memory 12 by the main memory write microinstruction. In addition, some locations in LSRl4 also serve as indirect main storage address registers for direct 1/O device cycle steal operations.

In this case, one register location is allocated for each priority level. The 1/0 device has its own data length counter.

Addresses main memory 12 to write I/0 data on input bus 10 to main memory 12 or to read data from main memory 12 and transfer it to input bus 10.
0, the contents of the main memory address register in LSR14 are automatically incremented in ALU 22 and transferred towards output bus 20 via ALU 22 and output bus 20 towards the I/O device. Sent. The I/0 device receives data from CPU 9 via output bus 20 and sends data to CPU 9 via input bus 10. Covered? ALU 22 is used to decode emulated instructions.

The 0P code of the instruction being emulated is ROSl
6 is added by ALU 22 to the current instruction address in address register 32 to obtain a displacement pointer pointing to the table immediately below the current instruction being executed. In this way, a 256-way branch is obtained for the ROS16 instruction to execute the emulated instruction. Instruction address register 32
Interrupt switching occurs via the same data bus for basic instruction execution. The instruction address in the instruction address register 32 is Al
．． U22, total register 2 internal bus 25, output buffer register 26 and output bus 20, Rl4
is memorized. Thus, when an interrupt occurs,
Is there a pointer to the next instruction that would have been executed at the current program priority level? Stored in Rl4. The highest level to be executed is then determined by using the priority code produced by priority encoder 54 to generate an address in LCO register 40.
The LCO register 40 contains the RO register for this interrupt level.
L containing a pointer to a subroutine in Sl6
Addresses a specific register location in SRl4. The pointer read from LSRl4 points to the subroutine for the interrupt level to be executed.
input bus 1 before being stored in address register 32 and output buffer register 26 for reading from l6.
0 to the CPU chip 9, and AL. U
22 to the summation register 24. When interrupt processing is finished, the current interrupt subroutine pointer is set to LS.
It is stored in Rl4 and the address pointer for the interrupted program is retrieved from there. Program Register 30 The program register 30 is a buffer for the current instruction, and is a buffer for the 0P of the instruction being executed by the CPU chip 9.
Keep the code.

Instruction count fee stored in program register 30. The field or address field may be gated directly into the decrement register 38 and LCO register 40. Total Register 24 The total register 24 is the AL. Upon receiving the output of U22,
This is loaded onto the bus bar 25.

This operation is performed at least twice during each instruction execution cycle. Once, the address of the next instruction to be executed is received and loaded onto the bus 25, and once
The AL. It receives it from U22 and loads it to the bus 25.

While the data from the ALU 22 is temporarily held in the summation register 24 and then sent to the output buffer register 26 for temporary storage there, certain operations can be performed on the input bus 10.
It is possible to simultaneously perform another operation on the output bus 20.

Such two-stage buffering in the loop enables overlap operations and vibe line processing. Instruction Address Register 32 The contents of instruction address register 32 are modified by ALU 22 during each instruction execution to retrieve the next instruction to be executed from ROS16.

Accumulation Register 34 and Extension Register 36 The accumulation register 34 and the extension register 36 are each 16-bit working registers, and are used for arithmetic shifts, logical shifts left or right, left shift counting, or left or right shifts. Provides 32 bits of capacity for instructions that use shift operations such as rotation in direction.

These registers, like count register 50 and output buffer register 26, are internal operand registers and can be directly addressed by microinstructions to perform arithmetic and logical operations within the microprocessor.

The contents of these registers can be changed by the contents (eg, operation results) stored in the external LSR14 or one of the other internal registers. Output Buffer Register 26 The output buffer register 26 has dual functionality.

When serving as an operand register for ALU 22, output buffer register 26 holds data as directed by the microprogram. Also, on interrupts or DMA cycle stealth accesses that force address pointer transfers, both the address and data must be transferred through the output buffer register 26. To ensure that the data placed in the output buffer register 26 by the microprogram is not lost, register location 0 of LSRl4 is used when the microprocessor changes instructions, addresses, and data during interrupt control or cycle steal operations. is used as an image register corresponding to output buffer register 26. The contents (operands) of the output buffer register 26 stored in register location 0 of LSR14 can be returned to the output buffer register 26 after completion of the interrupt processing or cycle steal operation. Therefore, it is not necessary to provide an extra buffer up register for the output buffer register 26 on the CPU chip 9. Power Drive 18 Information on bus 28 is sent from chip 9 via power drive 18 towards output bus 20 .

In LSL chips, each driver can only drive one load. Therefore, since the output bus 20 is a common bus connected to a large number of units (loads), re-energization (RepPower) is required. (In performing this re-energization, the expansion of the number of channel lines is accomplished by encoding the existing lines to up or down levels during different clock periods of each eight-clock microinstruction cycle. Decrement register 38 The decrement register 38 is used for all shift instructions, multiplication instructions,
It is used to perform counting operations in divide, decrement, test, and branch instructions.

Decrement register 38 is used to decrement the program level when a direct shift to a 32-bit position is requested. It receives an input from register 30 and returns a decremented value to program register 30. In an indirect shift in which the contents of the count register 50 become the shift count value, decrements by 1 are performed as in the case of a direct shift, and the decrement register 38 is decremented and the reduced value is returned to the count register 50. Hold this before. In this embodiment, the maximum shift is 32, so a 5-bit decrement register 38 is sufficient.

However, for field length counting, counting register 50 is also used. To perform this operation, a decrement operation using 8 bits is required. This is 5
This is accomplished by cycling the bit decrement register 38 twice, first taking a 4-bit character from the count register 50, decrementing it, and storing the carry in the fifth bit position. . The stored carry (if there is a carry) is decremented and returned to the count register 50 along with the upper 4 bit characters from the count register 50 to form an 8-bit decremented value. It will be done.
LCO Register 40 The LC0 register 40 addresses a register location in the I/O device or LSR14, depending on what data is being transferred.

Current Condition Code Register 48 The upper four bits of the current condition code register 48 hold four condition codes and the lower four bits hold four programmable indicators (flags).

These bits constitute the unconnected upper byte of counting register 50. Four condition codes are set for each arithmetic operation for subsequent field concatenation operations. The four conditions are binary carry, two's complement overflow, two's complement minus, and accumulation. It is a non-zero indicator.

Once the last non-zero indicator is set for any field length, it remains set until changed by a microinstruction. Count Register 50 The count register 50 is the second ALU operand register, but may also be used as a shift counter.

The shift count value initially stored in the count register 50 is
It is decremented each time the accumulation register 34 or extension register 36 is shifted. A similar decrement occurs when 34 and 36 are interconnected to perform a double precision shift operation. In the left shift count instruction, the shift operation is aborted as soon as the upper bit is found, and the value held in count register 50 indicates how much of the shift has taken place. Therefore, this value becomes an indirect address pointer to ROSl6 or LSRl4 in many operations. Thus, counting register 50 can be loaded from internal bus 25 and also from I/0
To address the device or LSR14, its contents are A[. It can be changed in U22. The modified result is loaded into the register 40, which causes the above-described addressing via the bus 21. For indexing in address calculations and calculation of effective addresses, the contents of counting register 50 are stored in Al. Used as a positive or negative displacement to be combined with data by U22.

The combined result is stored in any internal register on LSR14 or CPU chip 9. Storage condition code/
Register 42 The output of current condition code register 48 is selectively buffered into save condition code register 42.

The basic condition codes set as a result of an ALU operation are overflow, carry-borrow, and cumulative (CumuI).
active) is non-zero and negative. The current condition code is set for the latest operation result by the microinstruction. In a full left shift, the high order bits are shifted towards the current carry indicator. In left shift counting, the high order bit may set the current carry indicator. Loads, stores, logic, increment, decrement, jump and branches do not change the condition code. register 42
The condition codes at and 48 can be cleared separately and can be individually tested by jump instructions. In addition to these condition codes there are four program control indicator bits which are stored in the current condition code register 48 along with the current condition code. When a microinstruction is being emulated, the correct current microlevel code is transferred to the save condition code register 42 to save the microlevel condition code of the language being emulated at the microlevel. Interrupt Mask Register 44 The interrupt mask register 44 contains the current mask status of allowed interrupt levels.

The contents of this register 44 are also stored in AL. Changes by U22,
Storing to LSRl4 or returning from LSRl4 is possible. Error ● Register 46 Interrupt mask ● Register 44
The lower bit of 1 is used for error control and automatic recording.
Configure the byte error register 46.

Machine check errors that can be automatically logged include, for example, parity errors in instructions fetched from ROS16.
Error, data error from LSRl4, input bus 1
Parity error in data from main memory 12 detected by parity check on 0, parity error in data received from one of the I/0 devices, when the I/0 device is microprocessor 9 channel stop conditions such that the I/O device is not connected to or the I/O device does not advance the microprocessor 9 to the next microinstruction, and an I/O instruction is issued to an I/O device that does not exist and thus There are time-out errors that occur when the address is not discoverable. Any of these errors can be set in error register 46, and can also be modified, saved, tested, or stored in LSR14. These errors are automatically set by the hardware to either retry the operation or abort the current operation and proceed to a subroutine that provides a signal to the console.
Highest level in microprocessor 9 (level 7)
force an interrupt. The four-phase generator 60 and clock devices 64 and 66 receive input via line 59 from a single-phase oscillator (not shown) and have two clock devices, a basic clock device 66 and an auxiliary shift/timer. - Drive out clock device 64.

The basic clock unit 66 is a two-phase clock unit that can be stopped every two clock positions and has eight clock decoding positions provided by four overlapping latched states, and eight clock decoding positions for each microinstruction cycle. Generates a clock. The basic clock device 66 also has an upper latch location (flip-flop) 66a that is used when the microinstruction being executed requires double cycles, that is, when the main memory 12 is accessed. There is. When the main memory device 12 is accessed, the basic clock device 66 generates the same eight clocks as in the first half in the second half of the double cycle, but at this time, these eight clocks are Output as 8 to 15. Clock generation from base clock device 66 is controlled by clock decode 676b. The auxiliary clock device 64 also
It has an upper flip-flop 64a and an auxiliary clock decode 64b, but the decode 64b provides four separate time slots. Furthermore, the upper flip-flop 64a is used when two runs are executed, which is the maximum timeout of the auxiliary clock device 64, that is, when the clock generation cycle is repeated twice (equal to one instruction execution cycle). Ru. Auxiliary clock device 64
is used whenever a shift, multiplication, or division operation is performed. The basic clock device 66 clocks the seventh clock position (
It is stopped at clock 6). This allows performing a cycle steal operation in the middle of a shift, multiply or divide extended operation. Auxiliary clock device 64 is I/0
It is also used for timeouts in case a device is not responding or to perform a connection procedure in case one of the I/0 devices connected to the input bus 10 wants to exchange data. be done. If the timeout exceeds the allotted time, auxiliary clock unit 64 stops generating the clock and registers error register 4 to initiate the highest level interrupt, the machine check interrupt.
Set the indicator to 6. Integrated Cycle Steal/Interrupt Control Channel Referring to FIG. 5 in conjunction with FIG. It is controlled by the ball generatrix 53.

In this embodiment, the common ball bus 53 is 7 bits wide and is configured to serve requests for seven interrupt levels above the current executable program level. Therefore, the system as a whole has a ratio of 8. There will be a level of inclusion. Connections between I/O devices and the seven prioritized interrupt request lines are arbitrary, and any I/O device may be connected to any interrupt request line. Figure 5 Cycle● Steel●
Ball-specific latch 75 is set. Polling for interrupts is continuous, except when a cycle steal operation is performed. The I/O device is the CPU
9, the signal is sent to the assigned priority bit lines 530-536 of the common ball bus 53.
Make a request. A number of requests may be sent to the priority encoder 54, where the highest level request is encoded into a 3-bit code specifying one of eight priorities and sent to the line. 541,54
2 and 544. Interrupt priority is also controlled by interrupt mask register 44. If the interrupt mask register 44 is set to allow interrupts, the interrupt request will be sent to the interrupt gate 5.
2 through an AND circuit 96 to the priority encoder 54 where the priority of this requested interrupt is encoded. The encoded interrupt level is compared in a comparator 58 with the current interrupt level stored in a 3-bit current interrupt level register 56. The contents of register 56 are compared with each new level encoded from priority encoder 54 to see if the new level is superior to the current level. If the new level is higher than the current level, the next instruction in the current program chain is not executed and the current register pointer in instruction address register 32 is the register location for the current level in LSRl4. will be forwarded to. Next, a new level ● pointer? R
l4 and placed into instruction address register 32. The LSR address (one of eight possible interrupt pointers) for the interrupt routine is obtained as follows. First, the three least significant bits from current interrupt level register 56 are sent through lines 561, 562 and 564 and gate 81 to input lines 831, 832 and 833 of LCO register 40, respectively. Interrupted pointer? Rl4
The remaining bits of the LCO address to store are:
Loaded from current interrupt level setting line 73 to upper input lines 834 and 835 of LCO register 40. LSRl4
Similarly, the new pointer to the interrupt register in L
Loaded into CO register 40. In this case, the upper input lines 834 and 835 are loaded from the current interrupt level setting line 73, while the lower input lines 831 to 833 are loaded with the encoded new interrupt level by the signal on the new interrupt level load line 72. , is transferred from the priority encoder 54 to the current interrupt level register 56, and then this register 5
Loaded from 6. As a result, the LCO address is changed to the address of a register location in LSRl4 that contains a pointer to the occasional subroutine (located in ROSl6) that handles the selected level interrupt. L
The address pointer taken from SRl4 is . AL
, U22 and summation register 24, output bus 20
and the instruction address register 32. When the new interrupt level subroutine finishes executing, the branch
An out order is issued. This instruction restores a pointer to a previously interrupted program. Since the above-mentioned subroutine that handled the interrupt resets this interrupt, there should be no request for the same interrupt. If another interrupt at the same level or a higher level is requested, the program does not return to the original interrupted position but processes this new interrupt request. This allows nesting up to eight interrupt levels. Also, for each interrupt level, there may be multiple sublevels. Once a given interrupt level is detected, the interrupt level status word (IL
SW) command is issued to all, for example, 16 I/0 devices.

One I/O device requesting service at any interrupt level must identify itself. (In this way, for each of the 8 interrupt levels, 16 sublevels can be obtained,
The total number of interrupt sublevels is 128. ) The interrupt level status word received in one of the registers in the microprocessor can be used to determine which of the I/O devices is requesting service at this level. This is done by one left shift count instruction. The first bit of the most significant bit stops the execution of the left shift counting instruction, and the counting register 5 at this time
A count of 0 indicates the location of the subroutine for the I/O requesting service. The common ball bus 53 is also used for cycle steal operations, in which case all interrupt requests must first be cleared.

The I/O device requesting a cycle steal sets the common cycle steal request line 68 to a negative logic level. This will recycle ●Steel●
Once the ball-only latch 75 is set, the cycle steal ball request line 77 is immediately pulled up, forcing I/O devices to pass their interrupt requests to the common ball bus line until the cycle steal operation is complete. Request to be removed from 53. Common interrupt request line 70 and common cycle steal request line 6
8 is disabled by all I/O devices, cycle steal response latch 76 is set on the next clock 0. This indicates that a cycle steal priority exists on common bus 53 for the I/O device requesting cycle steal. This cycle steal priority is interrupt mask ● gate 5
2 and directly to the priority encoder 54. A 3-bit encoded LCO priority address is generated from the priority encoder 54, and the AND circuit 82 opened by the output from the AND circuit 89 and the LCO
Through the lower input lines 831 to 833 of the register 40,
It is sent to the temperature register 40. At the same time, the upper byte or (only the low byte may be set), the LSR associated with the level of cycle stealing requested
Certain high order bits addressing the pointer in l4 (used as the main memory address) are also loaded into the LCO register 40. In this mode, the interrupt level is only delayed by the occurrence of a cycle steal instruction, regardless of whether it is at the program level or a higher level. The contents of interrupt level register 56 remain unchanged. As mentioned above, storage accesses are performed using the lower three bits indicating which of the eight cycle steal levels are allowed, and a half-word register in LSRl4 that holds the indirect memory address. This is done using a pointer from the ■°C register, which contains the high-order bits that give the displacement.

The indirect memory address is from LSRl4 to input bus 10.
and AL. After being incremented by U22, it is sent to the output buffer register 26. The incremented address on output bus 20 is ? during main memory 12 access. Can be written back to the corresponding cycle steal register in Rl4. Also, cycle steel
To keep the address intact, cycle ● steal ●
The I/0 device that receives the acknowledgment for the request shall:
This writeback can also be prohibited. If the 1/0 device allows read selection of main memory 12 and disables write pulses supplied from microprocessor 9 to control line 19, after accessing main memory 12, the data will be removed from main memory 12. It is successively outputted to the input bus 10. I
/0 devices can provide their data to input bus 10 for writing to main memory 12. In this way, the I/0 device is completely in control of incremental or non-incremental operations and read or write modes by the ALU 22. In the write mode, even after the write operation is completed, the I/O device can sense its data on the output bus 20 for the next clock 1.
In read mode, data read to input bus 10 is passed through ALU 22 and summation register 24 to output buffer register 26 and then to output bus 20.
is output towards. Although all I/O devices are connected to the output bus 20, in read mode, data on the output bus 20 is received only by the cycle, steal, level, and code supplied to the six LCO address lines 21. Only the 1/0 device recognized the . After this, the microprocessor either returns to the normal instruction execution sequence or returns to processing the interrupt routine that was suspended due to this DMA (ie, cycle steal) cycle. Timing The timing for executing microinstructions will now be described with reference to FIGS. 2A-4C.

Since all microinstructions have similar execution timing characteristics, we will first provide a general description followed by a detailed discussion of each instruction type. The meanings of the symbols used in FIGS. 2A to 4C are as follows.

A = Accumulation register 34 B = Extension register 36 BI = Input bus 10 C = Current condition code register 48 E = Error register 46 1 = Interrupt mask register 44 1/0 = I/0 device L = LSR14 M = Output Buffer register 26 N = Count (shift count) register 50 P = Program ● register 30 PCC = Storage condition code ● register 42 R = ROS16 STO = Main memory 12 T = Total register 24 7U = Instruction address register 32 Clock The cycle is divided into eight different clocks 0-7.

Clocks 8 to 15 are repeats of clocks 0 to 7, and are generated only when the main memory device 12 is operating (including DMA). The eight clock basic instruction cycle is divided into two parts related to ALU 22 utilization.

From clock 7 to clock 2, AL. U22 is used exclusively for incrementing or modifying instruction address register 32. In clocks 3 to 6, microinstruction processing is performed. In this way, one instruction execution cycle is divided into a half cycle for instruction execution by the ALU 22 and a half cycle for updating the instruction pointer, and the ALU 22 is continuously used by repeating these half cycles. . The basic window in which the address for ROS16 appears on the output bus 20 begins at clock 3, when the calculated new address
A pointer is loaded from ALU 22 into summation register 24 and transferred towards output buffer register 26. This address does not change until the next clock 0 is reached. At clock 0, output buffer register 26 is modified to contain data for sending via output bus 20 to LSR14 or any I/O device. Clock 0 is at the beginning of each microinstruction cycle when microinstructions are loaded from ROS16 into program register 30.

Buffering the microinstruction to program register 30 in this way allows the microinstruction to be executed while the ROS address is being changed at clock 3, as described above, in order to access the next microinstruction. . The summation register 24 is loaded with the instruction address at clock 2 and is loaded with the instruction address at clock 6 as the AJ. The data processed in U22 is loaded.

When a microinstruction directs this data to be written to LSRl4, this writing occurs at clock 1 after the data has been calculated. In this case, data is written directly from output buffer register 26 via driver 18 to a particular register location in LSR14 selected by six K° lines. In a similar manner, data can also be transferred towards an I/0 device. In this case, data is loaded into output buffer register 26 at clock 0 and a signal is provided on line 19 at clock 1 indicating that the data on output bus 20 is valid. This data is changed at the beginning of clock 3, when the address of ROS16 appears in the output buffer register 26. Data entering microprocessor 9 through input bus 10 for storage or modification is sent to AL. It must be supplied to U22 and must be valid at this time. The ALU 22 performs processing specified by the instruction being executed during these clocks. For the same reason? Data from Rl4 is placed on input bus 10 at clock 2 for processing by microprocessor 9. This data is made available for processing in ALU 22 at clock 3 (which allows for signal delays). As mentioned above, the data from LSRl4 is placed on the input bus 10 at clock 2, but from clock 7 to clock 2, it is placed on the AL. U2
2 is used to update the instruction address register 32, so this data is not gated into the ALU 22 until clock 3.

ALU 22 transitions to address increment processing at the beginning of clock 7, thus completing its basic microinstruction processing. Referring to FIGS. 2A and 2B, the main storage device 12
For microinstructions (FS) that use
The second cycle (clocks 8 to 15) is in that the next microinstruction is fetched from RαI6 during clock 8, even though execution of the current instruction continues from clock 15 to the next clock 0. It's slightly different.

The data retrieved from main memory 12 is finally set in a designated register of microprocessor 9 at clock 8 or sent to one of the I/O devices. In the above case, the new microinstruction following each instruction that accesses main memory 12 is gated into the program register 30 at the following clock 0, since it has already been trapped at clock 8 of the preceding instruction cycle. Never. Also, since updating the instruction address register 32 is just a direct transfer with no changes made through the ALU 22 (already changed between clocks 7 and 10 of the previous main memory instruction), The window for this update is shortened and only starts at clock 1, two clocks after clock 15, and continues until the next clock. The main memory write instruction writes data to main memory 12 during clocks 13-15 of the second cycle of the instruction.

Referring to FIGS. 3A to 3C, in the case of w-adic operations, AL. During the first four clocks, U22 has an equivalent value of 2
Perform a base operation to store an intermediate carry for each back w base digit.

Subsequently, the processing of AL.U22 is repeated for another four clocks under the control of the auxiliary clock device 64 in order to perform the "6" correction to obtain the actual pheasant result.
Referring to Figures A through 4C, a branch operation (such that the branch address is loaded at clock 7)
For example, conditional branches, multiple tables when decoding 0P codes from the target language being emulated.
When a branch or a return to branch linkage by returning the address of the source from the instruction address 14 to the instruction address register 32) is performed, the look-ahead address calculated in advance during the execution of the preceding instruction is , another four clock clocks by the auxiliary clock device 64 are used to access the ROS16.
cycle is added.

For shift operations, auxiliary clock device 64 requires two clocks for each bit shifted in accumulation register 34 or extension register 36, and one clock if both registers are used as one double-precision register.
Each bit shift requires four clock periods (half the basic microinstruction execution time). Accumulation register 34 and extension register 36 are logically connected as one double precision register by selectively cycling through ALU 22. In a jump operation, during the basic processing time of ALU 22 (clocks 3 through 6), the equal or greater test is a mask test.

The result of the test is unknown until the beginning of clock 7,
Then, at clock 7, a decision to skip is made. If a jump is not performed, processing of the next instruction that has already been accessed continues without delay. If the jump condition is satisfied and an instruction is skipped, the base clock unit 66 generates another dummy microinstruction cycle during which the address increment for fetching the next microinstruction is , without executing the skipped microinstruction. Unconditional branch instructions can be executed very quickly because there is no need to test conditions and therefore no delay due to auxiliary clocks. Additionally, the 12-bit BROUCH address is input to Al. Pass through U22 and total register 2
4 directly. This address is transferred from summation register 24 to instruction address register 32 and output buffer register 26 at clock 3, thus being synchronous with the normal look-ahead access. Instruction Set Basic machine instructions are optimally designed for emulation and stored in ROS16.

In the following discussion, the term ``instruction'' may be used instead of ``microinstruction'' unless a distinction must be made between emulated target machine instructions and microprocessor instructions. What all instructions have in common is a parity code in the most significant bit position (bit O).
bit and a 3-bit OP code (bits 1 to 3).

The remaining bits are divided into several fields, the length and content of each field depending on the type of instruction. Since there are only eight OP codes, some of the instruction types are distinguished by decoding additional qualification bits.

Most instructions are highly encoded and specify or imply various operations. Many of these operations are performed sequentially. Execution of such sequential operations is shown in FIGS. 2A to 4.
It is controlled by a precisely set timing pattern as shown in Figure C. Next, Figures 2A to 4
The 11 types of basic commands will be explained with reference to Figure C.

j Each instruction has 1 bit parity and 3 bits 0P
It can be defined by 16 bits containing the code.

Also the pair of OP code and instruction type specified by bits 1 to 3? Outside? i■゛ = 5 seconds. Control command (CO)
The timing for the control commands is shown in Figure 3C.

Control instructions include, for example, data transfers, indirect execution, setting interrupt masks, setting paging, table branch operations, arbitrary mode selection, operations based on save condition codes and current condition codes, program indicators, and I/0 transfers. Issued for such operations. First, various uses of control instructions will be described. Many of the control instructions are related to interrupt processing.

One such instruction can cause an interrupt after the completion of each microinstruction, while another instruction provides an interrupt window. In this interrupt window,
Processing of any pending interrupts is allowed and interrupt switching occurs. After this, interrupts are disabled until the interrupt window is encountered again. Other control instructions are
Related to ROSI/0 paging.

The 4-bit page of ROS16 is an internal page specified by page register 32a, which forms part of instruction address register 32. Page register 3
2a is an instruction location where direct register specification of ROSl6 is possible. is used whenever a direct branch across the boundary of is required. ALU 22 increments addresses across the 4K boundary and across the 64K half-words of ROS16. Further, the interrupt switching pointer performs addressing using all 16 bits instead of 12 bits. Therefore, it is also possible to address all of the commands in K. There are also control instructions that control the four indicator bits.

These indicator bits are the lower four bits of the current condition code register 48, which, along with the remaining bits of register 48 that define the four condition codes, are used in count register 50.
constitutes the non-connected upper byte of The indicator bits can each be set by the programmer to provide a different indicator and can be used as switches in subroutines. These indicator bits are stored in the LSR14 together with the condition code and the contents of the count register 50 (corresponding to the lower byte) at the time of interrupt switching.
You can restore it from there. The remaining control instructions relate to condition codes.

In this example, two levels of condition codes are used, each condition code including binary carry, two's complement overflow,
It has the high-order minus bit of the two's complement number and four bits representing cumulative non-zero. Current Condition Code The upper four bits of register 48 are changed for each arithmetic operation, logical shift left, count left shift, multiplication, and division. For other logic instructions, the registers themselves are tested for zero, non-zero, all 6R9, or a mix of 66r9 and 46099. The stored condition code register 42 is the current condition code register 48, except when the equivalent code of the emulated macro language condition code is being transferred or accumulated under microprogram control. The same 4 bits are stored. In the embodiment of the present invention, the following control operations are performed, for example.

(a) Loading immediate data (KBUS) The data field of the instruction is loaded into the upper bit position of the output buffer register 26.

Output buffer ●Lower bit position of register 26 is L
Data bits 0-4 of register 0 of SRl4 are loaded and the contents of output buffer register 26 are
Written to register 0 to LSRl4. (b)LS)
Transfer R data to I/0 device (KLSR) This command is
It has a 4-bit field for addressing registers 0-15 of LSRl4, and data from the addressed local storage register is sent to the output buffer.
It is transferred to register 26 and then to output bus 20.

This KL. The 6-bit field of the SR instruction is I/0
Provides a device address that is loaded into the Ec register 40 to address devices 1-63. (c) Transfer immediate data to I/0 device (KL, CO) Output buffer ● Immediate data from the instruction code is loaded into a part of the register 26, and the remaining part is loaded with the selection of register 0 of LS) Rl4. bits are loaded. Data in other bit positions of the instruction code is L for device address.
Loaded into CO register 40. The contents of output buffer register 26 are loaded into register 0 of LSR14. (d) Interrupt mask setting (KILM) An interrupt mask bit is supplied to the interrupt mask register 44 so that ゜゜1゛ is set in the bit position corresponding to the level of the interrupt to be disabled.

This instruction code has one bit that specifies saving or setting the interrupt mask bit. (E) ROS16 paging settings (KIAP and 5KRAP) KLAP has a field for specifying pages 0 to 15,
On the other hand, KRAP specifies page 16.

Each page consists of 4096 (4K) half words. The control operation for the table branch is R
Specifies the register or portion thereof to be added (exclusive-OR) to the contents of the instruction address register 32 to obtain the next sequential address in OS16. This includes:
There are the following: 1ーーー ´～ノにr
This control operation transfers the contents of the instruction address register 32 to the register location corresponding to the current interrupt in I-SRl4, and reset and
The new interrupt is sampled and the contents of the register location corresponding to the sampled new interrupt in LSR14 is transferred to the instruction address register 32.

(h) KSIE The KSIE control command is used to control interrupt codes (release or sample a certain interrupt and disable future interrupts), error code,
mode, and three 2-bit fields (11.,EE
and SS).

KSIE control instruction interrupt code (11) ● field, error ● mode (EE) ● field and main storage byte ● address (SS) ● code 01 in one or more of the fields is KSIE control instruction as shown in the table below. Specifies an alternative control operation to one based on the instruction's interrupt code, error mode, or main storage byte address mode. If the control code is 11. ．． When indicating EE or SS, the KSIE control instructions define operations specified by interrupt code, error mode, or main storage byte address mode, respectively. (ri) Control operations using KNTCKNTC are performed using K in the above table.
It performs the function of TP■, and if the next instruction is an arithmetic instruction, then executes KCSE.

Indicator 4 in the condition code is reset to 6° even number 2 or set to “odd number” based on the result.
The KPCCKPCC control instruction transfers the contents of save condition code register 42 directly to current condition code register 48.

(Le) KFCC The KFCC control instructions specify whether the current condition code ● register 48 is to be saved or set, and the location where it is to be saved or set, i.e. carry, borrow, overflow, minus, Specifies cumulative non-zero or indicators 1-4.

Main Memory Instructions Main memory instructions include logical write (LW) and storage fetch (FS) instructions.

In these instructions, shown in FIGS. 2A and 2B, data is read from main memory 12 and stored in four basic internal data registers, i.e., storage. is loaded into count register 36, expansion register 36, count register 50, and output buffer register 26. Data retrieved from main memory 12 is addressed by extension register 36 or one of the local storage registers, depending on the designation in the instruction address.

The address is first updated by incrementing or decrementing to provide a continuously changing pointer to main memory 12 to output bus 20, or the displacement of count register 50 ( (positive or negative) into a valid address. For storage instructions, half-word, addressing mode, or byte addressing mode can be specified.

IBMll3O addresses data in main memory in half-word mode. The IBM 36O and 370 and IBM System/3 use a byte addressing mode, but can also retrieve two bytes in a single access. In the System/3 instruction set architecture, 3-byte, 4-byte, 5-byte, or 6-byte
Because byte instructions are possible, the instructions themselves are not aligned on half-word boundaries. Therefore, in order to simplify emulation, the microcomputer according to the invention:
At AL, U22, the data from the main storage device 12 is
Half-word alignment is performed by rearranging the bytes of this data so that particular bytes are in particular positions, for example, so that the 0P code of an instruction always appears in the lower byte. Logical Write Command (LW) As already explained, in the present invention, the output bus 20
is used as an address bus for the main memory 12 and is not used for data transfer to the main memory 12, so there is no direct data transfer path from the microprocessor 9 to the main memory 12.

Input bus 10 is bidirectional only in relation to main memory 12 . The reason input bus 10 is not bidirectional in relation to microprocessor 9 is to save area on microprocessor chip 9. The output drivers required to provide data to the input bus 10 require a large amount of area and power on the chip 9, and therefore their inclusion on the chip 9 is undesirable. The four logical write instructions described below select half-word mode, low-byte mode, or high-byte mode and write data retrieved from the addressed register location or I/O device of LSRl4. The data is stored in the main storage device 12.

Logical Write from LSR In the first logical write instruction, the data read from register location 1 of LSRl4 is written to LSRl4.
4 locations 0 through 63.

One register location 1-63 of LSRl4
is selected and its contents are incremented or decremented by one, or left unchanged, before setting the output buffer register 26 to address main memory 12. The updated address is written back to the above-mentioned selected register location in LSR14. L.S.
If register location 0 of Rl4 is specified as the address source, should the contents of count register 50 be the source for the main memory address? Rl4 register
Used as an indirect address for a location. A memory write cycle is performed using data read from register location 1 of LSR14, which is connected to input bus 10. It is also possible to use two bits of the 0P code as an address change code so that when this is set to 10, only the lower byte or upper byte is written to main memory 12.

If a control instruction sets byte addressing mode, all address updates are performed with +2 or -2, and high byte selection forces -1 address updates (low byte is address ). If the updated address is an even number, the upper byte is stored; if the updated address is an odd number, the lower byte is stored. Also, the initial contents of output buffer register 26 are LSRl4
The register is selected from register number 0. By address from extension register 36? Logical Write from Locations 0 to 63 of Rl4 The second logical write command indicates that the data to be written to main memory 12 is obtained from locations 0 to 63 of LSRl4, and
is the same as the first logical write instruction except that the address of is obtained from extension register 36.

Selective writing of the upper byte or lower byte as described above is also possible. Logical write from 1/0 device 0-63 using address from same LSR location The third logical write instruction is also almost the same as the first instruction, but
The selection of address registers and the selection of I/O devices 0 to 63 that supply data to be written to main memory 12 are
? The difference is that they are performed by the same register locations 0-63 of Rl4.

I/0 device 1 using address from extension register 36
Write from 63 to 63 The fourth logical write command is 2 except that the data to be written to main memory 12 is supplied to input bus 10 from selected I/O devices 1 to 63.
It is the same as the th logical write instruction.

Storage Fetch Instruction (FS) The storage fetch instruction is set to perform a fetch operation in half-word mode.

Regarding setting byte addressing instead of half word addressing, please refer to the description of control instructions. (Current condition code register 48 and count register 50, or interrupt mask register and error register 46, are always used together in byte mode, and the high byte is not brought to O in a storage fetch. .) Loading from main memory 12 to register of CPU 9 using LSR address (half word ●
Address mode) One of register locations 1 through 63 (excluding location 0) of LSRl4 is selected and its contents are set to output buffer register 26 to address main memory 12. Previously changed by 0, ±1 or or1.

If the change is ±1, the contents of output buffer register 26 are updated and written to the selected register location of LSR14. Following this, a memory read cycle is performed and the data read from main memory 12 to input bus 10 is transferred to accumulation register 3.
4, selectively loaded into expansion register 36, output buffer register 26 or count register 50/error register 46; Instead of current condition code register 48 and count register 50, interrupt mask register 44 and error register 46 may be selected by the KSIE control instruction. (Count register 50/error register 46 has only the lower byte.) LSRl4
Register location 0 of selects indirect addressing of μSRl4 from the lower six bits of count register 50. The first data in the output buffer register 26 is also selected from register location 0 of LSR14. Using Bus Operand Address (Half-Word Address Mode) This instruction uses output buffer register 26 (register location 0 of LSR14) in place of extension register 36, and bus 2
The auxiliary address transfer via 1 is transferred to output buffer register 26 or l:) register location 1 of LSRl4.
is the same as the next instruction, except that it acts as a half-word move to one of LSRl4 through 63 or a load of the updated address into register location 0 of LSRl4.

Using operand address from extension register 36 (half word address mode) extension register 36
The contents of 0, ±1 before output buffer register 26 is set to address main memory 12.
or by addition of the operand displacements in count register 50.

The updated contents of output buffer register 26 are written back to expansion register 36. Next, the main storage device 12
A read cycle is started. If the selection of LSR14 is from register locations 1 through 63 (not including location 0), then the auxiliary transfer will occur before the data from main memory 12 is available. The contents of instruction address register 32 may be written to selected register locations in LSR14. Finally, data from main memory 12 is selectively transferred to accumulation register 34, extension register 36, output buffer register 26, or count register 50/error register 46, as in the first FS instruction. It is sent towards the input bus 10 for loading. Also,
The first data in output buffer register 26 is LSR
Selected from register location 0 of l4. Load from Main Memory 12 to I/0 Device (Half Word Address Mode) This instruction loads the contents of address register 32 from expansion register 36 or the register of 6LSR 14 corresponding to the selected I/0 device. Same as the instructions above except that it can be selected from a location and updated.

After the data read from main memory 12 is loaded into the output buffer register 26 (not in register location 0 of ?Rl4), the data read from main memory 12 is transferred to the selected I /0 is sent to the device. No auxiliary transfer takes place. Device 0 selects device indirect addressing from the lower six bits of count register 50. Also, the initial contents of output buffer register 26 are stored in register location 0 of LSRl4.
selected from. Arithmetic and Logical Instructions Figures 3A to 3C
The arithmetic and logical instructions shown in the figure are Data Modification (MD)
and change operand (MO).

Arithmetic instructions include addition and subtraction with or without carry. These can be implemented in two's complement form or in backw-adic form (each 4-bit field contains one modulo digit without sign). Arithmetic operations are performed in microprocessor internal registers (
3 accumulation registers, 36 expansion registers, 50 counting registers
and output buffer register 26). In addition, the accumulation register 34 or the extension register 3
6 can be arithmetically combined with one of the 64 register locations of LSRl4, in which case
What is the calculation result? Stored in one register location of Rl4 or extension register 36. All arithmetic instructions executed between internal registers of the microprocessor 9 may be executed in half-word mode, upper mode only mode, lower byte mode or lower four digits pass-bit mode. The remaining bits in each of these modes are unchanged. Logical instructions include AND, OR, and EXCLUSIVE OR.

If these logical instructions are executed only between internal registers, the lower 4
It can be implemented in digit-by-bit mode, low byte mode, high byte mode, or half word mode. L.S.
When using Rl4, all logic instructions can only be executed in half-word mode. Data change (MD) The contents of the accumulation register 34 or extension register 36 are changed to L! by this data change instruction. The content of 5R14 (which does not change) may be modified.

Additionally, the contents of a designated register location in LSR14 can be modified using the contents of extension register 36. In this case, the contents of extension register 36 are unchanged and the result is loaded into the selected register location of LSR14. Additionally, any 1/0 device may be selected to provide data to input bus 10. This data can be modified with the data in expansion register 36, and the result of the modification can be made by setting the data in output buffer register 26 (not LSRO) and subsequently forwarding it towards output bus 20. LSRl4
), the same I/
0 device. If the address portion of the data modification instruction is set to O, data of O will appear on the input bus 10. A move is made from the expansion register 36 to the output buffer register 26 by using an OR operation.The output buffer register 26 is set to all O's by using an AND operation. Modifying operations that may thus be specified are binary addition with or without carry or back w-adic addition with carry, binary or back w-adic subtraction with borrow (?Rl
No subtraction is done from the 4 or I/0 device. The opposite is good), and, or, and exclusive or. LSR
If l4 is specified, its register location 0 starts from the lower 6 bits of count register 50. Rl
4 or indirect addressing of I/0 devices. Modify Operand (MO) In a modify operand instruction, either the accumulation register 34 or the extension register 36 is modified.

The contents of the extension register 36 are the output buffer ●Register 2
6. If extension register 36 is 0, register location 0 of LSRl4 (
Output buffer ●Extend the contents of register 26) to expansion register 3
6 and LSRl4 register locations 1-15
You can move it to one of the following. The operand change instruction is appended with a move operation between any combination of accumulation register 34, extension register 36, or count register 50/error register 46, and
This is the same as the data modification instruction described above, except that subtraction from register 46 is not allowed (the reverse is allowed).

Also, all of the operations described above can be performed on a half word, only the high byte, only the low byte, or only the low digits, except that the high byte of the count register 50/error register 46 is not present. After each of the above operations is completed? Half-word result (count register 50/error register 46 high byte current condition code register 48/interrupt mask register 44) to selected register location (one of 1 to 15) in Rl4
) may be moved. Logical Shifts The shift operations shown in Figures 4A and 4B are performed one at a time.
This is done bit by bit either to the left or to the right.

The number of shifts depends on the register length. The accumulation register 34 and the expansion register 36 are each capable of shifting 1 to 16 bit positions. If double precision is required for multiplication and division, the accumulation register 34 becomes the upper register of the extension register 36, and both registers are combined to form one 32-bit register. This 32
The register of bits shifts 1 to 32 bit positions in any of the following modes: arithmetic shift right, shift left count, logical shift left, logical shift right, shift left rotate, and shift rotate right. A faster operation equivalent to rotating an 8-bit position in a 16-bit register can be performed in one microinstruction cycle.

This operation is a 1-byte swap (Bytetwist) J
It is called. Immediate Modification (IM) The timing of the immediate modification command is shown in Figure 3C.

Program●1 byte of data from register 30 (0
P bits 8-15) are associated with the lower byte of the accumulation register 3 expansion register 36 or count/error register 50, 46 selected by the previous KISE control instruction. When the accumulation register 34 or the expansion register 36 is selected, the combination operations are subtraction, load, or,
and, exclusive or, and addition. The carry (borrow) generated as a result of addition (subtraction) is propagated toward the upper byte. The combinatorial operations for count/error registers 50, 46 are or, and, load, and addition. In addition or subtraction operations, any carry input is ignored and a new condition code is set.
Conditional Jump (JC) The jump instruction whose timing is shown in Figure 4B is executed if the result of the test is negative.

The following tests are performed using the mask byte in the instruction and the lower 8 bits (lower byte) of the selected register. (1) The mask and lower byte are equal. (2) The mask is larger than the lower byte. (3
) The mask bits are tested for on bits in the lower byte and the remaining unselected bits are ignored. (4
) The mask is tested for off bits in the low byte and the remaining bits are ignored. The current condition code register 48, which has four condition codes and four program control indicator bits, is tested using a mask to select on/off bits and jump through any combination of conditions.

If the result of the test is negative, the next instruction is skipped. In addition, the accumulation register 34 or the extension register 3
The upper digits of 6 can also be tested for all 6603 conditions. Branch operations Branch operations include conditional branches and unconditional branches, which are arbitrary branches in ROS16. Can be performed within a range.

Before taking an unconditional branch, a branch association operation is performed by storing the contents of the current instruction address register 32 plus one in one register location of LSR14. Return to the subroutine in which the branch association operation was performed is accomplished by taking the above-mentioned address stored in LSR14 from LSR14 and returning it to instruction address register 32. A second group of branch instructions performs multi-table branch operations.

This multi-table ●branch operation consists of the lower four bits of the microprocessor register, the next four bits (
These can be done on the zone * bits (the lower 4 or 6 bits are ignored) or on all 8 bits, thus resulting in a 256-way table branch. Based on this, the 8-bit OP code can be decoded by an unconditional branch instruction from the table. The third group of branch instructions is 1
Perform a signed displacement branch operation based on a number of week condition (eg, whether a register is zero or not, whether a register is negative or not). A displacement branch operation is performed by taking an 8-bit displacement from the instruction and adding it to the contents of the current instruction address register 32 as a signed 16-bit number. Other instructions perform displacement branch operations based on the contents of count register 50, which is decremented by 1 or 16, and whether the result is all zeros or not, with the lower four bits being all zeros.
Branching is performed depending on whether the lower four bits are all 1, whether the upper four bits are all 1, and so on.

Logical Move-Count (LM) The logical move-count instruction, the timing of which is shown in FIG.
63 are selectively moved to instruction address register 32, accumulation register 34, extension register 36, or the combined current condition code register 48 and count register 50.

The contents being moved may be changed by +1 or -1 (other than moving a single byte to accumulation register 34 or extension register 36), and the changed value is transferred to the selected register of LSRl4. It is written back to locations L through 63. On the contrary, the specified registers (instruction address register 32, accumulation register 34, extension register 36)
, or the contents of the combined current condition code register 48 and count register 50), either unchanged or with a +1 or -1 change (other than a single byte movement from the accumulation register 34 or the extension register 36) LSRl4 may be moved to selected register locations 1-63. For byte movement, the accumulation register 34
Alternatively, either the upper byte or the lower byte of the extension register 36 can be specified, but as described above, the byte being moved is not changed. The contents of instruction address register 32 constitute a 16-bit address for ROS16. Current condition code register 48 may only be selected as the upper byte in combination with count register 50 unless increment or decrement is specified. Interrupt mask register 44 and error register 46 may also be used in place of current condition code register 48 and count register 50 if set by the KSIE control instruction described above. If a logical move-count instruction specifies register location 0 of LSRl4, then current condition code register 48 and count register 50 are selected as destination or source registers (these and register locations of LSRl4 0), from the lower 6 bits of the counting register 50? Indirect addressing of Rl4 is selected. 1/0 Operation No special I/0 instructions are used in this embodiment.

(2) Direct program-controlled transfer of data or control messages to and from the /O device is accomplished by storage fetch instructions, storage logic write instructions, data modification instructions, and control instructions. The storage fetch instruction transfers data from main memory 12 to the I/O device via the internal data bus formed by buses 23, 25 and 28. A logical write instruction is executed by writing the extension register 36 or the data register 14.
from the I/O device via the input bus 10 to the main memory 1 using the address from one register location in the
2 (does not pass through the microprocessor 9). The data change command takes data from the I/O device, performs an AL.U operation on this data using the extension register 36, and sends the result from the output bit register 26 to the output bus 20. 0 device. Certain control instructions may return specified register locations 0-15 of LSR14 or the immediate data in the instruction.
It can be used to output data from the field towards an I/O device. Data transfers from any I/O device to accumulation register 34, expansion register 36, or register locations 0 through 15 of LSR14 can be accomplished by separate control instructions. In either case, the device address specified directly by the instruction or indirectly using the contents of count register 50 is also used to address LCO output line 41 and auxiliary address bus 21 (LSR14). () to the I/O device.

A 1/0 transfer operation involves a pair of connection procedure signals, namely sample and
Synchronized by in and sample out.

These connect procedure signals can be used in conjunction with hold clock in to perform asynchronous 1/0 transfer operations independent of line length and 1/0 device operation delays.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the connection between FIGS. 1A to 1C, FIGS. 1A to 1C are block diagrams showing one embodiment of the microcomputer according to the present invention, and FIG.
Block diagram showing the connection between Figure A and Figure 2B, Figure 2A
2B and 2B are timing diagrams showing the timing of execution of the FS instruction and LW instruction, and FIG.
3A to 3C are timing diagrams showing the timing of execution of MD instructions, MO instructions, LM instructions, IM instructions, and control instructions; FIG. Block diagram showing the connections between
What about Figures A to 4C? Instruction, JC instruction, 0 instruction and BU
FIG. 5 is a timing diagram showing the timing of instruction execution. FIG. 5 is a block diagram showing details of the interrupt/cycle steal processing mechanism. 10... Input bus line, 12... Main storage device, 14...
・LSR, 16... ROSll8... Drive device, 2
0... Output bus, 21... Auxiliary (mini) address bus, 22... ALU124... Total register, 23
, 25, 28... Internal bus line, 26... Output buffer register, 30... Program register, 32...
...Instruction address register, 34...Accumulation register, 36...Extension register, 38...Decrement register,
40... E℃ register, 42... Storage condition code.
Register, 44... Interrupt mask register, 46...
...Error register, 48...Current condition code register, 50...Counting register, 52...Interrupt gate, 53...Common ball bus, 54...Priority encoder, 56...・Current interrupt code●Register, 58...
- Comparison device, 60... Four-phase generator, 62... Instruction decoding device, 64... Auxiliary clock device, 66... Basic clock device.

Claims (1)

[Claims] 1. A unidirectional input bus that transfers instructions or data, a unidirectional output bus that transfers a first address, a second address, or data, an auxiliary address bus that transfers a third address, and the input bus and a first storage device connected to the output bus and configured to read data to or write data from the input bus in response to the first address; and a first storage device connected to the input bus and the output bus. a second storage device for reading instructions to the input bus in response to the second address; and a third storage device connected to the input bus, the output bus, and the auxiliary address bus;
a third storage device for reading data received from the output bus to the input bus in response to an address; and a CPU comprising means for connecting the input bus to the output bus to form a loop bus. A data processing system having .