JPS6053930B2 - variable frequency divider circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency divider circuit with a variable frequency division ratio, and more particularly to a variable frequency divider circuit that can obtain a frequency division ratio including values below the decimal point.

A frequency dividing circuit is a circuit that obtains one output pulse for m input pulses, and m (in this invention, m is referred to as a frequency division ratio) is usually an integer, but this frequency division ratio is As a frequency dividing circuit that includes values below the decimal point, the one shown in FIG. 1 is conventionally known. This connects first and second frequency dividers 1 and 2 in series with frequency division ratios m and n, and sets a flip-flop 4 in a pulse extraction circuit 3 with the output pulse CP3 of the second frequency divider 2. At the same time, the input pulse CP resets the flip-flop 4, and the inverted output Q of this flip-flop 4 controls the N-loss gate 5.
The input pulse CP is thinned out by one to obtain CP, and the output CP2 is taken out from the output terminal of the first frequency divider 1. However, since inverters 6 and 7 are included at each input end of the flip-flop 4, setting and resetting of the flip-flop 4 are executed at the falling edge of the output pulse CP3 and the input pulse CP of the second frequency divider 2, respectively. . The operation of this frequency dividing circuit is shown in the time chart of FIG. This is an example where m=3 and m=2, and in this case, 6 pulses CPl are applied to the first frequency divider 1 during the period of 7 input pulses CP. Since two output pulses CP2 are obtained at the output terminal, the frequency division ratio is 712 = 3.5
becomes. That is, in this frequency divider circuit, when (Mxn) pulses are applied to the first frequency divider 1, one pulse appears at the output terminal of the second frequency divider 2, which causes the first frequency divider to Since the input pulse that is supposed to be input to frequency generator 1 is thinned out by one, its operation cycle is expressed as the number of input pulses CP (Mn+1).
It becomes an individual portion. Since n pulses CP2 appear at the output terminal of the first frequency divider 1 in each cycle, the overall frequency division ratio is expressed by the general formula. Here, M and n are positive integers, so
In the end, this frequency dividing circuit provides a frequency division ratio that includes values below the decimal point. Further, this frequency division ratio can be varied by using variable frequency dividers as the first and second frequency dividers 1 and 2 and changing the values of M and n. However, in this conventional variable frequency divider circuit, it is difficult to set the value below the decimal point of the frequency division ratio to the desired value, and the intervals are not equal, so it is difficult to actually use it for applications such as frequency synthesizers. There was a drawback that it was inconvenient.

In other words, the value 1/n below the decimal point of the frequency division ratio shown in equation (1) above is as shown in FIG. Change as shown. As is clear from this figure, the function 1 with n as a variable
/n is a monotonically decreasing function, and since n is a positive integer, the value below the decimal point of the frequency division ratio is, for example, 4. It cannot take such a value. Also, when changing n, the decimal value 1/n of the frequency division ratio changes greatly in the area where n is small, and as n increases, the change becomes smaller, so it cannot be changed at equal intervals. . Furthermore, in the conventional variable frequency divider circuit, the leading edge (the falling edge in FIG. 2) of the sampling pulse (inverted output Q of the flip-flop 4) in the pulse sampling circuit 3 is connected to the second frequency divider 2. Since it coincides with the trailing edge of output pulse CP3, that is, the trailing edge (rising edge in Figure 2), the output pulse of frequency divider 2 differs from input pulse CP due to the operation delay of frequency dividers 1 and 2. If CP3 is delayed by more than half a cycle of the input pulse CP, the leading edge of the sampling pulse will be delayed from the rising edge of the input pulse CP, resulting in a thin pulse being output at the part that should be sampled.
There was a problem that reliable pulse sampling was not possible.

This invention was made in view of the above problems, and allows the value below the decimal point of the frequency division ratio to be changed more finely and at equal intervals, and is stable without being affected by circuit operation delays. The purpose of this invention is to provide a variable frequency divider circuit that can operate. ) In this invention, after the main frequency dividing element that divides the input pulse by m (m is any integer), Q (Q is O to P- 1
a rate multiplier configured to generate an output pulse of at least an integer of . , the basic idea is that the output is taken out from the frequency dividing element.

Then, a pulse sampling circuit that extracts the input pulse to the frequency division element in synchronization with the output pulse of the rate multiplier receives the output pulse of the rate multiplier and divides the input pulse into the frequency division element within this output pulse generation period. a first gate circuit that extracts input pulses to the frequency dividing element; and a first gate circuit that is driven by the input pulse to the frequency dividing element extracted by the first gate circuit, and is driven by a predetermined input pulse to the frequency dividing element. 1
A sampling pulse whose leading edge is synchronized with one edge of the second one and whose trailing edge is synchronized with one edge of the next one is generated within the generation period of the output pulse of the rate multiplier. It is constituted by a pulse generation circuit and a second gate circuit which receives this sampling pulse and extracts one input pulse to the frequency dividing element.

In the variable frequency divider circuit according to the present invention, by changing the value of Q in the rate multiplier, the value below the decimal point of the frequency division ratio can be changed minutely and at equal intervals. In addition, according to the pulse sampling circuit configured as described above, since a sampling pulse whose leading edge and trailing edge are synchronized with one edge of the input pulse to the frequency dividing element is used, the frequency dividing element and the rate multiplier are Regardless of the operational delay, the input pulse of the frequency dividing element can be reliably extracted in synchronization with the output pulse of the rate multiplier.

The present invention will be explained in detail below with reference to Examples.

FIG. 4 shows a variable frequency divider circuit according to an embodiment of the present invention, including a variable frequency divider 11 that divides an input pulse by m, and a variable frequency divider 11 that generates Q output pulses for P input pulses. The output pulse of the rate multiplier 12 is applied to the pulse sampling circuit 13, and this circuit 13 synchronizes with the rising or falling timing of the output pulse of the rate multiplier 12. The input pulse to the variable frequency divider 11 is extracted by using the variable frequency divider 11, and the output is taken out from the output terminal of the variable frequency divider 11. Here rate ● multiplier 12
I will explain about it.

Figure 5 shows the rate multiplier P=8, Q=0~7
FIG. 6 is a diagram showing an example of the configuration in the case of , and is a time chart thereof. In FIG. 5, flip-flops 21a, 2
1b, 21c are cascade-connected via the N1 gate 22 to form a synchronous counter, and each of these flip-flops 21a, 21b, 21c is activated at the rising edge of the input pulse CP2 (output pulse of the variable frequency divider 11). When the device is in operation, its respective outputs Qa, Qb, and Qc are as shown in FIG. AND gates 23a, 23b, 23c are CP
2 and Qa, Qb, Qc and their inverted outputs'
Among the combinations of Qa, 'Qb, Oc, (CP2△Qa)
, (CP2△Qa△ηb), (CP2△Qa△Qb△mutualc), and as shown in FIG. output pulses at different times. The respective outputs of these AND gates 23a, 23b, 23c are selectively taken out by AND gates 24a, 24b, 24c according to control signals C2, Cl, CO,
Further, they are synthesized by an 0R gate 25 and taken out as an output pulse CP3. With this configuration, the control signal C2
, Cl, CO, eight input pulses C
From 0 to 7 output pulses CP3 can be generated for P2.

For example, C2 = logic ゜゜1゛, C1 = logic ゜゜1゛, CO
= logic "0", the output of the 0R gate 25 is (
CP2△ηa)△(CP2△Qa△0b), and the sixth
As shown in the figure, six output pulses CP3 are generated for eight input pulses CP2. On the other hand, the pulse sampling circuit 13 inputs the input pulse C to the variable frequency divider 11 in synchronization with the output pulse CP3 of the rate multiplier 12.
The pulse sampling circuit 13 shown in FIG. 4 has a configuration in which the variable frequency divider 11
This is an example of a circuit that can reliably extract only one input pulse CP and make it CPl even against the delay effect of the rate multiplier 12.

In the pulse extraction circuit 13, 31 and 32 are flip-flops that are reset when the reset terminals Rl and R2 are at logic 6 "03" in response to the rising edge of the input pulse;
33, 34 are AND gates, 35, 36, 37 are NAN
It is a D gate, and NAND gates 36 and 37 constitute a zero reset R-S flip-flop 38. Here, the AND gate 33 is the rate ● multiplier 12
A first gate circuit is configured to extract the input pulse CP within the period of the output pulse CP3.

In addition, flip-flops 31, 32, NAND gate 3
5 and the R-S flip-flop 38 constitute a sampling pulse generation circuit 39 that is driven by the input pulse CP pulse extracted by the AND gate 33 and generates a sampling pulse. Furthermore, the AND gate 34 constitutes a second gate circuit for extracting one input pulse CP by the sampling pulse from the sampling pulse generating circuit 39. Next, the operation of the variable frequency divider circuit shown in FIG. 4 will be explained with reference to the diagram in FIG.

However, FIG. 7 shows an example where m=8, P=2, and Q=1. Now, if the output CP3 of the rate multiplier 12 is logic ゛“0゛, then the R-S flip-flop 3
The output 03 of 8 is logic ``1'', so that the flip-flops 31 and 32 are in the reset state, and the input pulse CP is blocked by the AND gate 33 to maintain the initial state. Since the output 'Q2 of the flip-flop 32 is logic "1", the input pulse CP passes through the AND gate 34 and is added as the input pulse CP1 to the variable frequency divider 11. When the count progresses and the output CP3 of the rate multiplier 12 becomes logic ``1'', the input pulse CP passes through the M-width gate 33 and is input to the flip-flop 31.
When the outputs Ql and Q2 of 1 and 32 become logic 6 "1" at the same time, the output of the N,AND gate 35, that is, the set input S3 of the R-S flip-flop 38 becomes logic "40", so that this R- The S flip-flop 38 is set.As a result, the output 'Q3 of the R-S flip-flop 38 becomes logic "03", so the flip-flops 31 and 32 are reset. Furthermore, the R-S flip-flop 38 outputs the output CP of the rate multiplier 12.
3 returns to the logic "0", the reset input R3 becomes the logic "0" and is reset and returns to the initial state. At this time, the input pulse CP1 of the variable frequency divider 11
is given by the AND gate 34 as the product output of the input pulse CP and the output 'Q2 of the flip-flop 32. Therefore, only when the output 02 of the flip-flop 32 is logic "0", one pulse is output from the input pulse CP. The sampled pulse is added to the variable frequency divider 11 as an input pulse CPl.In this way, the variable frequency divider circuit of FIG.
The operation of extracting one input pulse to be input to the variable frequency divider 11 at the time when the output Q2 of the flip-flop 32 becomes the logical value "0" is repeated. Therefore, in the operation example shown in FIG. 7, two output pulses CP2 are obtained for 17 input pulses CP, resulting in a frequency dividing circuit with a frequency division ratio of 8.5. Furthermore, according to the pulse sampling circuit 13 configured above, when the output pulse CP3 of the rate multiplier 12 arrives,
The input pulse CP within the period of this output pulse CP3 is extracted by the 5AND gate 33 which is the first gate circuit, and the flip-flops 31 and 32 in the sampling pulse generation circuit 39 are
are sequentially driven, so that the leading edge, that is, the leading 3 edge (rising edge in FIG. 7) becomes the input pulse CP.
is synchronized with one edge (rising edge in Fig. 7) of a predetermined one (the first pulse of CP in Fig. 7), and the trailing edge (falling edge in Fig. 7). is a sampling pulse (output Q2 of flip-flop 32) synchronized with one edge (falling edge in FIG. 7) of the next 4.1 input pulses CP (the 11th pulse of CP in FIG. 7). is generated within the output pulse generation period of the rate multiplier 12, and this sampling pulse is used to extract one pulse from the input pulse CP by the AND gate 34, which is a second gate circuit. Because of this, stable operation is possible.

That is, frequency divider 11 and rate multiplier 1
Due to the operation delay of 2, the rate and
The output pulse CP3 of the multiplier 12 is the input pulse C
Even if there is a delay of more than half a cycle of P, the sampling pulse is generated in synchronization with the input pulse CP regardless of the delay of this output pulse CP3, so the frequency divider 11 is generated during the period of the sampling pulse. There is no possibility that a narrow pulse will be generated in the input pulse CPl of the input pulse CP1, and the pulse sampling will be performed reliably. In the variable frequency divider circuit shown in FIG. 4, the operation period of the rate multiplier 12 is P times the number of input pulses CP2, and during this period, the input pulses that are supposed to be input to the variable frequency divider 11 are Since Q extracted CPs are actually given to the variable frequency divider 11 as input pulses CPl, the overall operating cycle is equal to the input pulses C
The number of P pulses is (Pm+Q), and P output pulses CP2 appear at this period at the output terminal of the variable frequency divider 11, which is the output terminal thereof.

Therefore, the frequency division ratio of this variable frequency divider circuit can be expressed as a general formula.

From this, for example, let P=8 and Q=0.1, 2...
. . . By changing the frequency as shown in 7, the frequency division ratio as shown in Table 1 can be obtained. This shows that it is possible to change the values at equal intervals.

Further, this interval can be made sufficiently small by selecting the values of P and Q. Therefore, the value below the decimal point of the frequency division ratio can be changed minutely, and can be easily set to a desired value. As described above, according to the present invention, it is possible to provide a variable frequency divider circuit that can finely change the value below the decimal point of the frequency division ratio at even intervals.

Other embodiments of the invention are shown in FIGS. 8 and 9.

Figure 8 shows a prescaler (
A prescaler 14 is inserted, and if the frequency division ratio of this prescaler 14 is n, then the overall frequency division ratio is as follows.

In FIG. 9, a prescaler 14a and a pulse sampling circuit 13a are further inserted in the front stage of the variable frequency divider circuit in FIG. A rate multiplier 12a that generates Q and a rate multiplier 12b that generates Q2 output pulses for P2 output pulses are provided. 14a and the pulse sampling circuits 13a and 13b on the input side of the variable frequency divider 11 are respectively controlled.

The frequency division ratio in this case is given by the following equation, where Nl and n2 are the frequency division ratios of the prescalers 14a and 14b.

FIG. 10 shows another configuration diagram of the pulse sampling circuit used in the present invention, in which 40 is an inverter, 41 and 42 are D-type flip-flops corresponding to 31 and 32 in FIG. 4, and 43 to 47 are D-type flip-flops. N corresponding to gates 34 to 37 in FIG.
OR gate, 48 is a flip-flop corresponding to 38 in FIG. 4, 49 is an OR gate, and flip-flop 4
1, 42, and gates 45 to 49 constitute a sampling pulse generation circuit 50.

Moreover, the time chart is shown in FIG. That is, this pulse sampling circuit is a rate multiplier 12.
variable frequency divider 1 at the falling timing of output pulse CP3.
This is an example in which the input pulse CP to 1 is extracted as CP. On the other hand, the rate multiplier is not limited to the circuit shown in Fig.
It is sufficient that Q output pulses are obtained for Q input pulses.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of a conventional variable frequency divider circuit, Fig. 2 is a time chart showing its operation, Fig. 3 is a diagram showing its characteristics, and Fig. 4 is an embodiment of the present invention. 5 is a circuit diagram showing an example of the configuration of a rate multiplier used in the present invention, and FIG. 6 is a time chart showing this operation.
FIG. 7 is a time chart showing the operation of the gate shown in FIG. 4, FIGS. 8 and 9 are block diagrams showing other embodiments of the present invention, and FIG. 10 is another configuration of the pulse sampling circuit used in the present invention. A circuit diagram showing an example, and FIG. 11 are time charts showing the operation. 11...Variable frequency divider, 12, 12a, 12b.
...Rate multiplier, 13, 13a, 13
b...Pulse extraction circuit, 14, 14a, 14
b... prescaler, 33, 43... first gate circuit, 34, 44... second gate circuit,
39,550...Pulse generation circuit for extraction.

Claims (1)

[Claims] 1 A frequency dividing element that divides the input pulse by m (m is any integer), receives the output pulse of this frequency dividing element as an input pulse, and divides the input pulse into Q pulses for P (P is any integer) input pulses. a rate multiplier configured to generate an output pulse (Q is an integer from 0 to P-1), and at least Q being variable; and the frequency dividing element in synchronization with the output pulse of the rate multiplier. a pulse sampling circuit for extracting input pulses from the rate multiplier, and extracting an output from the frequency dividing element, the pulse sampling circuit receiving output pulses from the rate multiplier,
a first gate circuit that extracts an input pulse to the frequency dividing element within this output pulse generation period; and a first gate circuit that is driven by the input pulse to the frequency dividing element extracted by the first gate circuit; The leading edge is synchronized with one edge of a predetermined one of the input pulses to the frequency dividing element, and
a sampling pulse generating circuit that generates one sampling pulse whose trailing edge is synchronized with one edge of the rate multiplier within the generation period of the output pulse of the rate multiplier; A variable frequency divider circuit comprising: a second gate circuit that extracts one input pulse to a frequency element;