JPS6053985B2 - vertical synchronizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical synchronization device for a television receiver, in which an input signal is made to have approximately the same phase as the start of a vertical blanking period of a video signal, and a vertical blanking period is set to be in phase with the vertical blanking period of a video signal. The purpose is to reduce the power consumption of the vertical output circuit by configuring the vertical synchronization circuit so that the period is almost the same as the vertical blanking period.

As shown in the block diagram of FIG. 1, the configuration of a conventional vertical synchronization circuit is such that the signal separated by a synchronization separation circuit 1 is passed through an integration circuit 5 to eliminate the horizontal synchronization component, and then input to a vertical oscillation circuit 6 to generate vertical synchronization. The oscillator circuit 6 is triggered and synchronized, and its oscillation output is input to the vertical output circuit 7, where it is integrated and amplified to cause a sawtooth wave current to flow through the deflection coil 8 to vertically scan the cathode ray tube screen. ing.

In FIG. 1, 2 is a horizontal AFC circuit, 3 is a horizontal oscillation circuit, 4 is a horizontal output circuit, and the horizontal AFC circuit 2 is a horizontal synchronization signal in the synchronization signal separated by the synchronization separation circuit 1 and a horizontal synchronization signal from the horizontal output circuit 4. The horizontal oscillation circuit 3 is synchronized with the horizontal synchronization signal by comparing the output signal with the output signal. Here, the phase relationship of these signals will be explained using FIG. 2. Figure 2 A, B, C, D, E, F, G, and H are also shown in Figure 1. FIG. 2A shows a video signal subjected to video detection, which is determined by the broadcast standard to have an equivalent pulse before (13H), a vertical synchronizing pulse (13H) after, and a vertical blanking period of 2H. Therefore, this video signal is synchronously separated (B in Figure 2), the signal is integrated (C and F in Figure 2), and the vertical oscillator 6 is triggered by adjusting the frequency of the vertical oscillator 6. Synchronization can be achieved even at the position of the volume shown in FIG. 2F. If synchronization is achieved with this phase, the oscillation output pulse will rise at a phase much later than the beginning of the vertical blanking of the video signal. If the vertical output circuit 7 is driven by this pulse, the retrace period (output pulse width) of the vertical output circuit 7 can only take a maximum of 1511, and if it is larger than this, it will appear at the top of the scanning line on the cathode ray tube screen. There is a possibility that the video signal enters the retrace period at the portion of the video signal, and that fraction may not be output. Furthermore, the width of this output pulse is closely related to the power consumption of the vertical output circuit, and the wider the pulse is designed, the lower the power consumption of the circuit will be. However, for the reasons mentioned above, the conventional circuit is designed so that the output pulse width is approximately 15H. This would consume approximately 3.5W of power using the conventional method. The present invention aims to reduce this power consumption, and embodiments of the present invention will be described below. FIG. 3 shows one embodiment of the present invention, and the same parts as those in FIG. 1 are given the same numbers and their explanation will be omitted. The feature of this embodiment is that the signal C (FIG. 4C) obtained by integrating the synchronization signal is amplified by the switching amplification and differentiation circuit 11 to become the signal D (FIG. 4D),
This was differentiated to become a signal E (Fig. 4 F), the time of that signal was delayed to obtain a signal F (Fig. 4 F), and the signal was frequency-divided by 1/262.5 from the horizontal oscillation circuit 3. The signal is reset to form a signal G (G in FIG. 4), and this signal is input to the vertical output circuit 7. 9 is a reset pulse generation circuit, 10 is 1/262. It is a disguised circuit.

Therefore, the phase relationship of those signals will be explained with reference to FIG. A
is the video signal, B is the synchronization separation output, and C is the integrated signal.Currently, this signal C is amplified, but at the switching level shown in the figure. If the signal is amplified, the resulting signal D and its differential signal E will lag approximately 1H behind the vertical synchronization signal (however, this 1H will vary somewhat depending on the configuration of the integrator, the selection of constants, and the setting of the switching level. ). This means that the position is delayed by 4H from the start of vertical blanking of signal A. Next 1/26
2. If a circuit as shown in FIG. 5 is used as one means of the frequency dispersion circuit 9, its pulse width will be 7.5H as shown in FIG. 6a. Even if the signal F shown in FIG. 6b is 1/262 in FIG. If the frequency adjustment circuit is reset, its output signal will become the signal shown in G in FIG.

If this signal G is used to drive the vertical output circuit 7, the rising phase will match the beginning of the vertical blanking of the video signal, so the blanking period width of the vertical output circuit (
This makes it possible to increase the output pulse width to 21H. If a vertical output circuit is designed using such a synchronous circuit, the output circuit will be the same as the conventional one, but by changing the design of the deflection coil, the vertical output/output circuit will operate with an experimental power consumption of 2.4 W. Become.

1/262 as shown in Figure 5. I explained only the 1/262 circuit, but what kind of 1/262. Even in the confusing circuit,
It is possible to change the delay time of the reset pulse F (including no delay).

FIG. 7 shows an example of the reset pulse generation circuit 9 in FIG. 3. This device is a circuit that delays signal F by 3.5H. Further, as a clock signal, a signal (2fH=J) that is horizontally synchronized at twice the horizontal frequency is used.
F2 and F3 are T-type flip-flops. If the signal is input to T of the clock input F1 and reset R is applied by signal E, a pulse delayed by 3.5H from the falling edge of E will be generated. FIG. 8 shows the signal waveform. As described above, according to the present invention, it is possible to obtain a vertical synchronization device that can significantly reduce power consumption, which is of high industrial value.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional vertical synchronizer,
2A, B, C, D, E, F, G, H are waveform diagrams for explaining the device; FIG. 3 is a block diagram of the vertical synchronization device in an embodiment of the present invention; FIG. 4 A, B, C, D, E,
F, G, H are waveform diagrams for explaining the circuit, Figures 5 and 7.
Each figure is a block diagram of a part of the same device, Figure 6A
, b, and FIG. 8 are waveform diagrams for explaining the device. 1... Synchronous separation circuit, 5... Integrating circuit, 7... Vertical output circuit, 8... Deflection coil,
9...Reset pulse circuit, 10...1/
262.5 frequency divider circuit, 3...horizontal oscillation circuit, 11...
...Switching amplification and differentiation circuit.

Claims (1)

[Claims] 1 A synchronization separation circuit that separates a synchronization signal from a video signal, a horizontal oscillation circuit, a horizontal output circuit driven by the output of this horizontal oscillation circuit, and a horizontal synchronization signal of the synchronization signals and a horizontal output circuit driven by the output of the horizontal oscillation circuit. horizontal AF that synchronizes the horizontal oscillation circuit with the horizontal synchronization signal using an output signal;
C circuit, an integration circuit that integrates the synchronization signal and removes the horizontal synchronization component, and a switching amplification and differentiation circuit that amplifies and differentiates the output signal of the integration circuit at a predetermined switching level and outputs a differential signal. a frequency divider circuit that divides the output signal of the horizontal oscillation circuit to create vertical frequency pulses; a reset pulse is created by delaying the differential signal for a predetermined time; and the reset pulse resets the frequency divider circuit. and a reset pulse generation circuit that synchronizes the pulse of the vertical frequency with the vertical synchronization signal,
A vertical synchronization device characterized in that an output signal whose phase matches the phase 3H before the vertical synchronization signal is obtained from the frequency dividing circuit, and this output signal is applied to the vertical output circuit.