JPS6054628B2 - Logic circuit automatic inspection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic logic circuit testing device for testing the performance of complex logic circuits such as electronic computers.

In general, in equipment such as electronic computers, due to the large-scale adoption of high-density integrated circuits such as MSI and In testing, a huge amount of test input data given from the outside is applied to the circuit under test, the data at the output terminal is detected, and the quality of the circuit under test is determined by comparing the output data with reference output data given from the outside. It is necessary to perform a series of operations at high speed, such as determining whether a product is defective or defective.

A conventional automatic inspection device of this type will be explained with reference to FIGS. 1 and 2.

In Fig. 1, C is a control computer that has a data interface function with the outside and controls the operation of the entire device, I temporarily stores n series of test input data, and applies data to the circuit under test U at high speed when performing a test operation. An input data storage device D having the function of An S-phase clock pulse generator that operates a flip-flop circuit etc., D2 is its drive circuit group, and P is the circuit under test U.
o is an output data storage device of n series which temporarily stores the data of the detection circuit group P; S is the control computer C's output terminal signal; The drive circuit groups D, , D are connected to the input terminal group of the circuit under test U by a command signal. This switch circuit group has the function of connecting any circuit of the detection circuit group P to the output terminal group of the circuit under test U. FIG. 2 shows the internal structure of the input data storage device I in FIG.

In FIG. 2, M is 1 for n input drivers at the same time,
2,..., an mxn storage element matrix that supplies m pieces of data in m order, AD is an address recorder/decoder with m output terminals, AC is an address counter,
R is the command signal from the control computer C and the clock pulse generator K
This is a control circuit that controls the drive, read, and write signals of the address counter according to the timing from . In an automatic test device having such a configuration, in order to test whether the logical function operation of the circuit under test U is performed correctly, first, the input terminal of the circuit under test U is connected from the control computer C to the switch circuit group S. Tested circuit U according to the output terminal arrangement
A connection command signal between the drive circuit groups Dl and D2 and the detection circuit group P is sent, each switch circuit of the switch circuit group S operates, and the circuit under test U is connected to the automatic test device. Next, input data from the control computer C to the input data storage device 1 is
pieces of test data are transferred, written into the input data storage device 1, and stored. Next, a test execution command signal is issued from the control computer C, the clock pulse generator K is driven, and a clock pulse is applied to the circuit under test U via the drive circuit group D2 and the switch circuit group S.

At the same time as the completion of the test, data is read from the input data storage device 1, and the test data is applied to the input terminal of the circuit under test U via the drive circuit group Dl and the switch circuit group S, so that the circuit under test U operates. Start. Next, after the standard time of the operating speed of the circuit under test U determined by the circuit configuration of the circuit under test U and the operating speed of the constituent elements has elapsed, the data at the output terminal of the circuit under test U is transferred to each of the detection circuits P. The logic level is determined by the detection circuit and the result is written to the output data storage device 0. Next, the clock pulse generator K is also driven by a signal from the control computer C.

Thereafter, such operations are repeated a maximum of m times, and the input data from the control computer C is first transferred to the storage device 1. When the transfer of the transferred data is completed, the inspection of one unit is completed, and the data accumulated in the output data storage device 0 is transferred to the control computer C, and the control computer C uses the criteria given in advance from the outside. Output data and output data storage device 0
A comparison is made with the data transferred from the test circuit U, and it is determined whether the operation of the circuit under test U is good or bad.

When this is completed, the control computer C checks whether all the test data regarding the circuit under test U given in advance from the outside has been transferred to the input data storage device 1, and if there is any remaining data, it is input from the control computer C. Data transfer to the data storage device 1 and write operation in the input data storage device 1 are performed, and the following operations are performed. By repeating such operations, the logic operation of the circuit under test U is tested. The conventional automatic inspection device as described above has the following drawbacks. First, theoretically, there are 2n types of test input data for a logic circuit with n input terminals, and one test unit (logic circuit printed circuit board, etc.) of a logic circuit of an electronic computer is usually The number of input terminals is several hundred, and it is practically impossible to perform inspection using all 2n types of input data. As an alternative, various software methods have been devised that use computers to extract only valid data from a huge amount of inspection data, or to combine and compress multiple data into a single data set, and are generally automated. Inspection data given to the inspection device is created using these methods. For this reason, the inspection input data necessarily includes data that could not have been predicted at the circuit design stage, and since data is generally handled at two levels: logic ゜゜0゛ and logic ゜"1", It is possible to handle transient phenomena caused by delay times and their irregularities, one-shot circuits that operate by ignoring clocked pulses, so-called asynchronous elements such as delay circuits, and the operation of circuits with transiently undefined values such as latch circuits. Because of the difficulty, it is not possible to sufficiently test the logic circuits including them, and because the output data detected for the same human input data is not constant and unstable, it is impossible to determine whether it is good or bad. Second, the software method described above can obtain complete test data for the circuit when the circuit under test U is composed of only so-called combinational circuits.
It is a well-known fact that complete test data cannot necessarily be obtained when a so-called sequential circuit such as a flip-flop circuit is included.

As a solution to this problem, so-called testable logic circuits are constructed in electronic computers and the like. The block diagram of FIG. 3 shows an example of a circuit U to be tested that includes a sequential circuit, that is, a logic circuit in which a combinational circuit and a sequential circuit are separated via gates to facilitate testing. In Fig. 3, CO is a combinational circuit having external input terminals 1, 2, . . . , i and external output terminals 1, 2, . . . , J, Fl, F2,
..., Fx are x sequential circuits having external input/output terminals 11, , 10 for testing and forming a shift register, and G is an input between the combinational circuit CO and the sequential circuits Fl, F2, ..., Fx. This is a gate circuit that opens and closes the output data line using a signal from an external terminal k. To test a logic circuit configured in this way, first close the gate circuit G by a signal from the external terminal k, and then connect the combinational circuit CO and the sequential circuit Fl.
, F2, . . . , FO are disconnected, a binary code sequence of length Set.

Next, open the gate circuit G and connect the combinational circuit CO and sequential circuit F.
l, F2,... After performing the test operation, the gate circuit G is closed and the test output terminal L is connected. The sequential circuit Fx,..., F2, Fl
The state value at that time is detected after X shift operations. When performing this test operation using the apparatus shown in FIG. 1, the input data transfer time from the control computer C to the circuit under test U is Tl, and the output data transfer time from the circuit under test U to the control computer C is TO. Then, the time required for m-step inspection is as follows, and the inspection time for a general circuit is m(Ti+TO
), and for circuits where the value of x is large and the number m of required test data is large, the increase in test time cannot be ignored in practice.

This invention was made to eliminate the above-mentioned drawbacks, and instead of having one input data storage device 1 and one output data storage device 0 shown in FIG. Read and write cycles (
A group of storage devices with different frequencies) or different time axes are installed.

This invention will be explained below. FIG. 4 is a block diagram showing an embodiment of the present invention, and is a device capable of testing a circuit under test U having n input terminals and n output terminals, similar to the automatic testing device shown in FIG. 1. The symbols C, K, Dl, D2, S, and P in this figure have the same functions and configurations as those explained in FIG. 1, and 11, 12, 1
, 01 are input or output data storage devices each having the basic configuration shown in FIG. 2, and 14, 0 . is a high-speed shift register type input or output data storage device (its basic structure is omitted).

The input data storage device 11 has an operating frequency f (Hz) and the number of inputs and outputs is 50, and the input data storage device 12 has an operating frequency f/A.
(Hz) (A is a constant value), and the number of inputs and outputs is 5α.The input data storage device 13 has a frequency f (Hz), but compared to the input data storage device 11, the phase is shifted by a time t, and the number of inputs and outputs is 50, 14 is the frequency FXB (Hz) (B is a constant value), the number of inputs and outputs is 1, and the output data storage device 01 is the frequency f (Hz)
The number of inputs and outputs is 200, and the output data storage device Q2 has a frequency of F.
It is XB (Hz) and has 1 input/output. Next, the inspection operation will be explained.

When testing the circuit to be tested U, the control computer C goes to the switch circuit group S, and then from the control computer C to the input data storage devices 11,1. , 13, 14 (1 in the case of FIG. 1), from the control computer C to the clock pulse generator K, from the clock pulse generator K to the circuit under test U, input data storage devices 11 to 1.
The order of signal transfer operation from the circuit under test U to the circuit under test U, from the circuit under test U to the output data storage devices 01 and 02, and from the control computer C to the output data storage devices 01 and 02 is exactly the same as in the device shown in FIG. be. The circuit under test U includes a flip-flop circuit whose output value becomes temporarily unstable due to the delay time of the constituent elements of the input circuit, and the circuit under test is connected to the input circuit. When the input terminals of U are the detection circuits Pl and P2, the switch circuit group S receives data from the input data storage device 11 to the detection circuit P1, and receives data from the input data storage device 11 to the detection circuit P2 according to a command signal from the control computer C. It is connected to receive data from 13. The phase shift time t between the input data storage devices 11 and 13 at this time is larger than the delay time between the maximum number of connected stages of elements constituting the circuit under test U. Furthermore, when the circuit under test U includes a one-shot circuit with a large delay time, the input terminal of the circuit under test U related to the circuit is connected to the input data storage device 12 having the operating frequency F/A. Test circuit U is tested. In this way, the circuit under test U, which is a combination of several circuits with different operating speeds, is
The input terminal groups related to each of the groups are divided into several groups depending on the size of the time width, and are connected to the input data storage device corresponding to the operating time by the switch circuit group S, thereby eliminating time lag. A compensated test is performed. At this time, the output data of the circuit under test U is stored in the output data storage device 01 via the detection circuit P, and is transferred to the control computer C at the end of one unit of test execution. Depending on the detected timing, the control computer C may contain useless data, and the control computer C may store the used input data storage device 11.
14 and the operating time of the output data storage devices 01 and 02, the output data is selected using general software means and the test results are determined. Next, when the circuit under test U is configured with the shift register type logic that is easy to test as shown in FIG. Output terminal 1.

A high-speed output data storage device 02 is connected to the combinational circuit CO, and an input data storage device 11 and an output data storage device 01 are connected to the input terminal group of the combinational circuit CO for inspection. As a result, data transfer to the sequential circuits Fl, F2,...FO is performed at high speed, and the overall test time is determined by the test time of the combinational circuit CO, so it is almost the same as a general circuit. It is possible to reduce the inspection time to approximately As explained in detail above, in this invention, the input data storage device and the output data storage device are divided into a plurality of units each having a different operating cycle or phase, so that element delay Multiple input data storage devices can also be used for logic circuits where the values of the output terminals detected are unstable due to uneven operation times of the constituent circuits, and it is difficult to determine the criteria for determining whether the circuit is good or bad. By making an appropriate selection, it is possible to always maintain a constant criterion. In addition, for complete logic function testing, the so-called easy-to-test circuit was constructed so that it could be separated into a combinational circuit section and a sequential circuit section that had input/output terminals for testing and that formed a shift register. Logic circuits also have the advantage of being able to be tested in about the same amount of time as other general logic circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a conventional automatic testing device, FIG. 2 is a block diagram showing the basic configuration of an input data storage device of the automatic testing device, and FIG. 3 is a block diagram showing an example of a circuit to be tested. , FIG. 4 is a block diagram showing an embodiment of the present invention. In the figure, C is a control computer, 11 to 14 are input data storage devices, 01 and 02 are output data storage devices, Dl and D2 are drive circuit groups, S is a switch circuit group, P is a detection circuit group,
K is a clock pulse generator, and U is a circuit to be tested.

Claims (1)

[Claims] 1. Send a connection command signal from the control computer to the switch circuit group according to the arrangement of the input terminals and output terminals of the circuit under test, connect the circuit under test, and store the test data from the control computer in the input data storage device. Then, the test data is applied to the circuit under test according to a test execution command signal from the control computer, the result is stored in the output data storage device, and the control is performed based on the data stored in the output data storage device. In an automatic testing device that uses a computer to determine whether the circuit under test is good or bad, a plurality of input data storage devices each having a different operating cycle or phase for temporarily storing test data and applying test data to the circuit under test are used as the input data storage device. 1. An automatic logic circuit testing apparatus characterized in that an input data storage device is provided, and a plurality of output data storage devices corresponding to the plurality of input data storage devices are further provided as the output data storage devices.