JPS6055917B2 - semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high speed static memory.

An example of a conventional static memory device is shown in FIG.

Memory cells are arranged in m rows and n columns, m bit line pairs (BLi, BLi; i=1, ... m in the row direction) and n word lines (WLk; = 1 in the column direction). ,...n
) are placed. The bit line is connected to one data line pair (DL, DL) via a multiplexer, and the input terminal of the output circuit is connected to the data line. The memory cell is composed of four transistors Q1 to Q and two load elements 1, as shown in FIG.

A signal of a memory cell is read out to a data line via a bit line and a multiplexer. In a conventional asynchronous static memory, since a memory cell at a certain address is always selected, the signal of that memory cell remains read onto the data line.

Therefore, when a new read cycle begins and a memory cell at a different address is selected, the signal from one cycle before remains on the data line, and in order to read a new signal, the remaining signal must be removed. It is necessary to cancel the signal that is on.

The operation time required to cancel the remaining signals has been a major cause of slowing down the read operation of the static memory. The present invention provides l (≧2) data line pairs to
The feature is that the data line is switched every cycle to perform the read operation, and its purpose is to cancel the signal from the previous cycle remaining on the data line before the read operation to increase the speed. The aim is to increase the speed by using a sense amplifier using a flip-flop circuit, which has been difficult. FIG. 3 shows a first embodiment of the present invention, in which memory cells are arranged in m rows and n columns, and m bit line pairs (BLi, BLi; i=1, . . . m )
, n word lines (Wk; k=1,...
・In a memory device in which l(≧2) data line pairs (DLk, DLk; k=1,...L
) and a multiplexer (MUXi) arranged in m rows x 1 column
j; i=1,...M, j=1,...n
), and each bit line pair (BLi, BLi; i=1, .
・・・・・・m) is connected to one multiplexer (MU
Xil,...,MUXil;i=1,...
... m) input terminal pair, and each data line. Versus (DL
j, DLj; j=1,...l) respectively into m multiplexers (MUXlj,...MUXm
Connect to the output terminal pair of j; j=1,...1),
A precharge circuit (Pj; j=1,...
. . l) are provided, and a connection portion 3 is provided between the I data line pairs and the output circuit.

As the multiplexer, one using a transfer gate shown in FIG. 4a or one using a differential amplifier circuit shown in FIG. 4b can be used.

As the precharge circuit, a circuit using NMOS shown in FIG. 5a or a circuit using PMOS shown in FIG. 5b can be used. As a control signal, a data line selection signal (Fj;
j=1,...1) and precharge operation signal (G
j:j=1,...l) and column selection signal (Ci
;i=1,...m), and Gj is “High
When h, the precharge circuit operates and Ci becomes 6'High.
h55 and Fj is 66High55, one bit line pair BLi, BL.
i and data line pair DLj, DLj are electrically connected.

The read operation will be explained using the data line pair DLk, DLk.

In this case, it is assumed that the data line pair DLj'', ``drunk'' was used one cycle ago. In a new read cycle, the column selection signal Ci corresponding to the memory cell to be read is set to ``High - 1 cycle ago. The unlit data line selection signal Fj (j=j'') is set to ``High'', and the data line pairs DLj'' and DLj other than the data line pairs DLj'' and ``■'' used in the previous cycle are set to ``High''. Take out the signal.
At this time, by setting the precharge operation signal Gj'' to 6High, the signal remaining on the data line DLj'', which was used one cycle before, is canceled.Then, the signal remaining on the data line pair DLj, DLj is The extracted signal is input to the output circuit via the connection part.By sequentially switching the data line pair every cycle and performing the read operation, the signals remaining on the data line pair are inputted before the read operation. The data line signal inversion time can be reduced.

FIG. 6 shows a second embodiment of the present invention, in which the connecting portion of the first embodiment is connected to one sense amplifier (SAj; j=1, . . . using a flip-flop circuit driven by a control signal HJ).・
...l) and a switching circuit 4, one pair of data lines is connected to each pair of input terminals of one sense amplifier, and each pair of output terminals of one sense amplifier is connected to a pair of switching circuits. , and the output terminal pair of the switching circuit "4" is connected to the input terminal pair of the output circuit.
As the sense amplifier, a circuit constructed of MG as shown in FIG. 7a, a circuit constructed of NMOS and PMOS as shown in FIG. 7b, etc. can be used. In conventional static memories, flip-flop circuits cannot be used as sense amplifiers, but in the present invention, the data lines can be brought into a balanced state before the read operation, so they can be used.

As a switching circuit, one can be used that is constructed of a transfer gate as shown in Fig. 8 and is electrically connected to the output terminal of the sense amplifier SA] and the input terminal of the output circuit by setting the control signal Sj to '6High32. . In this second embodiment, the operation of sequentially switching the data lines is the same as in the first embodiment; the difference is that the connection is made to the data line after a signal appears on the data line in use. The method is to drive a sense amplifier and electrically connect the output terminal of the sense amplifier to the input terminal of an output circuit using a switching circuit. Further, this second embodiment has the same effect as the first embodiment, and furthermore, by providing a sense amplifier using a flip-flop circuit, it has the effect of rapidly amplifying the minute signal appearing on the data line. .

With this configuration, the driving force for the output circuit can be increased, so the operating time of the data line and output circuit can be shortened.
Furthermore, since the signal amplitude of the bit lines electrically connected via the multiplexer can be reduced, the signal inversion time of the bit lines can also be shortened. FIG. 9 shows a third embodiment of the present invention, in which the connecting portion of the first embodiment is replaced by one transfer gate controlled by a control signal Ej and a flip-flop circuit driven by a control signal Hj. It is constructed using one sense amplifier and a switching circuit 4, and one data line pair is connected to each input terminal pair of one transfer gate.
Each pair of output terminals of one transfer gate is connected to a pair of input terminals of one sense amplifier, and each pair of output terminals of one sense amplifier is connected to one pair of input terminals of a switching circuit. The pair of output terminals of one sense amplifier is electrically connected to the pair of input terminals of the output circuit.

As a transfer gate, a circuit with one transistor as the basic gate shown in Figure 10a or a circuit with N as shown in Figure 10b
A device with a MOS, pMOSl set as the basic gate can be used. The operation of sequentially switching the data lines is the same as in the first embodiment; the difference is that the signal of the data line pair in use appears at the input terminal pair of the sense amplifier via the transfer gate, and then the signal of the data line pair is and the sense amplifier are electrically disconnected, and then the sense amplifier is driven, and a switching circuit electrically connects the pair of output terminals of the sense amplifier to the pair of input terminals of the output circuit.

An example of the clock waveform when operating this embodiment is shown in the 11th example.
As shown in the figure. The third embodiment described above has the same effect as the first and second embodiments, and also enables high-speed sense amplifier operation because the data line with a large load capacity is disconnected from the sense t-pump when driving the sense amplifier. This has the effect of

As explained above, data lines are multiplied by l (≧2) and
By switching and operating each cycle, it is possible to cancel signals remaining on other data lines while one data line is being used, thereby enabling high-speed read operations.

Furthermore, since sufficient time can be secured to bring the data lines into an equilibrium state before the read operation, a flip-flop circuit, which has been difficult to introduce in the past, can be used for the sense amplifier, thereby enabling high-speed read operations.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional static memory, FIG. 2 is a circuit diagram of a memory cell, FIG. 3 is a configuration diagram of a first embodiment of the present invention, and FIGS. 4A and 4B are circuit examples of a multiplexer. Fifth
Figures A and b are circuit examples of a precharge circuit, Figure 6 is a second embodiment of the present invention, Figures 7A and b are circuit examples of a sense amplifier, Figure 8 is a circuit example of a switching circuit, and Figure 9 is a circuit example of a switching circuit. The figure shows a third embodiment of the present invention, FIGS. 10A and 10B show examples of transfer gate circuits, and FIG. 11 shows an example of clock waveforms in the third embodiment. CELLll, CELLl2, ~, CELLmn...
...Memory cell, (BLl, BLl), (BL2, B
L2. , ~, (BLn, ■ edition)... Bit line pair, WLl, WL2, ~, WLn... Word line,
MUXll, MUXl2, ~, MUXfil...
・Multiplexer, (DLl, DLl), (DL2, D
L2), ~, (DLl, DD')... Data line pair, Pl, P2, ~, P1... Precharge circuit, SAl, SA2, ~, SAI●●●●● ●Sense amplifier, TGl, 'TG29~9TG1●●●◆●◆Transfer gate, Fl, F2, ~, Fl... Data line selection signal, Gl, G2, ~, GI... Precharge circuit drive signal, Cl, c2~, Cm...
...Column selection signal, Hl, H2, ~, H1...
・Sense amplifier drive signal, Sl, S2, ~, S1...
...Switching circuit control signal, El, E2, ~, El...
...Transfer gate control signal, Q1ゞQll9Q
l5ゞQ2O9Q23ゞQ sum Q379QOOOO3N channel field effect transistor, Ql2, Ql3, Ql
OQ2l9Q229Q29ゞT349Q399Q4OO
O″″P-channel field effect transistor (arrow in the figure indicates P-channel MOS)
, Q35, Q36... N-channel or P-channel field effect transistor.

Claims (1)

[Claims] 1. Memory cells are arranged in m rows and n columns, and m bit line pairs (BLi, @BLi@; i=1, 2, . . .
..., m), n word lines (WLk; k=1,
2, ..., n), one (≧2) data line pair (DLj, @BLj@;j
= 1, 2, ..., l) and a multiplexer (MUXfj; i = 1, 2, ..., arranged in m rows x l columns)
..., m, j=1, 2, ..., l), and each bit line pair is connected to l multiplexers (MU
Xi1,..., MUXil; i=1, 2,...
. . . m) input terminal pairs, and each data line pair is connected to m multiplexers (MUX1j, . . .
...MUXmj; j=1, 2, ......, l)
A precharge circuit (Pj; j=1) that is connected to the output terminal pair of the
, 2, . . . , l) are provided on each data line pair,
A memory device characterized in that a connection portion is provided between l data line pairs and an output circuit. 2. The connection section is configured by using l sense amplifiers using flip-flop circuits and a switching circuit, and l data line pairs are respectively connected to l sense amplifier input terminal pairs, and l sense amplifiers are connected to l sense amplifier input terminal pairs. 2. The memory device according to claim 1, wherein the output terminal pairs of the amplifier are selected as child pairs among the l input terminal pairs of the switching circuit and are electrically connected to the input terminal pairs of the output circuit. . 3 The connection section is configured using l transfer gates, l sense amplifiers using flip-flop circuits, and switching circuits, and l data line pairs are connected to input terminal pairs of l transfer gates, respectively. Connect the output terminal pairs of the l transfer gates to the input terminal pairs of the l sense amplifiers, and connect the output terminal pairs of the l sense amplifiers to the l input terminal pairs of the switching circuit. 2. The memory device according to claim 1, wherein the output terminal pair of one sense amplifier is selected by the switching circuit and electrically connected to the input terminal pair of the output circuit.