JPS6056009B2 - gain control circuit - Google Patents

Description

Detailed Description of the Invention The present invention extracts the output from any collector terminal of an amplifier connected in a differential or bi-differential format and applies a gain control voltage to the base of the differential or bi-differential amplifier. The present invention relates to a gain control circuit that performs gain control.

FIG. 1 is a circuit diagram showing an example of a conventional gain control circuit.

In FIG. 1, in an amplifier using a transistor 1 with terminal a as an input terminal and terminal c as an output terminal, the voltage applied between the bases of differential amplification transistors 3 and 4 is determined by the gain control voltage applied to the base of transistor 9. is varied, thus controlling the ratio of the signal input voltage applied to the base of transistor 1 to the signal output voltage developed at load resistor R15, and thus the voltage gain of the amplifier. Here terminal c
The output signal taken out from is amplified by an arbitrary amplifier 100, and further converted into a DC signal by a rectifier circuit 200, and when this is applied to the g terminal of the gain control circuit shown in FIG. 1, the input signal applied to the input terminal a is An M°C circuit can be designed by designing the voltage amplifier and rectifier circuit after terminal c so that the DC signal voltage applied to terminal g also increases in the direction in which the voltage increases. The characteristics of conventional gain control circuits are:
The purpose is to control the gain by changing the bias current applied to the terminal g and flowing through the load resistor R15. Note that in the example of FIG. 1, the bias of terminal d is normally selected to be higher than the bias of terminal c, and when no control voltage is applied to terminal g, transistor 4
The operating point is set so that it becomes a cutoff and operates at maximum gain. Now, the problems of the conventional gain control circuit shown in FIG. 1 will be described.

First, it is susceptible to the influence of noise contained in the control voltage, and the internal noise generated from the gain control circuit is also large, so that the signal-to-noise ratio (S/N) at the output terminal c may not be very good. That is, the external noise applied to the gain control terminal g is amplified by the mutual conductance of the transistor 9 and the resistor Rl9, is generated at the base input terminals of the differential amplifier transistors 3 and 4, and is further added to the noise generated by the resistor Rl9. , is output as noise to output terminal c. Therefore, the signal-to-noise ratio at input terminal a is deteriorated by the above-mentioned noise. Second, it is difficult to set the control voltage at which gain control begins, and furthermore, it is difficult to arbitrarily set the loop gain of an automatic gain control circuit (AGC) and the control voltage at which gain control begins.

That is, the input control signal level at which gain control begins is the point at which the collector current of transistor 9 begins to flow and resistor Rl.
Determined by 9. In order to reduce the input control signal level at which this gain control starts, the resistor Rl8 may be set small or the resistor Rl9 may be set large. However, since the input control signal level at which gain control begins depends on the resistance values of the resistors Rl8 and Rl9, it is susceptible to manufacturing variations in the resistance values of these resistors. Particularly on integrated circuits, the influence of manufacturing variations is unavoidable, and it is difficult to set the input control signal level at which gain control begins. Moreover, this setting simultaneously increases the ratio between the resistor Rl8 and the resistor Rl9, increasing the AGC loop gain in this portion. Therefore, when the gain control circuit shown in FIG. 1 is used in various automatic gain control circuits, the input signal level (proportional to the input control voltage) at which automatic gain control starts and the ACC loop are required. The gain cannot be arbitrarily designed. The conventional gain control circuit shown in FIG. 1 suffers from the problems described above, which are also dependently related.

In other words, the first problem can be improved to some extent by lowering the gain of the automatic gain control circuit mentioned in the second section, but on the other hand, for this reason, the input signal where automatic gain control (AGC) starts to apply It is extremely difficult to achieve both since there are restrictions on level settings. An object of the present invention is to provide a gain control circuit that solves the first and second problems mentioned above all at once.

A gain control circuit according to the invention includes a differential amplifier circuit including first and second transistors whose emitters are connected in common, and a means for applying an input signal to the common emitter of the differential amplifier circuit, connected in a differential manner. and a gain control section having a multi-emitter transistor as a load, a gain control voltage being applied to the base of at least one of the third and fourth transistors, Each emitter of the multi-emitter transistor is connected to each base of the first and second transistors, and an output is obtained from the collector of at least one of the first and second transistors. .

Next, the present invention will be explained in more detail with reference to the drawings.

An embodiment of a gain control circuit according to the present invention is shown in FIG.

In FIG. 2, transistors 1, 3, 4 and resistor 11
, 15 are transistors 1, 3, and resistor 11 in FIG.
, 15. Also, terminals A, b, c, f,
k corresponds to A, b, c, f, and k in FIG. Transistor 10 is added differentially with transistor 9,
The emitters of these transistors 9, 10 are resistors 20, 2
1 to the current source resistor 18, respectively. A multi-emitter transistor 17 having two emitters is provided as a load for the differentially connected transistors 9, 10, and the two emitter voltages of this transistor are supplied to the bases of the transistors 3, 4, respectively. The base of transistor 3 is further connected to terminal K via resistor 22. The collector of transistor 17 is terminal b
It is connected to the. The feature of the circuit of the present invention shown in FIG. 2 is that the output obtained at terminal c is connected to a differential amplifier, transistors 9 and
0 base terminal g or h, and the change in this gain control voltage corresponds to the voltage between the base and one emitter of the multi-emitter follower transistor 17 with reference to the terminal d set to a predetermined bias voltage. The purpose is to control the gain by changing the signal current flowing through the load resistor R15 through the transistors 3 and 4 of the differential amplifier.

At this time, a constant bias voltage is applied to the terminal g or h to which no gain control voltage is applied and the terminal f.
It is omitted in the figure. Next, the advantages of the gain control circuit according to the present invention shown in FIG. 2 will be described. First, the signal-to-noise ratio (S/N) characteristics are significantly improved compared to the conventional gain control circuit shown in FIG. That is, the second
In the figure, transistors 3 and 4 forming a differential amplifier
The base terminal of is connected to a multi-emitter follower transistor 17 whose base is connected to a reference voltage application terminal d (grounded in AC terms), and the noise generated here is similar to that of the conventional circuit in Figure 1. is generally relatively large (several K
Ω) While the noise is caused by the resistor Rl9, it is due to the emitter resistance of the emitter follower transistor 17, which has a very low impedance (26Ω when the collector current is 1 mA), for example, several hundredths of that of the conventional one. , significantly possible. Second, the gain control circuit according to the present invention is
There is an advantage that the AGC loop gain and the control voltage at which gain control starts can be independently set as desired.

That is, the input signal voltage value at which gain control starts can be arbitrarily set by the bias voltage applied to either the comparison voltage terminal h or g, as described later. Since the AGC voltage applied to the other terminal h or g is generated by the amplifier circuit 100 and the rectifier circuit 200 independently of the bias voltage applied to either the comparison voltage terminal h or g, this bias voltage The settings do not change the AGC loop gain. Therefore, the AGC loop gain and the control voltage at which gain control starts can be set independently. Thirdly, compared to the conventional gain control circuit (FIG. 1), the input control signal voltage value at which the gain control starts is as follows in the gain control circuit according to the present invention:
Since transistors 9 and 10 constitute a differential amplifier, the comparison voltage is applied to either one of the comparison voltage terminals h or g. Determined by bias voltage. When the N° C. voltage applied to the other comparison voltage terminal h or g becomes larger than this bias voltage, gain control starts to work. Therefore, the voltage at which this gain control starts can be determined without being influenced by manufacturing variations in resistance values and the like. Also, if this bias voltage is made to have the same temperature characteristics as the AGC voltage,
Gain control characteristics are not affected by temperature changes. That is, in the gain control circuit shown in FIG.
10 and transistors 3 and 4 are each configured in a differential type, and transistor 17 is a multi-emitter transistor, so if the temperature characteristics of each transistor are made uniform, the control voltage applied to terminals G and h will be The operation of the gain control circuit is temperature compensated. Here, in order to make the temperature characteristics of each transistor uniform, it can be relatively easily achieved by configuring the circuit of the present invention on a semiconductor integrated circuit in which these transistors are formed on the same semiconductor chip. However, by this means, variations in the characteristics of each element can be reduced, and therefore variations in the input signal voltage at which gain control begins can be reduced. Further, by changing the emitter area ratio of each of the transistors 9 and 10 and the multi-emitter transistor 17, the gain control characteristics can be freely set. As described above, by using the gain control circuit according to the present invention, automatic gain control (AGC) having excellent characteristics can be achieved.
) The circuit can be easily designed.

Furthermore, according to the configuration of this embodiment, transistors 9 and 1
The emitter of 0 is connected to the current source resistor 18 through resistors 20 and 21.
Since the multi-emitter transistor 17 has two emitter regions formed within a single base region, it is possible to arbitrarily lower the loop gain of the gain control circuit. The electrical characteristics of the outputs obtained are very consistent, and this consistency is not affected by manufacturing variations.

Therefore, transistor 3 in the non-gain controlled state
.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional gain control circuit. FIG. 2 is a circuit diagram showing one embodiment of the present invention. 1,3
, 4, 9, 10 and 17...transistors,
11, 15, 20-21...Resistance, a...
...Signal input terminal, b...Power supply voltage supply terminal,
c...Signal output terminal, D, e, f...
DC bias terminal, G, h...gain control voltage application terminal, k...ground terminal.

Claims (1)

[Claims] 1. A differential amplifier circuit including first and second transistors whose emitters are connected in common, and a means for applying an input signal to the common emitter of the differential amplifier circuit, the transistors being connected in a differential manner. a gain control section having a multi-emitter transistor as a load; a gain control voltage is applied to the base of at least one of the third and fourth transistors; Gain control characterized in that each emitter of the multi-emitter transistor is connected to each base of the first and second transistors, and an output is obtained from the collector of at least one of the first and second transistors. circuit. 2. The gain according to claim 1, wherein one emitter of the multi-emitter transistor is connected to the collector of the third transistor, and the collector of the fourth transistor is connected to a power supply. control circuit.