JPS6056286B2 - Method for forming electrode windows in semiconductor devices - Google Patents
Method for forming electrode windows in semiconductor devicesInfo
- Publication number
- JPS6056286B2 JPS6056286B2 JP13369277A JP13369277A JPS6056286B2 JP S6056286 B2 JPS6056286 B2 JP S6056286B2 JP 13369277 A JP13369277 A JP 13369277A JP 13369277 A JP13369277 A JP 13369277A JP S6056286 B2 JPS6056286 B2 JP S6056286B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon dioxide
- film
- electrode window
- dioxide film
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置における電極窓の形成方法とくに乾
式エッチング技術を用いた電極窓の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming an electrode window in a semiconductor device, and particularly to a method of forming an electrode window using a dry etching technique.
集積回路において、半導体基板上を覆う厚い二酸化シリ
コン膜にあけた電極窓にアルミニウム配線を施こすと、
電極窓周囲の急峻な段差のため、アルミニウム配線の段
切れを生じる。このため、電極窓周辺にゆるい傾斜を設
けて上述の如き事故を防止している。電極窓周辺に傾斜
を設ける方法としては、たとえば、半導体基板上を覆う
厚い二酸化シリコン膜の表面に隣Pをドープして該膜の
表面のエッチレートを深部のそれより大きくした後、湿
式による選択エッチングを施こして電極窓を形成する方
法がとられる。In integrated circuits, when aluminum wiring is applied to electrode windows in a thick silicon dioxide film covering a semiconductor substrate,
Due to the steep step around the electrode window, breaks in the aluminum wiring occur. Therefore, a gentle slope is provided around the electrode window to prevent the above-mentioned accident. A method for forming a slope around the electrode window is, for example, by doping the surface of a thick silicon dioxide film covering the semiconductor substrate with P to make the etch rate on the surface of the film larger than that on the deeper part, and then wet selection. A method is used in which electrode windows are formed by etching.
しカルながら、湿式のエッチング法では、フォトレジス
トと二酸化シリコン膜との間にエッチング液が浸透する
などのため寸法精度が良くない。寸法精度を向上させる
ためには、乾式エッチング法を用いれば良いが、電極窓
の周囲にゆるい傾斜を設けることができない。However, the wet etching method does not have good dimensional accuracy because the etching solution penetrates between the photoresist and the silicon dioxide film. Dry etching may be used to improve dimensional accuracy, but it is not possible to provide a gentle slope around the electrode window.
本発明は、周辺に傾斜を持つた寸法精度の良い電極窓を
乾式エッチング法を用いて形成する新しい製造方法を提
供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a new manufacturing method for forming an electrode window with good dimensional accuracy and having a sloped periphery using a dry etching method.
その目的のために、本発明の半導体装置における電極窓
の形成方法は、半導体基板に形成した二酸化シリコン膜
上にレジスト膜を被着した後、電極窓形成領域上に位置
する該レジスト膜に、周辺に庇を形成した孔を設け、該
レジスト膜をマスクとして二酸化シリコン膜をイオン照
射と化学反応とを併用したエッチング方式により乾式エ
ッチングし、二酸化シリコン膜にゆるい傾斜を周辺に持
つた電極窓を形成することを特徴とするもので、以下実
施例について詳細に説明する。For that purpose, the method for forming an electrode window in a semiconductor device of the present invention includes depositing a resist film on a silicon dioxide film formed on a semiconductor substrate, and then applying the steps to the resist film located on the electrode window formation region. A hole with an eave formed around the periphery is provided, and the silicon dioxide film is dry-etched using an etching method using a combination of ion irradiation and chemical reaction using the resist film as a mask to form an electrode window with a gentle slope around the periphery of the silicon dioxide film. Examples thereof will be described in detail below.
第1図は半導体基板の一部にNPN型のトランジスタを
形成した後の断面図であり、図中1はN型のシリコン半
導体基板、2はN1厘の埋込層、3はN−型のコレクタ
領域、4はP−型のベース領域、5はN1厘のエミッタ
領域、6はアイソレーシヨン領域、7は表面を覆う二酸
化シリコン(SiO0)膜である。FIG. 1 is a cross-sectional view after forming an NPN type transistor on a part of a semiconductor substrate, in which 1 is an N type silicon semiconductor substrate, 2 is an N1 layer buried layer, and 3 is an N- type A collector region, 4 is a P-type base region, 5 is an N1 emitter region, 6 is an isolation region, and 7 is a silicon dioxide (SiO0) film covering the surface.
次に二酸化シリコン膜7の点線で示す位置にゆるい傾斜
をもつた電極窓を形成する工程を説明する。(1)まず
、二酸化シリコン膜7の上に、第2図に示す如く電子ビ
ームに感光するレジスト膜8を被着した後、マスク材を
その上に載置して電子ビームを照射し、露光を行なう。Next, the process of forming a gently sloped electrode window at the position indicated by the dotted line on the silicon dioxide film 7 will be described. (1) First, a resist film 8 that is sensitive to electron beams is deposited on the silicon dioxide film 7 as shown in FIG. Do this.
この時、該レジストの所要感度の3〜4倍程度の露光量
(〜10−4クロン/Cd)を与えると、該レジスト中
における電子ビームの散乱により第3図に示すように現
像の際レジスト膜8にあけた孔9の周辺には逆テーパが
生じ、庇91が形成される。(2)二酸化シリコン膜7
上に孔9を形成したレジスト膜8を被着した半導体基板
を2枚の対向した平面形電極を備えたプラズマエッチン
グ装置の陰極面上に装着する。そして、該プラズマエッ
チング装置内にフレオン系ガス(CxF2x+2(x=
1,2,3)、(HF3等)を主体としたガスを送り込
み、内部のガス圧を(0.1乃至1.0〔TOrr〕)
程度に保つた後、電極間に高周波電圧を印加する。 高
周波電圧の印加により、内部にガス放電が起り、このガ
ス放電により生じたイオン又はラジカルは陰極暗部領域
で加速され、陰極面に装着された半導体基板に対してほ
ぼ垂直方向に入射する。(3)入射したイオン又はラジ
カルはレジスト膜8に設けられた孔9を通つて二酸化シ
リコン膜7を照射して該膜7をエッチングし始める。At this time, if an exposure dose (~10-4 Cron/Cd) that is about 3 to 4 times the required sensitivity of the resist is applied, the scattering of the electron beam in the resist will cause the resist to become opaque during development as shown in Figure 3. A reverse taper is generated around the hole 9 made in the membrane 8, and an eave 91 is formed. (2) Silicon dioxide film 7
A semiconductor substrate with a resist film 8 on which holes 9 are formed is mounted on the cathode surface of a plasma etching apparatus equipped with two opposed planar electrodes. Then, Freon gas (CxF2x+2(x=
1, 2, 3), (HF3, etc.) is sent in, and the internal gas pressure is set to (0.1 to 1.0 [TOrr]).
After maintaining the temperature at a certain level, a high frequency voltage is applied between the electrodes. Application of a high-frequency voltage causes internal gas discharge, and ions or radicals generated by this gas discharge are accelerated in the cathode dark region and impinge on the semiconductor substrate mounted on the cathode surface in a substantially perpendicular direction. (3) The incident ions or radicals irradiate the silicon dioxide film 7 through the holes 9 provided in the resist film 8 and start etching the film 7.
この時のエッチング反応は、前記エッチングガスの解離
によつて生じたCF4ラジカルと二酸化シリコン膜との
化学反応により揮発性のSiF4が生成されることによ
るものと考えられている。また、プラズマエッチング装
置内のガス圧が前述の如く比較的に高いため、庇の二酸
化シリコンにもラジカルが一部供給され、該庇の下も浅
くエッチングされる。このため、二酸化シリコン膜7は
第4図に示すように、なだらかな傾斜を持つた部分10
を生じながらエッチングされて行く。なお、このエッチ
ングにより、レジスト膜8も点線から実線の部分まで消
耗する。ししながらその量は少ないためパターンの寸法
精度は維持される。(4)このエッチングを続行し、エ
ッチング領域がシリコン半導体基板に達したときエッチ
ングを中止する。The etching reaction at this time is thought to be due to the chemical reaction between CF4 radicals generated by dissociation of the etching gas and the silicon dioxide film to generate volatile SiF4. Furthermore, since the gas pressure within the plasma etching apparatus is relatively high as described above, some of the radicals are also supplied to the silicon dioxide in the eaves, and the area under the eaves is also shallowly etched. Therefore, as shown in FIG. 4, the silicon dioxide film 7 has a gently sloped portion 10.
It is etched while producing. Note that due to this etching, the resist film 8 is also consumed from the dotted line to the solid line. However, since the amount is small, the dimensional accuracy of the pattern is maintained. (4) Continue this etching and stop the etching when the etched region reaches the silicon semiconductor substrate.
第5図はエッチングが終了した直後の半導体基板の断面
図である。第5図からあきらかなように、二酸化シリコ
ン膜7にあけられた電極窓11の低面すなわち半導体基
板と接している部分の幅は、当初レジスチ膜8にあけら
れた孔9の上端の幅dとほぼ一致する。そしてあけられ
た電極窓11の周辺には、ゆるやかな傾斜面12が形成
される。(5)その後半導体基板をプラズマエッチング
装置から取り出した後、レジスト膜8を剥離し、通常の
方法で電極窓11部分にアルミニウム配線を施こす。FIG. 5 is a cross-sectional view of the semiconductor substrate immediately after etching is completed. As is clear from FIG. 5, the width of the lower surface of the electrode window 11 made in the silicon dioxide film 7, that is, the portion in contact with the semiconductor substrate is the width d of the upper end of the hole 9 originally made in the resist film 8. almost matches. A gentle slope 12 is formed around the opened electrode window 11. (5) After that, the semiconductor substrate is taken out from the plasma etching apparatus, the resist film 8 is peeled off, and aluminum wiring is applied to the electrode window 11 portion using a conventional method.
なお、通常のフォトプロセスでは、レジスト膜に逆テー
パを設けた孔をあけることは不可能なことである。Note that it is impossible to make a hole with a reverse taper in a resist film using a normal photo process.
しかしながら、本発明の方法は、レジスト膜にあけた孔
に庇を設けて、二酸化シリコン膜にイオン照射を受けな
い部分が生じるようにすればよいのであるから、フォト
プロセスを用いてフォトレジスト孔を設ける場合には、
第6図に示すように、二酸化シリコン膜7の上に感度の
異なる二種のフォトレジスト膜81,82を被着してフ
ォトレジスト81にあけた孔の幅d1をフォトレジスト
膜82にあけた孔の幅yよりも大きくして庇13を形成
すれば、前記実施例と同様の作用が期待できる。以上詳
細に説明したように、本発明によれば、乾式のエッチン
グを行なつているので、二酸化シリコン膜にあけた電極
窓の寸法精度は湿式エッチングによりあけた電極窓の寸
法精度よりもよくなるばかりか、電極窓の周囲にはゆる
やかな傾斜面が形成されるため、電極部分に行なわれる
アルミニウム配線に段切れを生じることがない。However, in the method of the present invention, all that is required is to provide an eaves over the holes drilled in the resist film so that there are parts of the silicon dioxide film that are not exposed to ion irradiation. If provided,
As shown in FIG. 6, two types of photoresist films 81 and 82 having different sensitivities were deposited on the silicon dioxide film 7, and the width d1 of the hole made in the photoresist 81 was made in the photoresist film 82. If the eaves 13 are formed with a width larger than the width y of the hole, the same effect as in the embodiment described above can be expected. As explained in detail above, according to the present invention, since dry etching is performed, the dimensional accuracy of the electrode window formed in the silicon dioxide film is better than that of the electrode window formed by wet etching. In addition, since a gentle slope is formed around the electrode window, no breaks occur in the aluminum wiring formed in the electrode portion.
図面の簡単な説明第1図乃至第5図は本発明の実施例を
説明するための工程断面図、第6図は他の実施例の部分
断面図てある。BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 5 are process sectional views for explaining an embodiment of the present invention, and FIG. 6 is a partial sectional view of another embodiment.
1はシリコン半導体基板、7は二酸化シリコン膜、8は
レジスト膜、9は孔、91は庇、11は電極窓、12は
傾斜面である。1 is a silicon semiconductor substrate, 7 is a silicon dioxide film, 8 is a resist film, 9 is a hole, 91 is an eave, 11 is an electrode window, and 12 is an inclined surface.
Claims (1)
ト膜を被着した後、電極窓形成領域上に位置する該レジ
スト膜に、周辺に庇を形成した孔を設け、該レジスト膜
をマスクとして二酸化シリコン膜をイオン照射と化学反
応とを併用した乾式エッチング方式によりエッチングし
、二酸化シリコン膜にゆるい傾斜を周辺に持つた電極窓
を形成することを特徴とする半導体装置における電極窓
の形成方法。1. After depositing a resist film on the silicon dioxide film formed on the semiconductor substrate, a hole with an eaves around the periphery is provided in the resist film located on the electrode window formation region, and the silicon dioxide film is deposited using the resist film as a mask. A method for forming an electrode window in a semiconductor device, comprising etching the film using a dry etching method using a combination of ion irradiation and chemical reaction to form an electrode window with a gentle slope around the periphery in a silicon dioxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13369277A JPS6056286B2 (en) | 1977-11-08 | 1977-11-08 | Method for forming electrode windows in semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13369277A JPS6056286B2 (en) | 1977-11-08 | 1977-11-08 | Method for forming electrode windows in semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5466768A JPS5466768A (en) | 1979-05-29 |
| JPS6056286B2 true JPS6056286B2 (en) | 1985-12-09 |
Family
ID=15110633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13369277A Expired JPS6056286B2 (en) | 1977-11-08 | 1977-11-08 | Method for forming electrode windows in semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6056286B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56114319A (en) * | 1980-02-14 | 1981-09-08 | Fujitsu Ltd | Method for forming contact hole |
| JPS6181628A (en) * | 1984-09-28 | 1986-04-25 | Nec Corp | Dry etching method |
| JPS62277746A (en) * | 1986-05-27 | 1987-12-02 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS63124418A (en) * | 1986-11-13 | 1988-05-27 | Canon Inc | Dry etching method |
-
1977
- 1977-11-08 JP JP13369277A patent/JPS6056286B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5466768A (en) | 1979-05-29 |
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