JPS6056299B2 - semiconductor container - Google Patents
semiconductor containerInfo
- Publication number
- JPS6056299B2 JPS6056299B2 JP5159676A JP5159676A JPS6056299B2 JP S6056299 B2 JPS6056299 B2 JP S6056299B2 JP 5159676 A JP5159676 A JP 5159676A JP 5159676 A JP5159676 A JP 5159676A JP S6056299 B2 JPS6056299 B2 JP S6056299B2
- Authority
- JP
- Japan
- Prior art keywords
- metallized
- container
- bonding pad
- semiconductor container
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 239000000919 ceramic Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 238000005219 brazing Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は改良された半導体容器の構造に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved semiconductor container structure.
従来セラミック等の絶縁材にメタライズして構成される
半導体容器は、第1図の部分断面斜視図に示すような構
造である。すなわちセラミック基板1は中央部に設けら
れた凹部底に半導体素子固着部となるメタライズ層2(
以下アイランド部と呼ぶ)を持ち、アイランド部2の周
辺から放射状に広がるメタライズリードを基板側面メタ
ライズ部3まで延長し、アイランド部2の周辺における
それぞれのメタライズリードの一端部を金属細線接続部
4(以下ボンディングパッド部と呼ぶ)、他端を金属リ
ード5(以−下ピンと呼ぶ)のロウ材6によるロウ付部
としたもので、この上にボンディングパット部4とアイ
ランド部2とを露出できる大きさの開口部を中央部に具
えた絶縁枠7がメタライズリード部をはさんで積層され
、絶縁枠7の開口部周縁に設けられ;たメタライズ層8
にロウ材を用いてキャップ封止する構造のものである。A semiconductor container conventionally constructed by metallizing an insulating material such as ceramic has a structure as shown in a partially sectional perspective view of FIG. That is, the ceramic substrate 1 has a metallized layer 2 (which serves as a semiconductor element fixing part) at the bottom of a recess provided in the center.
The metallized leads that spread radially from the periphery of the island part 2 are extended to the metallized part 3 on the side surface of the substrate, and one end of each metallized lead around the island part 2 is connected to a thin metal wire connection part 4 (hereinafter referred to as an island part). (hereinafter referred to as a bonding pad part), and the other end is a brazed part with a brazing material 6 of a metal lead 5 (hereinafter referred to as a pin), and is large enough to expose a bonding pad part 4 and an island part 2 on top of this part. An insulating frame 7 having an opening in the center thereof is laminated across the metallized lead part, and a metallized layer 8 is provided around the opening of the insulating frame 7.
The structure is such that the cap is sealed using brazing material.
しかしながら、この様にボンディングパッド部4がすべ
て同一平面にメタライズされている構造であると、LS
I用半導体容器のようにボンディングパッド部を100
個所以上も必要とする場合には、ボンディングパッド巾
と相隣るボンディングパッド間隔を極端に狭くしなけれ
ばならず、また容器の外形をむやみに大きくする訳にも
行かず、半導体容器の製造歩留りやボンディング作業性
を悪くする欠点があつた。本発明はこれらの問題点を解
決する為になされたもので、[Iのような多ピンリード
半導体装置に適した容器を提供することを目的とする。
本発3明の特徴は、セラミック基板の一主表面に凹部が
設けられ、この凹部の周囲に複数のボンディングパッド
部となるメタライズ層が設けられた半導体容器において
、これらの複数のメタライズ層が凹部からの高さの異な
る複数の位置に設けられている半導体容器にある。本発
明によれば、従来のボンディングパッド巾ならば2倍の
パッド数をつくることも可能であり、又同じパッド数に
するならばボンディングパッド巾を2倍にすることも可
能である。However, if the bonding pad portions 4 are all metallized on the same plane, the LS
The bonding pad part is 100mm like the semiconductor container for I.
If more than one bonding pad is required, the width of the bonding pad and the spacing between adjacent bonding pads must be extremely narrow, and the external shape of the container cannot be made unnecessarily large, which reduces the manufacturing yield of the semiconductor container. It also had the disadvantage of impairing bonding workability. The present invention was made to solve these problems, and an object of the present invention is to provide a container suitable for a multi-pin lead semiconductor device such as [I].
The third feature of the present invention is that in a semiconductor container in which a recess is provided on one main surface of a ceramic substrate and a plurality of metallized layers serving as bonding pad portions are provided around the recess, the plurality of metallized layers are formed in the recess. The semiconductor container is located at multiple positions at different heights from the semiconductor container. According to the present invention, it is possible to make double the number of pads with the conventional bonding pad width, and it is also possible to double the bonding pad width with the same number of pads.
以下本発明の実施例を図面を用いて説明する。Embodiments of the present invention will be described below with reference to the drawings.
第2図は本発明の半導体容器の一実施例の構造を示す部
分断面斜視図である。本構造を製造方法に従つて説明す
ると、まずグリーンテープよりなる第1層のセラミック
基板1aの中央部に、半導体素子を個着するアイランド
部2’をWメタライズにより印刷する。FIG. 2 is a partially sectional perspective view showing the structure of an embodiment of the semiconductor container of the present invention. To explain this structure according to the manufacturing method, first, an island portion 2' on which a semiconductor element is individually attached is printed by W metallization in the center of a first layer ceramic substrate 1a made of green tape.
次にアイランド部2’より大きな開口部9を有するO、
5wrIn厚のグリーンテープよりなる第2層のセラミ
ック基板lbに、該開口部9から周縁に向つて放射状に
Wメタライズリード10を形成する。更にグリーンテー
プよりなる第3層のセラミック基板1cは、第2層のグ
リーンテープと同口径の開口部を有し、しかも第2層の
Wメタライズリード10のボンディングバッド部が露出
するように櫛形に切に取られた溝部11が設けられ、残
つた部分から周縁に向つて放射状にWメタライズリード
1『が施されたものである。このようにメタライズされ
たグリーンテープを第1層、第2層、第3層の順に位置
合わせし、その上に開口部を持つキャップ封止用の絶縁
枠12を重ねてブレス圧着する。これを1500〜16
00℃の還元雰囲気中の炉で焼成させた後にNiメッキ
を施し、次いでピン5″を側面メタライズ部3″にAg
−Cuロウ材でロウ付けしてAuメッキを施すと、第2
図に示すような内部メタライズリード数を2倍に増加さ
せた半導体容器が得られる。本実施例による容器を用い
ると、例えば従来42ピンを必要とする容器の場合、ピ
ンのピッチ間隔が2.547m長手方向寸法52wr!
nの容器を使用していたのに対し、ピン間隔を1.27
w$tとすることによつて長手方向寸法が32T$Lの
24ピン用の容器で済ますことができる。Next, O having an opening 9 larger than the island portion 2',
W metallized leads 10 are formed radially from the opening 9 toward the periphery of the second layer ceramic substrate lb made of green tape with a thickness of 5 wrIn. Furthermore, the third layer ceramic substrate 1c made of green tape has an opening with the same diameter as the second layer green tape, and is shaped like a comb so that the bonding pad portion of the second layer W metallized lead 10 is exposed. A cut groove 11 is provided, and W metallized leads 1' are applied radially from the remaining portion toward the periphery. The thus metalized green tape is aligned in the order of the first layer, the second layer, and the third layer, and an insulating frame 12 for sealing the cap having an opening is placed thereon and press-bonded with a press. This is 1500-16
After firing in a furnace in a reducing atmosphere at 00°C, Ni plating is applied, and then the pin 5'' is plated with Ag on the side metallized portion 3''.
- When brazing with Cu brazing material and applying Au plating, the second
A semiconductor container is obtained in which the number of internal metallized leads is doubled as shown in the figure. When using the container according to this embodiment, for example, in the case of a container that conventionally requires 42 pins, the pin pitch interval is 2.547 m and the longitudinal dimension is 52 wr!
n container was used, but the pin spacing was changed to 1.27.
By using w$t, a container for 24 pins with a longitudinal dimension of 32T$L can be used.
このピン間隔1.27wLは、製造技術上からもピンの
機械的強度上からも十分実用に供される寸法である。This pin spacing of 1.27 wL is a dimension that is sufficiently practical in terms of manufacturing technology and mechanical strength of the pins.
さらに第3図は本発明の他の実施例を示す断面斜視図で
、ピンの機械的強度を増したい場合には、1.27wn
間隔のピンの相隣る2本13,13″の間に、例えば樹
脂モールド法等により絶縁物14を挾んで一体化し、こ
の一体化されたピンは2.547m間隔で42ピン用と
して使用できる。Furthermore, FIG. 3 is a cross-sectional perspective view showing another embodiment of the present invention, and when it is desired to increase the mechanical strength of the pin,
An insulator 14 is sandwiched and integrated between two adjacent pins 13 and 13'' of the interval pins by, for example, a resin molding method, and this integrated pin can be used for 42 pins at an interval of 2.547 m. .
このように本発明による容器は、多ピンリードを有する
構造であるので、今後益々発展する多電極大型化チップ
を簡潔に搭載することが可能となるものである。As described above, since the container according to the present invention has a structure having multi-pin leads, it becomes possible to easily mount large-sized multi-electrode chips that will be developed more and more in the future.
第1図は従来の半導体容器の部分断面斜視図、第2図お
よび第3図は本発明の半導体容器の実施例をそれぞれ示
す部分断面斜視図である。
第1図、第2図および第3図において、1,1a,1b
,1c・・・・・・セラミック基板、2,2″・・・・
アイランド部、3,3″・・・・側面メタライズ部、4
・・・・・・ボンディングバッド部、5,5″・・・ゼ
ン、6・・・・・・ロウ材、7・・・・・・絶縁枠、8
・・メタライズ層、9・・・・・・開口部、10,1『
・・・・Wメタライズリード、11・・・・・・溝部、
12・・・・・・絶縁枠、13,13″・・・ゼン、1
4・・・・・・絶縁物。FIG. 1 is a partially sectional perspective view of a conventional semiconductor container, and FIGS. 2 and 3 are partially sectional perspective views showing embodiments of the semiconductor container of the present invention. In Figures 1, 2 and 3, 1, 1a, 1b
, 1c...ceramic substrate, 2,2''...
Island part, 3,3″... Side metallized part, 4
...Bonding pad part, 5,5''... Zen, 6 ... Brazing material, 7 ... Insulation frame, 8
... Metallized layer, 9... Opening, 10, 1'
...W metalized lead, 11...groove,
12...Insulation frame, 13,13''...Zen, 1
4... Insulator.
Claims (1)
周辺の前記一主表面上にボンディングパッド部となるメ
タライズ層が設けられた半導体容器において、前記ボン
ディングパッド部は前記凹部底面からの高さが各々異な
る複数の面に形成されていることを特徴とする半導体容
器。1. In a semiconductor container in which a recess is provided on one main surface of a ceramic substrate and a metallized layer serving as a bonding pad is provided on the main surface around the recess, the bonding pad has a height from the bottom of the recess. A semiconductor container characterized in that it is formed on a plurality of different surfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5159676A JPS6056299B2 (en) | 1976-05-04 | 1976-05-04 | semiconductor container |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5159676A JPS6056299B2 (en) | 1976-05-04 | 1976-05-04 | semiconductor container |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52134375A JPS52134375A (en) | 1977-11-10 |
| JPS6056299B2 true JPS6056299B2 (en) | 1985-12-09 |
Family
ID=12891280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5159676A Expired JPS6056299B2 (en) | 1976-05-04 | 1976-05-04 | semiconductor container |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6056299B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02237043A (en) * | 1989-03-09 | 1990-09-19 | Mitsubishi Electric Corp | Semiconductor device |
| JPH07101723B2 (en) * | 1989-05-19 | 1995-11-01 | 三菱電機株式会社 | Semiconductor integrated circuit package |
-
1976
- 1976-05-04 JP JP5159676A patent/JPS6056299B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS52134375A (en) | 1977-11-10 |
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