JPS6057097B2 - Data transmission method between central processing units - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data transmission system between central processing units for easily performing one-to-N communication.

[Background of the invention]

Various methods have been considered for data transmission between central processing units (hereinafter referred to as CPUs) of computers.

The most suitable method for each system is selected in consideration of transmission speed, transmission distance, transmission equipment price, etc. In the transmission method of a transmission device that is relatively close and connected by wire, there are multiple CPUs communicating,
A conventional example of a so-called 1-to-N type data transmission system in which these are one upper CPU and a plurality of lower CPUs will be described below. FIG. 1 shows the basic configuration of a 1-to-N data transmission system. In Figure 1, 1 is the upper CPU, 2 is N
Lower CP consisting of CPUs 2A, 2B, ..., 2N
U group, 3 is N CPU data transmission devices 3A, 3B,
..., a data transmission device group for the upper CPU consisting of 3N,
4 is a data transmission device for N CPUs 4A, 4B, . . .
, 4N is a data transmission device group for each lower CPU, and 5 is N data transmission lines 5A that connect the respective data transmission devices.
, 5B, ..., 5N, 6 is C
N data buses 6A, 6B, . . . , 6 provided for the interface between the PU group 2 and the data transmission device group 4
A data bus group 7 is composed of N data buses 7A, 7B, . . . , 7N provided for an interface between the CPUI and the data transmission device group 3. As shown in Figure 1, the upper CPU and lower CPU
U is radially coupled around the host CPU by each pair of transmission devices. This example has no contention between the CPUs of each transmission path, and is the most basic configuration. However, as is obvious from the figure, this method requires N pairs of data transmission devices and has the disadvantage of being expensive. FIG. 2 shows a possible configuration to compensate for the drawbacks of FIG. 1.

In the second part, 30 is a data device for the upper CPU, 40 is a data transmission device for the lower CPU, 50 is a transmission line between the data transmission devices, and 70 is the data transmission device 30 for the higher CPU1.
9 is a shared data bus for the lower CPU, and 10 is a shared data bus switching control device. In this example, the lower CPUs are connected through a shared data bus 9, one data transmission device 40 is installed on the data bus 9, and the shared data bus is switched between the lower CPUs to share the transmission device. The goal is to be achieved with a pair of data transmission devices. The principle of shared data bus switching control at this time is shown in FIG. Lower CPU2A, 2B
,...,2N are data transmission devices 40 shared by each
When you want to use the shared data bus, you issue a switching request 81 to the shared data bus switching control device 8 and connect the shared data bus 9 to your own CPU bus. That is, C.P.
When U issues a switching request to the shared data bus control device, the switching request signal 81 is received by the switching control circuit 80, which switches the connection of the shared data bus 9 to the CPU that requested it. Switching control at this time is performed by a switch 83 that is switched in accordance with a switching control number 82 outputted from a switching control circuit 80. In the above configuration, the lower data transmission device is used alternately by the lower CPU, and the transmission speed appears to be slower at first glance, but even in the configuration shown in Figure 1, the upper CPU is used by one lower CPU. It communicates with the other party and operates serially, so at first glance it looks like the communication is being done in parallel, but the system configuration is actually serial after all, so there is not much difference.

However, the configuration shown in FIG. 1 has the advantage that when a transmission device is of a low-speed type, it is possible to carry out so-called simultaneous processing in which communication is executed by another transmission device during the transmission interval. Now, in the example shown in FIG. 2, the cost is reduced by reducing the number of transmission devices, but the following practical problems arise.

That is, the upper CPU cannot determine which lower CPU the lower shared data transmission device is connected to, and cannot actively select the CPU with which it wants to communicate. It is possible to communicate only with lower CPUs connected to the shared data bus. On the other hand, competition between shared data transmission devices also occurs on the lower CPU side, and it is difficult to control this without adding more complicated hardware and software. Furthermore, when data transmission starts and an error occurs, it is difficult to determine whether the failure is in the data transmission device or in the other CPU. [Object of the Invention] An object of the present invention is to eliminate the drawbacks of the above-mentioned prior art, and specifically to provide a data transmission system between central processing units that enables data transmission with a simple configuration.

[Summary of the invention]

The present invention is characterized in that the bus switching control system and the data transmission system are constructed separately.

Here, a process input device (hereinafter referred to as PIO) to which the best embodiment of the present invention is applied will be described.

FIG. 4 shows the basic configuration of PIO.

As its name suggests, PIO24 is mainly used in a control computer to control and monitor process 2.
Changes in analog quantities and digital quantities in 9 are CP.
In order to import into U2l or output analog and digital amounts from CPU2l to process 29,
There is a device that relays information exchange between the PU 2l and the process 29. The PIO 24 has a plurality of information exchange terminals closest to the process for information exchange. These are analog input terminal 25 and digital input terminal 2, respectively.
7, analog output terminal 26, and digital output terminal 28. The CPU 2l transmits control signals to the PIO control device 22 located between these input/output terminals, operates these input/output terminals, and exchanges information. That is, when inputting information, the PIO control device 22 is designated with an input point number indicating whether it is an analog input or a digital input, and which one of the plurality of human-powered terminals is available. The designated number analog input 30 or digital input 32 is signal-shaped at the input terminal and exchanged with predetermined digital information, and then sent to the PIO data bus 23 and the PI0 control device 22.
The data is taken into the CPU via the CPU and stored in the main memory. For output, the reverse is true, and the contents of the main memory are sent via the PIO control device 22 to the output terminal of the designated number, and output from the output terminal to the process 29 as an analog output 31 or digital output 33. Here, the process 29 has a broad meaning, and process input/output refers to electrical signals and mechanical signals of various industries. Therefore,
As long as it has the function of taking in these electrical signals and mechanical signals to the CPU 2l, it does not need to be called PIO. Similarly, even if the other party is not a plant but, for example, a computer, if it is possible to exchange analog or digital information with that computer, the other party's computer will be different from the perspective of this CPU. is a process in a broad sense. [Embodiments of the Invention] Examples of the present invention will be described based on the above premises.

FIG. 5 is a diagram showing an embodiment of the present invention. In the figure, 11 is a PIO attached to the host CPU, which has digital output (hereinafter referred to as DO) and interrupt input (hereinafter referred to as 1N).
T) for the number of lower CPUs. 13 is PIO l3A, l3B,..., 13 attached to the lower CPU
A PIO group consisting of N, also DO. 1 each of l5lNT
I have one.

Generally, PIO is essential for control computer systems. These are attached to the CPU, and the number of points needed here is left over as spares or fractions. Therefore, there is no need to spend extra money to add it, and even if it is necessary, it is extremely inexpensive and there is no need to worry about price increases. 12 is a signal line 1 that connects the upper and lower PIOs.
In the signal line group consisting of 2A, 12B, . . . , 12N, the upper DO is connected to the lower INT, and the lower DO is connected to the upper INT by a pair of electric wires.

6 and 7 are flowcharts supplementing FIG. 5 and showing the operation thereof.

The data transmission system of the present invention will be described below with reference to FIGS. 6 and 7. The upper CPUl in FIG. 5 is the lower C
When transmitting zeta to PU group 2, first the upper PIO
The DO connected to the lower PIO group 13 of ll is turned on.

As a result, a specific PIO in the lower circle 0 group 13 has an IN
A signal is input to T, and the programs of the lower CPUs (hereinafter referred to as CPU2A and PIO13A) operate to switch the connection of the shared data bus to themselves, and connect the lower data transmission device 40 to themselves. When that is finished, lower C
PU2A turns on lower PIOl3A(:7)DO to report completion of connection switching. This DO enters the INT of the upper PIOll, and the program of the upper CPUl runs.
The data is then transmitted to the lower-level data transmission device 40 via the higher-level data transmission device 30 and stored in the storage device of the lower-level CPU 2A. When the upper CPU1 completes data transmission with the lower CPU 2A, it continues to transmit data to other lower CPUs such as C
Data is transmitted to and from the PU 2B in a similar manner, and the lower CPU 2B similarly receives and stores the transmitted data in the storage device. This process is repeated for the lower CPUs to complete a series of data transmissions. In the above example, the direction of data transmission was described as being from the upper level to the lower level, but once the shared data bus is switched, the data transmission device is one upper CPU and one lower CPU, so As long as the procedures are mutually determined and communication is carried out between them, it is possible to send data to either the upper or lower sides. In addition, since real data transmission can be started after the operating state of the other party's CPU is determined by an answer back, an error that occurs during real data transmission is clearly regarded as a failure of the data transmission device. Therefore, it becomes easy to handle errors such as errors. In the above embodiments, an input/output device may be used instead of yen 0.

〔Effect of the invention〕

According to the present invention, in a polling type 1-to-N type data transmission system, a transmission system that can perform inexpensive and efficient data transmission with a minimum mechanical configuration can be obtained.

[Brief explanation of the drawing]

Fig. 1 shows the basic configuration of a conventional 1-to-N data transmission system, Fig. 2 shows another conventional example, and Fig. 3 shows an example of the configuration of a shared data bus switching controller. , FIG. 4 is a diagram showing the configuration of a general PIO, FIG. 5 is a diagram showing an embodiment of the present invention, FIG. 6 is a processing flowchart thereof, and FIG. 7 is a flowchart of processing from a timing perspective. 1... Upper CPU12A, 2B,..., 2N...
Lower CPU1ll, l3A, l3B,...13N...
... PIOl3O ... Upper data transmission device, 4
0: Lower data transmission device.

Claims (1)

[Claims] 1. In a method of transmitting data between one upper central processing unit and a plurality of lower central processing units by a shared data transmission system, the upper central processing unit and the plurality of lower central processing units It is equipped with an input/output switching control system that controls which of the above central processing units transmits data, and when a transmission/reception request between a higher-level central processing unit and one of the lower-level central processing units matches through communication using this input/output switching control system, the above-mentioned A data transmission method between central processing units that is characterized by connecting a shared data transmission system between them and transmitting data.