JPS6057613B2 - integral circuit - Google Patents
integral circuitInfo
- Publication number
- JPS6057613B2 JPS6057613B2 JP5294279A JP5294279A JPS6057613B2 JP S6057613 B2 JPS6057613 B2 JP S6057613B2 JP 5294279 A JP5294279 A JP 5294279A JP 5294279 A JP5294279 A JP 5294279A JP S6057613 B2 JPS6057613 B2 JP S6057613B2
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- output
- switch
- circuit
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Amplifiers (AREA)
- Analogue/Digital Conversion (AREA)
- Feedback Control In General (AREA)
Description
【発明の詳細な説明】 本発明は入出力特性を改善した積分回路に関する。[Detailed description of the invention] The present invention relates to an integrating circuit with improved input/output characteristics.
従来の積分回路を第1図に示す。 A conventional integrating circuit is shown in FIG.
1は入力端子、2は積分開始のためのスイッチ、3は積
分値リセットのためのスイッチ、4は反転増幅器、5は
出力端子、R、は積分用抵抗器、R。1 is an input terminal, 2 is a switch for starting integration, 3 is a switch for resetting the integral value, 4 is an inverting amplifier, 5 is an output terminal, R is an integrating resistor, and R is an integrating resistor.
はリセット用抵抗器、Clはコンデンサである。この場
合スイッチ2及び3を半導体アナログスイッチ(例えば
トランジスタ)に置換するとその電源電圧によつて積分
出力は制限を受ける。そのためその半導体アナログスイ
ッチの電源電圧士VCc1よりも大きな積分出力電圧を
得たい場合には第2図の如き回路構成を要する。即ち6
は入力端子、7は半導体アナログスイッチで8は積分用
、9はリセット用であり、10は反転増幅器、11は同
相増幅器、12は出力端子、R3は積分用抵抗器、R、
はリセット用抵抗器、C2は積分用コンデンサである。
そして半導体アナログスイッチ7及び反転増幅器10に
は士Vcclを、一方同相増幅器11には士VcC2を
電源として印加する。±VCC2は所望の出力電圧を得
るためVCCIより高く取つてあり、同相増幅器11の
電圧利得は、Vcc2/Vclより大きく取ることによ
つて、この同相増幅器11の方が反転増幅器10よりも
早くクリップ(飽和)する様にしておく。この様な構成
にすると、出力12が士Vcc2A)、内で所望の出力
値になつた時でも、反転増幅器10の出力は依然として
±VcCl以内なので、半導体アナログスイッチ7が異
常な動作をすることはない。もし第1図の構成のままで
スイッチ2、3をアナログ化しただけでは反転増幅器4
の電源電圧を上げると、スイッチ3に高い電圧が印加さ
れて異常な動作をする。 従つて半導体アナログスイッ
チを用いた積分回路で、その半導体アナログスイッチの
電源電圧に制限があつて、しかもその電源電圧よりも高
い積分出力を得ようとする場合には、第2図の様に増幅
器11を追加せざるを得ない。 本発明はこの様な増幅
器を追加することなく簡単な回路で構成し、しかも誤動
作を生じない前記の目的を良好に達成する積分回路の提
供にある。is a reset resistor, and Cl is a capacitor. In this case, if switches 2 and 3 are replaced with semiconductor analog switches (for example, transistors), the integral output will be limited by the power supply voltage. Therefore, if it is desired to obtain an integrated output voltage greater than the power supply voltage value VCc1 of the semiconductor analog switch, a circuit configuration as shown in FIG. 2 is required. That is 6
is an input terminal, 7 is a semiconductor analog switch, 8 is for integration, 9 is for reset, 10 is an inverting amplifier, 11 is a common mode amplifier, 12 is an output terminal, R3 is an integrating resistor, R,
is a reset resistor, and C2 is an integrating capacitor.
Then, Vccl is applied to the semiconductor analog switch 7 and the inverting amplifier 10, and VcC2 is applied to the in-phase amplifier 11 as a power supply. ±VCC2 is set higher than VCCI in order to obtain the desired output voltage, and the voltage gain of the common-mode amplifier 11 is set larger than Vcc2/Vcl, so that the common-mode amplifier 11 clips faster than the inverting amplifier 10. (saturation). With this configuration, even when the output 12 reaches the desired output value within +Vcc2A), the output of the inverting amplifier 10 is still within ±VcCl, so the semiconductor analog switch 7 will not operate abnormally. do not have. If we keep the configuration shown in Figure 1 and simply convert switches 2 and 3 to analog, the inverting amplifier 4
When the power supply voltage is increased, a high voltage is applied to the switch 3, causing abnormal operation. Therefore, in an integrating circuit using a semiconductor analog switch, if the power supply voltage of the semiconductor analog switch is limited and you want to obtain an integrated output higher than the power supply voltage, an amplifier is used as shown in Figure 2. I have no choice but to add 11. The object of the present invention is to provide an integrating circuit which can be constructed from a simple circuit without adding such an amplifier, and which satisfactorily achieves the above object without causing malfunction.
即ち反転増幅器等の増幅器の出力端子から、コンデンサ
等のインピーダンスを通して反転入力端子・へ帰還する
積分回路において、その増幅器の出力を抵抗等で分割し
て反転入力端子へ帰還するとともにホールド時はその帰
還を阻止する、リセット回路を設けたものである。第3
図は本発明による回路例である。In other words, in an integrating circuit that feeds back from the output terminal of an amplifier such as an inverting amplifier to the inverting input terminal through an impedance such as a capacitor, the output of the amplifier is divided by a resistor and fed back to the inverting input terminal, and when holding, the feedback is A reset circuit is provided to prevent this. Third
The figure shows an example of a circuit according to the invention.
13は被積分信号を積分回路に入力するための端子、1
4は積分開始用のスイッチ、15は積分値をリセットす
るためのスイッチ、16は開始スイッチ14及びリセッ
トスイッチ15が半導体アナログスイッチで構成されて
いることを示す。13 is a terminal for inputting the signal to be integrated into the integrating circuit;
Reference numeral 4 indicates a switch for starting integration, 15 indicates a switch for resetting the integral value, and 16 indicates that the start switch 14 and the reset switch 15 are constituted by semiconductor analog switches.
17は反転増幅器、18は出力端子である。17 is an inverting amplifier, and 18 is an output terminal.
R5は積分用抵抗器、R6及R7はリセット用埠抗器、
C3は増幅器17の出力を反転入力に帰還する積分用コ
ンデンサである。反転増幅器17に印加する電源電圧士
VCC2は出力18に所望の出力電圧を得るために、十
分大きく取る。R5 is an integrating resistor, R6 and R7 are reset resistors,
C3 is an integrating capacitor that feeds back the output of the amplifier 17 to the inverting input. The power supply voltage VCC2 applied to the inverting amplifier 17 is set to be sufficiently large in order to obtain the desired output voltage at the output 18.
リセット用の信号は抵抗R6及びR,によつて分割して
増幅器の反転入力端子に帰還される。この様に分割して
帰還してもリセットの目的は十分達成される。しかも十
分大なる積分出力が増幅器から出力されても分割される
のでアナログスイッチの電源電圧が低くても異常動作を
生じな−い。ここでR6及びR7の分割比を、
になる様に選んでおくと最適な動作をする。The reset signal is divided by resistors R6 and R and fed back to the inverting input terminal of the amplifier. Even if the signal is divided and returned in this way, the purpose of resetting is sufficiently achieved. Moreover, even if a sufficiently large integrated output is output from the amplifier, it is divided, so that even if the power supply voltage of the analog switch is low, no abnormal operation will occur. If the division ratio of R6 and R7 is selected here, optimal operation will be achieved.
この様に構成した積分回路は、出力端子18における出
力電圧が、最大VCC2にまでなつたとしても、抵植只
。及びR7の分割点にはVCCl以下の電圧しか帰還さ
れないから、半導体アナログスイッチ16が異常動作を
することもない。この回路実施例において素子の定数例
として、±■Cc=±12V,±■CC2=±24V,
R6=4.7K,R7=3.9K,R5=100KΩ,
C3=4.7μFを用いると極めて良好な結果を得た。The integrator circuit configured in this way will only fail even if the output voltage at the output terminal 18 reaches the maximum VCC2. Since only a voltage lower than VCCl is fed back to the division point of R7 and R7, the semiconductor analog switch 16 will not operate abnormally. In this circuit example, as examples of element constants, ±■Cc=±12V, ±■CC2=±24V,
R6=4.7K, R7=3.9K, R5=100KΩ,
Very good results were obtained using C3=4.7 μF.
以上のように本発明は積分回路の出力を分割して積分値
リセットのための帰還させるのでリセットスイッチを半
導体アナログスイッチで構成しても、そのアナログスイ
ッチの電源電圧以上の積分出力を得ることができる。As described above, in the present invention, the output of the integrating circuit is divided and fed back for resetting the integral value, so even if the reset switch is configured with a semiconductor analog switch, it is not possible to obtain an integral output higher than the power supply voltage of the analog switch. can.
第1,2図は従来の積分回路図、第3図は本発明による
積分回路図であり、図中、17は増幅器、R5,C3は
積分素子、15はリセットスイッチ、R6,R7はリセ
ット用分割抵抗である。Figures 1 and 2 are conventional integration circuit diagrams, and Figure 3 is an integration circuit diagram according to the present invention. In the figure, 17 is an amplifier, R5 and C3 are integral elements, 15 is a reset switch, and R6 and R7 are for reset. It is a split resistance.
Claims (1)
力を反転入力に帰還して構成する積分回路において、更
にその増幅器の出力の分割出力をその増幅器の反転入力
に帰還するとともに、ホールド時はその帰還を阻止する
リセット回路を設けたことを特徴とする積分回路。1 In an integrating circuit configured by feeding back the output of an amplifier to the inverting input via an impedance such as a capacitor, the divided output of the amplifier's output is fed back to the inverting input of the amplifier, and the feedback is blocked during hold. An integrating circuit characterized by being provided with a reset circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5294279A JPS6057613B2 (en) | 1979-04-28 | 1979-04-28 | integral circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5294279A JPS6057613B2 (en) | 1979-04-28 | 1979-04-28 | integral circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55146568A JPS55146568A (en) | 1980-11-14 |
| JPS6057613B2 true JPS6057613B2 (en) | 1985-12-16 |
Family
ID=12928915
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5294279A Expired JPS6057613B2 (en) | 1979-04-28 | 1979-04-28 | integral circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6057613B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57109089A (en) * | 1980-12-26 | 1982-07-07 | Nec Corp | Initial value resetting circuit for operational amplifier |
-
1979
- 1979-04-28 JP JP5294279A patent/JPS6057613B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55146568A (en) | 1980-11-14 |
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