JPS6057709B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is based on PL (Integrated Injection).
The present invention relates to a semiconductor integrated circuit device in which memory cells of nLf)giC) configuration are arranged in an array.

The memory cell with the I″L configuration has, for example, the circuit configuration shown in FIG. 1, in which Q1 to Q6 are transistors, W1,
W2 is a word line, B1 and B2 are bit lines, and Qh is a transistor connected to the word line W2 for supplying a holding current Ih.

A schematic cross-sectional view of such a memory cell is shown in FIG. 2 with the same reference numerals, and the p-type region to which the word line W1 is connected is the common emitter of the lateral pnp transistors Q1 and Q2, and These transistors Q1, Q
2 constitutes an injector. Further, the npn transistors Q3 and Q4 operate with an n-type region normally used as a collector as an emitter, and an n-type region normally used as an emitter as a collector. Such memory cells are arranged in an array, and a transistor Qh for supplying a holding current is connected to a common word line W2, and the word line W2 is usually a buried layer doped with n-type impurities at a high concentration. Since it has an n-n configuration by epitaxially growing an n-type semiconductor layer with a lower impurity concentration on top of it, it has a considerable resistance due to back resistance compared to metal wiring. will exist.

The resistance of the word line W2 as described above causes problems of (a) non-uniform holding current and (b) increase in the write threshold current of the memory cell at the end of the array.

In order to solve this problem, it has previously been proposed to distribute holding current supply transistors and dummy cells in an array of memory cells. However, since an extra transistor and dummy cell are provided for supplying a holding current, there is a drawback that the degree of integration is reduced. The present invention
This is an improvement over the conventional drawbacks mentioned above, and aims to equalize the holding current of each memory cell, prevent an increase in the write threshold current, and prevent a decrease in the degree of integration. 'be.

Examples will be described in detail below. FIG. 3 shows an equivalent circuit of the embodiment of the present invention, CEL1 to CELn are memory cells represented by equivalent diodes of the memory cells shown in FIG. 1, BPa and BPb are shunt circuits, and ■, a, and HLb are holding circuits. , Qha, Qhb are transistors for supplying a holding current, and Rh is a resistance formed by a semiconductor layer corresponding to the word line W2 in FIGS. 1 and 2. Since the holding circuits HLa and HLb are arranged at both ends of the array, each memory cell CEL is
It is possible to equalize the holding currents flowing through CEL1 to CELn.

Further, by providing the shunt circuits BPa and BPb, the write current 1w when writing is performed by selecting, for example, the memory cell CEL1 at the end of the array, is shunted to the adjacent unselected memory cell CEL2 and the shunt circuit BPa. The current state is almost the same as when writing is performed by selecting a memory cell at another location, and an increase in the write threshold current can be prevented. The shunt circuits BPa, BPb have the injector of the memory cell shown in FIG. 1 as a basic component, and either one of transistors Q3, Q4 constituting a flip-flop can also be added as a component.

FIG. 4 is a conceptual diagram of a pattern of an embodiment of the present invention, where IS is an isolation region, BPb is a shunt circuit, HLb is a holding circuit, DCb is a dummy cell, W1 is a word line, CELn,
CEL (n-1) is a memory cell, p1 is a p-type region that constitutes the common emitter of transistors Ql and Q2 (see Figure 1) of the memory cell, and Nl, n2 are transistors Ql and Q.
n-type regions of the semiconductor layer constituting the base of 2, P2, p3
are the collectors of transistors Ql and Q2 and the transistor Q
3, p-type region as base of Q4, Q5, Q6, N3
is the -n type region as the collector of transistor Q4, N
4 is an n-type region as the emitter of transistor Q6, N
5 is an n-type region as the collector of transistor Q3, N
6 is an n-type region as the emitter of transistor Q5. Also, the shunt circuit BPb (7) PdO is a p-type region and the word line W! 1 and serves as a common emitter for the transistors of the injector, and corresponds to the p-type region p1 in the memory cell.

Further, the holding circuit HL,b(1)Eh is an n-type region as an emitter of the transistor Qhb, and Bh is a p-type region as a base. The shunt circuits BPa and BPb are connected to one injector and the holding circuit HL. a, HLb are each formed by one transistor, so that the shunt circuit BPa and the holding circuit Hl. a, shunt circuit BPb and holding circuit HLb
The area of dummy cell DCb consisting of It is possible to equalize the holding current, prevent an increase in the write threshold current due to the shunt circuit, and reduce the degree of integration to a very small degree.

FIG. 5 is a conceptual diagram of a pattern of another embodiment of the present invention, in which the same reference numerals as in FIG. 4 indicate the same parts, and the shunt circuit BPb
are transistors Ql and Q2 connected to word line W1
(see Figure 1) p-type region corresponding to the emitter d1
, an n-type region Ndl, nd2 corresponding to the base, a p-type region Pd2 corresponding to the collector of the transistor Q1 and the base of the transistor Q4, a p-type region Pd corresponding to the collector of the transistor Q2 and the base of the transistor Q3.
3 and an n-type region Nd3 corresponding to the collector of the transistor Q3.

In this embodiment as well, the shunt circuit BPa and the holding circuit HL
Since the area of the dummy cell DCb consisting of the shunt circuit BPb, the shunt circuit BPb, and the holding circuit HLb is smaller than the area of each memory cell, its influence on the degree of integration is small.

As explained above, the present invention provides a semiconductor integrated circuit device in which memory cells of I2L configuration are arranged in an array.
By distributing the holding circuits, it is possible to equalize the holding current of the memory cells, and by providing a shunt circuit, the write current is divided to prevent the write threshold current from increasing. can do.

Furthermore, since the shunt circuit can require approximately half the area of the memory cell, it has the advantage that it can be disposed in combination with the holding circuit, thereby minimizing a decrease in the degree of integration.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a memory cell with a PL configuration, and Figure 2 is a circuit diagram of a memory cell with a PL configuration.
3 is an equivalent circuit diagram of an embodiment of the present invention, and FIGS. 4 and 5 are conceptual diagrams of main part patterns of different embodiments of the present invention. be. BPa and BPb are shunt circuits, Hl. a and HLb are holding circuits, DCb is a dummy cell, CELl to CELn are memory cells, Wl and W2 are word lines, Bl and B2 are bit lines,
Q1 to Q6 are transistors, and Qh, Qha, and Qhb are holding current supply transistors.

Claims (1)

[Claims] 1 In a semiconductor integrated circuit device in which memory cells of an I^2L configuration are arranged in an array, a shunt circuit that shunts a write current of the memory cell and a holding circuit that supplies a holding current of the memory cell are incorporated. A semiconductor integrated circuit device characterized by having dummy cells arranged in a distributed manner.