JPS6057735B2 - Analog to digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital converter, and particularly to one that compensates for conversion errors due to drift.

A conventional analog-to-digital converter is shown in FIG.

That is, 1 is an operational amplifier, 2 is a resistor with a resistance value R, and 3
is a capacitor having a capacitance value C, and these constitute an integrator. The resistor 2 is supplied with an input voltage (E, >0) via the first switch 4, and is supplied with a reference voltage E0 (E, >0) via the second switch 5. 6 is a comparator which sets the reference level of the integrator output.

This integrator operates as follows.

When the output of the operational amplifier 1 is at the reference level, the first switch 4 is closed and the second switch 5 is opened. Then, the input voltage is supplied to the operational amplifier 1, and the output increases as shown by the solid line in FIG. This state continues for a preset time Tl. After Ti has elapsed, the first switch 4 is opened and the second switch 5 is closed. Then the reference voltage E. is supplied, and the output decreases as shown by the solid line in FIG. The time it takes for this output to reach the reference level is defined as T2. From the above operations, the following equation is established. If -0=Tl,t, -t1=T2, then.

Therefore, T2 becomes.

Since E2 and El are constant, T2 is proportional to the absolute value E1 of the input voltage. Therefore, if the clock pulse generator is operated only during T2, the number of generated pulses is
It is proportional to the absolute value E1 of the input voltage, making analog-to-digital conversion possible. However, in reality, an offset voltage is generated in the operational amplifier 1 due to drift, and if we assume that its magnitude is 1 Δe (Δe>0), the integral waveform that takes this drift into consideration is shown in Figure 2. The result is as shown by the dotted line, and the following formula holds true.

~-11iShino 1- ~νZi(No Crystal Zll', T2'' becomes, and if a drift occurs, an error will occur in analog-to-digital conversion.

An object of the present invention is to provide an analog to digital converter that compensates for errors in analog to digital conversion due to the above-mentioned drift.

This invention will be explained below based on two embodiments shown in FIGS. 3 to 6. The first embodiment has a configuration as shown in FIG. That is, 10 is an operational amplifier, the inverting input terminal of which is connected to a contact of a first switch 14 via a resistor 12 having a resistance value r1. The first switch 14 is a changeover switch, and one terminal thereof is supplied with an input voltage of 1 (E3>0), and the other terminal is grounded. The inverting input terminal of the operational amplifier 10 is further connected to a bias voltage via a resistor 16 having a resistance value R2.
(E3>0) is supplied. On the non-inverting input terminal side,
It is connected to the output terminal side via a resistor 18 having a resistance value R3. In this way, the adder 19 is configured. 20 is an operational amplifier, the inverting input terminal side and the output terminal side of which are connected via a capacitor 22 having a capacitance value C.

Further, the non-inverting input terminal side is grounded. One end of a resistor 24 having a resistance value R is connected to the inverting input terminal side. In this way, the integrator 25 is configured. The other end of the resistor 24 is connected to the output side of the operational amplifier 10 via a second switch 26 . Further, the reference voltage E2 (>0) is supplied to the other end of the resistor 24 via the third switch 28. Furthermore, it is grounded via a fourth switch 30. Analog switches such as relays, transistors, and MOSICs are used as the first to fourth switches. Reference numeral 32 denotes a controller that controls the opening and closing of the first to fourth switches as will be described later, and also operates and stops a counter 36 that will be described later.

34 is a clock pulse generator that generates pulses with a constant frequency.

A counter 36 counts the pulses generated by the clock pulse generator 34.

Reference numerals 38 and 40 are memory devices for storing the count value of the counter 36.

42 is a subtracter that calculates the difference between the value stored in the storage device 38 and the value stored in the storage device 40.

Next, the operation of this analog to digital converter will be explained with reference to FIG.

Now, the clock pulse generator 34 is in operation and the counter 3
6 is in an inactive state. When the output of the operational amplifier 20 is at a point a below a preset reference level,
The first switch 14 is switched to the upper 1 side, the second switch 26 is switched to the closed state, and the third switch 28 and the fourth switch are switched to the upper side.
The controller 32 opens the switch 30. Since the operational amplifier 20 is supplied with a voltage lower than the reference level from the operational amplifier 10, the output voltage is integrated and begins to rise. Then, the controller 32 causes the first to fourth switches to take the above-mentioned states until a predetermined time period elapses from the point b at which the reference level is exceeded. Immediately after the point c when the period ζ has elapsed, the first switch 14 is switched to the ground side, and the second switch 14 is switched to the ground side.
switch 26 is in the open state, the third switch 28 is in the closed state, the fourth switch 30 is in the open state, and the counter 3 is in the open state.
6 is activated by the controller 32. Then, a voltage of E2 (>0) is supplied to the operational amplifier 20, and an integral waveform in the opposite direction to the period appears at the output of the operational amplifier 20. The moment when this output waveform crosses the reference level is defined as point d. At point d, the controller 32 stops the counter 36 and the count value of the counter 36 is transferred to the memory 38. Let us call the period from point c to point d. The first to fourth switches remain in state 1 until a certain period of time passes from point d, or until the output of the operational amplifier 20 drops by the voltage equal to the reference voltage, and the output of the operational amplifier 20 remains in state 1. Immediately after point e reaches these states, the first switch 14 is switched to the ground side, the third switch 28 and fourth switch 30 are opened, and the second switch 26 is closed. The controller 32 then performs the following steps.

At this time, 1? to the J operational amplifier 20? E3 is supplied,
Its output gradually increases and eventually crosses the reference level.
Let that point be f, and from point f to point g after a period of time has elapsed,
The first to fourth switches maintain the state. Immediately after the fourth point g, during a period T3 to be described later, the first switch 14 is kept switched to the ground side, the second switch 26 and the third switch 28 are opened, and the fourth switch 30 is switched to the ground side. The controller 32 is in the closed state. During this time, only the offset of the operational amplifier 20 is integrated and appears in the output. The point at which the change has passed is h, and immediately after point h, the first switch 14
is switched to the ground side, and the second switch 26 and the fourth
The controller 32 places the switch 30 in an open state, the third switch 28 in a closed state, and the counter 36 in an operating state.

At this time, the reference voltage A2 is input to the operational amplifier 20,
The output of the operational amplifier 20 begins to fall and eventually crosses the reference level, which is defined as point 1. At point 1, the controller 32 stops the counter 36 and stores the count value in the memory 4.
Move to 0. Let ζ be the time from point h to point 1. When the count values of the counter 36 are stored in the storage devices 38 and 40, the subtractor 42 calculates the difference between these two values. This calculated value is obtained by digitizing 1 on the input voltage by removing the influence of drift. Note that via the operational amplifier 10,
When upper 1 and upper 3 are applied to operational amplifier 20, an offset voltage is added to them, the magnitude of which is
3l, and the slope direction of the integral waveform shown in FIG. 4 is not changed. Next, the reason why analog-to-digital conversion can be performed as described above will be explained.

Now, set the offset voltage of the operational amplifier 10 to -Δe1(Δe
1>0), and set the offset voltage of the operational amplifier 20 to -Δe(
Δe>0). The following equation holds true from point e to point d. Here, if cmb=chi and d-C=T2, the following equation holds true from point f to point 1.

Here, if g−f=chi, h−g=T3, and i−h=ζ, we obtain (7)−(9). When a person does this, it becomes .

Also, from equation (9), ζ is E2 is the number V1ΔEl, and Δe is 1
Since the voltage is around 0rr1■, equation (13) is
It becomes R3E3.

In equation (14), move 1( to the left side, and both sides
Multiplying R2E2 by one Δe gives the following equation.

? If E3 is chosen so that -Δe・(h above Jt
l1 R2E2ζ)
is sufficiently small compared to (T2-T4)E2, so it can be ignored.

Therefore, since equation (12) holds true, the period h<
5t, by operating the clock pulse generator and finding the difference in the number of pulses, it is possible to digitize the input voltage E1 without being affected by the offset voltage.

Further, even if these offset voltages drift, they are not affected by the drift. The above content will be explained using a specific example.

now,? =1,? =1, E3=0.5V, E2=5V, E
1=5V, and the offset voltages of the operational amplifiers 10 and 20 are Δe1=10mv and Δe=10rnV, respectively. The period is counted by clock pulses having a constant frequency, and t1 is set as 50,000 (issues). if,
If there is no drift, T2 will be obtained from equation (3).

This is derived by substituting the above values.

That is, an input voltage of 5 cm is represented by 50,000 pulses. However, if each of the operational amplifiers 10 and 20 drifts due to temperature changes or the like and the above offset voltage is generated, the error will be 301 compared to the true value of 50,000.

According to this device, (5+0.5+0.0
1+0.01)×50000=(5-0.01)T2(
From formula 9), we can find the following, and according to this device, the voltage of 5V can be changed to 50,000
When expressed in terms of the number of pulses generated, even if a drift of about 10r]1■ occurs, it is treated as an error and does not affect the result.

In the above-mentioned embodiment, since analog-to-digital conversion is performed with a certain limit, the influence of drift cannot be completely removed.

However, as shown in Figure 4! If and T3+T4 can be made completely equal, the influence of drift can theoretically be completely eliminated. That is, by substituting T2=T, +T4 into equation (9), we get, and from (7)-(28), we get L1.

Therefore, the influence of drift can be completely removed. Figure 5 Harato T3+! We will show you how to bring the relationship closer to an ideal state. In Fig. 5, the portion corresponding to that in Fig. 4 is Tx
O, TXl, TO2..., the part corresponding to T
yO. ．． It is expressed as tylty2... It is assumed that FIG. 5a shows the first integral operation immediately after the power is turned on. At this point, there is no information on Ty to determine TxO, so TxO is , -. (XV-ゞZV--
- and activate this device.

Then, TyO is determined. FIG. 5b shows an integral waveform when TXl is activated.

Tyl is determined based on this operation result. Figure 5c
is an integral waveform when TX2 is operated as follows.

Similarly, if we repeat this operation, that is, determine T3 for the next carryover using T obtained from the previous integration result, as long as 1 does not change in the input signal, , T2-T4 approach ideal values, and analog/digital conversion can be performed with the influence of drift removed. FIG. 6 shows a second embodiment in which a buffer amplifier 44 and a reference voltage amplifier 46 are added to the first embodiment, and a fifth switch 4 is inserted between the buffer amplifier 44 and the reference voltage amplifier 46.
8.

In this device, during the period from point g to point h in FIG. 4, the fifth switch 48 and the fourth switch 30 are closed, and the third
switch 28 is opened. From point c to point e1 point h
During the period from point 1 to point 1, if the fifth switch 48 and the fourth switch 30 are opened and the third switch 28 is closed, the drift of the buffer amplifier 44 and the reference voltage amplifier 46 can also be reduced It can be compensated by including it in the drift of 20. Furthermore, even if only the buffer amplifier 44 is installed between the second to fourth switches in FIG. 3 and the resistor 24, its drift can be included in the drift of the operational amplifier 20 and compensated for.

[Brief explanation of drawings]

) FIG. 1 is a schematic configuration diagram of a conventional analog-to-digital converter, FIG. 2 is an integral waveform diagram thereof, and FIG. 3 is a schematic configuration diagram of a first embodiment of an analog-to-digital converter according to the present invention. Figure 4 is an integral waveform diagram of the integrator, Figures 5 a to c
6 is an integral waveform diagram of the integrator in step 5 for determining the period T3, and FIG. 6 is a schematic configuration diagram of the second embodiment. 14...First switch, 19...Adder, 25...Integrator, 26...Second
Switch, 28...Third switch, 30...
...Fourth switch, 302...Controller,
36... Counter, 34... Clock pulse generator.

Claims (1)

[Claims] 1 The bias voltage whose absolute value is E_3 is the resistance value r_2
an adder to which an input voltage having the same polarity as the bias voltage is input via a first switch, and an output from the adder is input via a second switch. A reference voltage whose polarity is opposite to the input voltage and whose absolute value is E_2 is input through the third switch, and the fourth
an integrator grounded through a switch, a clock pulse generator that generates clock pulses with a constant period, and a counter that counts the pulses of the clock pulse generator.
a controller that controls the counting operation of the clock pulses in the first to fourth switches and the counter; and a subtracter that calculates the difference between the count values in the first and second counting operations of the counter. , the controller maintains the state in which the first and second switches are closed and the third and fourth switches are opened for a first set time t_1 from the time when the output of the integrator is at the reference value, and then With the third switch closed and the first, second, and fourth switches open, the counter is caused to perform the first counting operation for a time t_2 until the output of the integrator returns to the reference value, and the From the point when the output of the integrator is at the reference value, the second switch is closed and the first
The third and fourth switches are kept open for a first set time t_1, the fourth switch is closed, and the first, second, and third switches are kept open for a second set time t_3. Then, with the third switch closed and the first, second, and fourth switches open, the counter performs the second counting operation for the time until the output of the integrator returns to the reference value. The second set time t_3 is t_3=t_2−(r_
3E_3/r_2E_2) t_1.