JPS6057736B2 - A-D converter - Google Patents

Description

[Detailed description of the invention] The present invention relates to an oil converter.

The present invention relates to an oil converter that is made resistant to noise such as chatter by synchronizing a data transfer signal applied to a latch circuit with counted pulses input to a counter using three stages of half-bit flip-flops.

An object of the present invention is particularly to prevent switching noise of a digital circuit from being superimposed on an analog circuit and causing an error in an AD conversion value.

Another object of the present invention is to prevent malfunctions of latch circuits. The present invention can be applied to all types of AD converters that count pulses with a counter, and is very effective, but since it is most effective in a system called an integral type, hereinafter referred to as an example of an AD conversion system called a double integral system. We will explain the case when applied to.

As shown in Figure 1, the conventional AD conversion method called the double integration method includes an integrator 1, a comparator 2, a counter 3, a latch 4, a clock pulse generation circuit 5, a switch 6 and 7, and a control circuit 1. 8. As shown in FIG. 2, from the reference voltage source 9, the voltage to be converted Vx is input to the integrator for a certain period of time from the reset state using the switch 6, and is integrated.

Next, a reference voltage Vs with the opposite polarity to Vx is applied to the integrator through switch 7, and a comparator detects when it returns to the caliper reset bell, and calculates the time Tx from the time when inverse integration is started until the comparator is inverted. Count by counter/evening.
Since Tx is proportional to Vx, oil conversion is possible. Now, when the counter is 000, the control circuit opens and closes the switch so as to start integrating Vs, and at time Tl when the comparator is inverted, input the data transfer signal to the latch circuit. The latch circuit reads the contents and outputs the oil conversion value. The conventional system described above has the following two drawbacks.

That is, when spike noise due to the influence of clock pulses etc. is superimposed on the integrator output, the comparator is erroneously inverted as shown in FIG. 3, giving an error to the AD conversion value. Furthermore, as shown in Figure 4, when the timing at which the counter inverts and the timing at which the data transfer signal enters coincide, especially when a carry of the counter occurs, only the front stage of the counter is inverted and the rear stage is still inverted. It may be held by a latch before it occurs, causing a serious error in the AP conversion value. This is because the data of the counter 3 is input to the latch 4 when the transfer signal is H, so if the data changes during this time, some data will be input and some will not. The present invention eliminates the drawbacks of the conventional AD converter, and the circuit for generating the data transfer signal is composed of three stages of half-bit flip-flop circuits as shown within the dotted line in FIG. A synchronized data transfer signal is provided to the latch circuit.

The flip-flop circuit used here has a clock terminal CL.
When is H, the contents of data terminal D are passed through and output to Q, and when CL = L, the state of D immediately before the state of the CL terminal changes from H to L is held and output to Q. . Further, the counter 18 that counts pulses is assumed to advance at the falling edge of the clock, but the counter 18 is not limited to this case. This flip-flop circuit can be used as a latch circuit. The output of the comparator 12 is input to the D terminal of the flip-flop FFl-13, and the flip-flops FF2-14 and FF3-1 are sequentially input as shown in the figure.
5 are connected in cascade.

Each flip-flop is supplied with a clock that is in phase with the pulses counted by the counter 18 from an oscillator 19 to FFl, FF.
Apply a pulse of opposite phase to the CL terminal of FF2 to the CL terminal of FF2. As shown in Figure 6, the waveform of the comparator applied to the D terminal of FF1 is delayed by half a clock cycle, and
It is output to the Q terminal of F3.

Now, if we take the logical product of the negation of FF2's Q and the FF3's Q, we get
As shown in FIG. 6 and 7, 112 clock pulses whose rising and falling edges coincide are obtained. If this pulse is used as a data transfer signal, it will not be affected by the chatter of the comparator, and since the latch enters the hold state 112 cycles later than the timing at which the counter advances, malfunctions of the latch can be eliminated. Furthermore, large spikes are superimposed on the integrator waveform when the internal state of the counter changes (that is, when the counter advances, especially when a carry of the counter occurs), but as shown in FIG. An oil converter based on this method is completely unaffected by this. When the data transfer signal is created in this way, the latch holds the data from the moment the comparator inverts to the moment the source counter advances.Therefore, to prevent this phenomenon, a control circuit as shown in Figure 5 is required. It is a good idea to reset the counter for the period corresponding to the pulse emission at the point when you start integrating Vs from .If you make this reset time longer, the comparator will detect when the integrator output returns to the reference level. It is also possible to compensate for errors caused by the time required for (i.e., the response time of the comparator).Instead of resetting the counter, a gate circuit may be inserted between the oscillator 19 and the clock terminal of the counter to prevent the counter from advancing. The present invention is particularly effective when an analog circuit and a digital circuit are to be integrated into one integrated circuit, without requiring a capacitor or the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional AD converter and FIG. 5 is a block diagram of an AD converter according to the present invention.

Claims (1)

[Claims] 1. An oscillation circuit that generates a pulse train with equal time intervals, 2.
an integrator that integrates the voltage to be converted and a reference voltage; 3 a comparator that receives the output of the integrator and detects an input reset level; 4 a first flip-flop that receives the output of the comparator; second and third flip-flops connected in cascade to the oscillator circuit and inputting the output of the oscillation circuit as a clock; 5 a control circuit that controls the integration period; 6 a control circuit that counts the pulse train of the oscillation circuit and is reset by the control circuit; 7 a data transfer signal generated by AND outputting the negative output of the second flip-flop and the output of the third flip-flop; 8 latching the data of the counter only while the transfer signal is input; An AD converter comprising a latch circuit.