JPS6059611B2 - information processing equipment - Google Patents

Description

[Detailed description of the invention] The present invention relates to an information processing device.

Tightly coupled multiprocessing is a method in which multiple processors share a system control unit and main memory and operate externally as if they were a single processor information processing device (an information processing device with one processing reception window). It is called a processor method.

In an information processing device using this type of operation, when a processor fails and the processor is unable to continue processing, in the conventional device, the job that was being processed when the processor failed is It has to be abandoned (the work the processor has done on this job up to that point is wasted).

Also, at this point the processor is running the system program (
If the core part of the operating system (OS) is being executed, the system data commonly used by each processor will be interrupted midway through processing, so its correctness cannot be guaranteed.
Cause system down. An object of the present invention is to provide an information processing device that eliminates the above-mentioned conventional drawbacks. The devices of the present invention supply information on the inability to continue processing to the outside according to predetermined conditions when a failure occurs in each device, and transmit information necessary for continuing the processing to the outside in response to a transfer command supplied from the outside. It has a transfer circuit that can transfer and store information necessary for continuing the processing supplied from the external part, and a plurality of execution means that execute a predetermined transfer start command and issue a start to the outside. , a main storage device commonly used by the plurality of execution means, and a first execution means of one of the plurality of execution means in response to the supply of the processing continuation impossible information generated. Transferring the information necessary for the execution means to continue the processing of the execution means to a predetermined address area of the main storage device, and the activation based on the transfer start instruction executed by another second execution means. system control means for transferring and storing information necessary for continuing the processing transferred from the first execution means from the predetermined address area of the main storage device to the second execution means in response to the above. .

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Reference numeral 1 indicates a first processor (hereinafter CPUl),
This processor, together with the second processor 2 (Ishino QPU2), shares the system control unit 3 and main storage device 4 and operates as a tightly coupled multiprocessor system. When an error is detected as a result of executing a certain instruction in the CPU1 or CPU2, the installed hardware retries the instruction in accordance with the flowchart shown in FIG.

That is, first, when an error (for example, a parity error) is detected, the state of each register before execution of the instruction is restored (hardware is installed to enable this restoration).

The instruction is then retried and checked to see if any errors are detected in the results. If it is successful (if no error is detected), the next instruction is executed, but if it is not successful (if an error is detected), it is executed a predetermined number of times N according to the flowchart in Figure 2. If it is still unsuccessful, the initial state before execution of the instruction is restored, and the CPU notifies the system control unit 3 of information that it is impossible to continue processing. The following explanation will now be continued assuming that CPU1 has caused the above-mentioned failure.

FIG. 3 is a block diagram showing more detailed connections between each CPU and the system control section 3.

Now, the above-mentioned failure of the CPU1 is detected by the error detection circuit 10 included in the CPU1, and the above-mentioned processing inability information is sent to the system control unit 3 via the failure report line 11.
is supplied to cause an interrupt.

Upon receiving this fourth interrupt, the control section 3 instructs the CPU that caused the interrupt (currently CPU1) to perform a scan operation (transfer command) via the normal operation/scan operation instruction line 12. The functional circuit 13 of each CPU includes many registers for storing data at each processing stage, and each bit of each of these registers is configured by a flip-flop (F/F). ing. Therefore, a scan circuit (transfer circuit) 14 that is connected in series and operates as a shift register shifted by a clock is configured using a predetermined F/F among these in accordance with the scan operation instruction. . That is, when the operation instruction line 12 indicates normal operation, these F/Fs are F/Fs that can independently write and read 1-bit data under the control from the circuit 13. /F, but when the operation instruction line 12 instructs a scan operation, the 6'r', The data of 660F is then shifted into the transfer shift register 17 in the control section 3 via the scan-out line 15. In this way, when one word of data (for example, 64 bits) is shifted into the transfer shift register 17, the control unit 3 transfers this one word of data to a predetermined address in the storage device 4 in parallel. Transport and store.
Once this is completed, the data for the next one word is shifted in, transferred in parallel, and stored at the next address. The contents of all registers are transferred and stored in a predetermined address area of the main storage device 4. As mentioned at the beginning, the contents of these F/Fs are the contents that are restored to the state before the instruction was executed when an error occurs due to a certain instruction. The stored data contains all the correct information necessary for the CPU1 to continue executing the job it was doing from the failing instruction. Now, the system control unit 3, which has received the interrupt from the CPU1 that makes it impossible to continue processing, sends a message to the CPU2 via the external device failure interrupt line 18 in addition to the above processing. ) and instructs that the interrupted job should be continued in its place because CPU1 has failed.

When this interrupt is accepted, the CPU 2 sets a fault processing flag indicating that there is a fault to be processed in the interrupt routine, and immediately returns from the interrupt routine to the program currently being executed. Then, when the processing of the currently running program has finished (where this happens depends on the priority of the currently running program and the priority of the program that caused the problem, but in any case, When all the contents of the registers used by the program in the program have been processed and the results have been stored in the main memory and other locations, a scan start command (SWAPANDSTAR
T, transfer start command (hereinafter referred to as S-S) is executed. CPU2
When this instruction is stored in the instruction code register 19 to be executed, it is decoded by the decoder 20,
As a result, a report that the SS has been executed is supplied to the system control unit 3 via the scan start command (transfer start command) execution report line 21, causing an interrupt. When this interrupt is received, the control unit 3 sends one word of data (in this example, 64-bit data) from the first address where the contents of the register of the CPU1 of the main storage device 4 are stored.
are read out in parallel and stored in the transfer shift register 17.

And shift out output CP of this shift register 17
Connect to scan-in line 16 for U2 and
The contents of the shift register 17 are shifted into the scan circuit (transfer circuit) 14 attached to the functional circuit 13 of the CPU 2 using the normal operation/scan operation instruction line 12 for the CPU 2 as a scan operation instruction (transfer instruction). After this shift of one word is completed, one word of data is read from the next address of the main memory into the transfer shift register 17 in parallel and shifted in series, so that the CPU The contents of all necessary registers necessary for continuation of processing immediately before the failure occurs can be reproduced as the contents of the corresponding registers of the CPU 2. When this is completed, the control section 3 switches the operation instruction line 12 to normal operation. In this way, the CPU 2 can continue the job that the CPU 1 interrupted from the execution of the instruction that caused the error, and obtain the same result as if the CPU 1 had continued to execute the job without causing the error.

After a failure occurs in the CPU1, the processing capacity is reduced because the CPU1 no longer performs processing, but even during such a transitional period of failure handling, the processing continues without any essential hindrance to the outside world. You can continue.

In the above embodiment, the case of two CPUs has been described, but the present invention can be similarly applied to a case including a larger number of CPUs.

In this case, the system control unit that receives the information that it is impossible to continue processing from one CPU gives the external device failure information to another CPU in a predetermined order, or sends the information about the failure of the external device to another CPU in a predetermined order, or sends the information to the job that each CPU is currently executing. The CPU that first reports the execution of the scan start command by supplying external device failure information to a specific CPU determined according to the priority of
Various forms of relief can be taken depending on whether U is entrusted with continuing the job. Further, in the above embodiment, the external device failure information is supplied from the system control unit, but instead, the external device failure information is supplied from the failed CP.
The configuration may be such that the processing continuation impossible information issued by U is directly supplied to other CPUs as external device failure information.

Further, in this embodiment, all the flip-flops necessary for continuing a predetermined process are connected to one column of shift registers, but of course it can also be used as a shift register having a plurality of loops.

In addition, instead of using this type of register format, we use a circuit that writes and reads the contents of each register, which is generally provided for maintenance purposes separately from normal operation, to store the data necessary to continue processing. It is also possible to transfer

In addition, in this embodiment, as data necessary to continue processing, the contents of each register before the instruction that caused the error was executed are restored, and the contents of predetermined registers are transferred regardless of the instruction. However, instead of this, the data corresponding to the required instruction before execution is collected from the contents of each register at the time of error detection (therefore, it differs depending on the executed instruction) and transferred. It can also be configured.

As described above, by using the present invention, even if a failure occurs in a processor in a tightly coupled multiprocessor system, processing can be continued without abandoning jobs or causing system down, which is the case with conventional devices. It is possible to provide a device that enables this.

This has the effect of improving system reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an algorithm when the processor generates information that processing cannot be continued, and FIG. 3 shows a part of FIG. 1 in more detail. FIG. 2 is a block diagram for explanation. 1 and 3, 1...first processor (execution means), 2...second processor (execution means), 3...ustem control unit, 4.・・・・・・
・Main memory device, 10...Error detection circuit, 11
...Fault report line, 12...Normal operation/scan operation instruction line, 13...Functional circuit, 14...Scan circuit (transfer circuit), 15...
...Scan-out line, 16...Scan-in line, 17...Transfer shift register, 18...
...External device failure interrupt line, 19...Instruction code register, 20...Instruction decoder, 21...
...Scan start command (transfer start command) execution report line.

Claims (1)

[Claims] 1. In the event that a failure occurs in itself, each device supplies information on the inability to continue processing to the outside according to predetermined conditions, and in response to a transfer command supplied from the outside, transfers the information necessary to continue processing to the outside, and It has a transfer circuit that can transfer and store the information necessary to continue the supplied processing, and has a plurality of execution means that execute a predetermined transfer start command and issue a start to the outside, and is common to the plurality of execution means. and a main storage device used for processing of the execution means from the first execution means in response to the supply of the processing continuation impossible information generated by the first execution means of one of the plurality of execution means. Transfers information necessary for continuation to a predetermined address area of the main memory, and in response to the activation based on the transfer start command executed by another second execution means, the main memory An information processing apparatus comprising: a system control means for transferring and storing information necessary for continuing the processing transferred from the first execution means from the predetermined address area to the second execution means.