JPS6059776B2 - pulse width modulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width modulation circuit for converting a calculation result of a digital processing system into a pulse width modulation wave.

In recent years, with the development of digital processing technology accompanying the development of LSI, circuits that were conventionally configured as analog circuits are increasingly being digitized.

Along with this, A/D that connects the digital system and analog system
There are also increasing demands for accuracy and cost for converters and D/A converters. However, it is difficult to integrate these converters with digital systems into an LSI due to problems such as the accuracy of the resistors used. By the way, normal D/A
The converter converts the input digital signal into information in the amplitude direction as shown in FIG.

On the other hand, if the input digital signal is converted into pulse width information as shown in FIG. 1b and output, this becomes a pulse width modulated (PWM) wave. Like the AAM wave, this PWM wave also passes through a low-pass filter to become an analog waveform as shown in FIG. 1c. Therefore, pulse width modulation can be used in D/A converters. This kind of pulse width modulation circuit for A/A conversion can be realized by using a counter and a logic circuit, etc., since the output pulse width can be controlled by a counter according to the input digital signal, and it can be easily integrated into an LSI. it is conceivable that. The present invention has been made with attention to such points, and the calculation results of the data processing system are
The purpose of this invention is to provide a pulse width modulation circuit suitable for A conversion.

Usually, a digital processing system has a built-in control counter that divides the frequency of an original clock in order to generate a control clock that controls an arithmetic unit.

The present invention is characterized in that the contents of this counter are used for comparison with the calculation result of the digital processing system 5, and the calculation result is converted into a pulse width modulated wave. Second
The figure shows an embodiment of the present invention.

1 is a digital processing system, which operates according to an original clock 2;

Original clock 2 is added to control counter 3. In this example, the counter 3 is composed of six stages of binary counters 3a to 3f, and completes one cycle with 64 pulses of the original clock 2. Outputs 4a to 4f of each stage 3a to 3f of this counter 3 are 4a
The LSB144f is a natural binary code of the MSB, and is given to the arithmetic unit 5 together with the original clock 2. The arithmetic unit 5 is a circuit that performs digital arithmetic operations, such as a digital ● filter, and the outputs 4a to 4f of the original clock 2 and the counter 3.
(control clock), performs a predetermined calculation on the input signal 6, and the calculation result is 5 parallel 5 in this example.
Bit binary digital signals 7a to 7e are output. In this case, the sampling frequency of the digital processing system 1 (or the repetition frequency of the input signal 6 or output signals 7a to 7e) is 1164 times the frequency of the original clock 2. The output signals 7a to 7e of the arithmetic operation unit 5, which are the calculation results of the digital processing system 1, are transmitted to each stage 3a to 7e of the counter 3.
The outputs 4a to 4f of 3f are all taken into the latches 8a to 8e at a timing of 6"0"3, and are held for a period when the counter 3 completes one cycle.

The outputs 9a to 9e of the latches 8a to 8e are represented by natural binary codes, with 9a being the LSB and 9e being the MSB. Reference numeral 10 denotes a circuit that compares the arithmetic results of the digital processing system 1 taken into the latches 8a to 8e and the contents of the counter 3 for each corresponding bit, and determines whether a plurality of specific bits match or do not match.

That is, 11a to 11e are exclusive 0R (XOR) circuits, which compare the output of the counter 3 and the output of the latch circuit 8 with each other in corresponding bits, such as 4a, 9a, 14b, 9b, 14e, and 9e, respectively. When the two inputs match, “゜0” and when they do not match, “゜1゛” is output. The inverter 12 is the final stage 3f of the counter 3, that is, M
Invert the output 4f of SB. These XOR circuits 11a~
The outputs of 11e and inverter 12 are commonly applied to 0R circuit 13 and NAND circuit 14. 0R circuit 1
3 is used as a match judgment signal when 4a, 9a14b, 9b1...4e and 9e all match, and 4f, which is a bit higher than 4a to 4e compared with 9a to 9e, is at the ゜“1゛ level. , outputs a “0゛ level signal to the output 15.

N. The AND circuit 14 conversely connects 4a, 9a14b, and 9b1.
. . . When 4e and 9e all do not match, and 4f is at the "°0" level, a signal at the "°0" level is outputted to the output 16 as a mismatch determination signal. These 0R circuits 13 and NAN
Outputs 15 and 16 of the D circuit 14 are connected to two NAND circuits 2
1 and 22, respectively, to a reset terminal R and a set terminal S of a set/reset flip-flop 20.

This flip-flop 20 is reset when the output 16 of the NAND circuit 14 is "0", that is, when the mismatch judgment signal is input, and when the output 15 of the 0R circuit 13 is "0", the match judgment signal is input. is reset when input, thereby generating a PWM wave at the output 23.The pulse width of this PWM wave changes according to the values of the outputs 9a to 9e of the latches 8a to 8e.For example, 9a to 9e are When the order of 9e to 9a is ゜"11010゛ (representing ゛゜26゛ in W base), the flip-flop 20 outputs the outputs 4a to 4f of the counter 3.
is “゜00010”゛ (“5” in decimal) in the order of 4f to 4a.
It is set when 4f to 4a are 111
It is reset when it is 010゛ (represents ゜゜58゛ in W system).

At this time, the pulse width of the PWM wave of the output 23 of the flip-flop 20 is 58-3=5 for one period of the original clock 2.
This is equivalent to 3 clocks. As can be seen from this, the pulse width T of the PWM wave is T=(2X+1), where X is the value when the values 9e to 9a are expressed in decimal form. i.e. 9
With respect to the quantization step of e~9a, the change in the PWM pulse width T corresponds to two clocks, and this pulse width T is linear with respect to the increase/decrease of the values of 9e~9a, that is, the calculation results of the digital processing system 1. change. Moreover, the center position of each pulse of the PWM wave (the position of the broken line in Figure 1a) is 3f
This corresponds to the timing when the value of ~3a becomes ゜"100000゛, and the interval between these center positions, that is, the period of the PWM wave, is always the cycle period of the counter 3, that is, the sampling interval of the digital processing system 1 (or the input signal 6 or (repetition period of the output signal), and there is no FM component on the PWM wave.Therefore, by averaging this PWM wave through a low-pass filter, a D/
An A conversion output is obtained. As described above, by using the pulse width modulation circuit according to the present invention, it is possible to perform D/A conversion of the calculation results of the digital processing system with good linearity.

In this case, since a resistor is not used like a normal D/A converter, ? It is easy to convert into I, and there is no deterioration in conversion accuracy.
Particularly, in the present invention, a control counter in the digital processing system is used as a counter for comparison with the calculation result of the digital processing system in the pulse width modulation circuit, so that the logic of the comparison judgment circuit and the flip-flop circuit can be controlled. It has the advantage that the circuit can be easily constructed by simply adding the target parts. FIG. 3 shows another embodiment of the invention.

In this example, the control counter 3 is not a binary counter up to the final stage, but 3a to 3d constitute a binary counter, and 3e to 3g constitute a quinary counter. In this case, the outputs 4e to 4g of 3e to 3g are expressed in the order of 4g to 4e as "゜000゛,゜"00r゛,゜"010゛,"
From 011-゜゛100゛, it returns to "000゛.Also, in Fig. 2, the calculation results of the digital processing section 1 are taken out as parallel outputs, but in this example, they are taken out as serial outputs. That is, the values 4g to 4e are For example, when the value is "100", the serial 5-bit binary digital signal from the arithmetic unit 5 is sequentially input from the LSB to the shift register 8 for serial/parallel conversion, and the parallel outputs 9a to 9e are obtained from this shift register 8, and similarly It is input to the comparison/judgment circuit 10.Furthermore,
In this example, since the output signal of the seventh stage 3g of the counter 3 has been newly added, two inverters 12a112b are provided, and the outputs of these inverters 12a112b are sent to the 0R circuit 13 and the outputs of the XOR circuits 11a to 11e. It is commonly added to the NAND circuit 14. in this case,
The output 15 of the 0R circuit 13 has a convergence of "゜0゛, 4f is ゜゜1゛, and 4a, 9a14b, 9b1...4e and 9e.
When all match, 0゛, a toe saw match judgment signal is generated,
The output 16 of the NAND circuit 14 outputs ゜0゛ when the convergence is ``゜0゛, 4f is ``゜0゛, and 4a, 9a14b, 9b1...4e and 9e...all do not match. Therefore, when the convergence is ``1'', no judgment signal for either match or mismatch is output;
The output 3 of the flip-flop 20 is kept at "0". In this embodiment, the sampling frequency of the digital processing system 1 is 1180 of the original clock, but the resulting P
The pulse width of the WM wave is the same as in Figure 2, and P
The period of the WM wave is also longer than in the case of Fig. 2, but it remains constant. In this way, even if the control counter 3 is not configured as a full-stage binary counter, it is possible to obtain a PWM wave using this counter 3. The above explanation deals with the case where the output of the control counter and the calculation result of the digital processing system are natural binary codes, but even when the outputs of the control counter and the calculation results of the digital processing system are natural binary codes, these codes can be converted using known methods. The present invention can be similarly applied by converting it into a natural binary code.

As explained above, according to the present invention, a pulse width modulation circuit suitable for a D/A converter can be realized with a very simple configuration. As a known example, the D/A converter described in Japanese Patent Publication No. 48-22006 uses two comparators and two latch circuits to convert the first and second half of a pulse width modulated wave. They were created using separate paths and then synthesized, but in the present invention, a pulse width modulated wave in which the first half and the second half are continuous can be obtained at once with one comparing means and one flip-flop circuit. Coupled with the fact that the counter for pulse width modulation is shared with the control counter inside the digital processing system, the circuit configuration is significantly simplified compared to the known example.

[Brief explanation of drawings]

Figure 1 shows D/A conversion using normal D/A conversion and pulse width modulation.
FIG. 2 is a circuit diagram showing one embodiment of the present invention, and FIG. 3 is a circuit diagram showing another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Digital processing system, 3... Control counter, 5... Arithmetic unit, 10... Comparison/judgment circuit, 20...
・・Flip flop.

Claims (1)

[Claims] 1. In a pulse width modulation circuit for converting a calculation result output as a digital signal from a digital processing system with a built-in control counter that divides an original clock to create a control clock for controlling a calculation unit into a pulse width modulation wave. , a comparison means for comparing the calculation result and the output of the control counter for each corresponding bit, and all bits compared by the comparison means of the calculation result and the output of the control counter do not match, and When the state of the upper bits of the output of the control counter, including one or more higher-order bits that are not subjected to comparison by the comparing means, is in the first state, a mismatch determination signal is output, and the result of the calculation is compared with the above-mentioned means for outputting a coincidence determination signal when all bits compared by the comparison means with the output of the control counter match and the state of the upper bit of the output of the control counter is in a second state; and a flip-flop circuit that is reset by the mismatch determination signal from the means and set by the coincidence determination signal to output a pulse width modulated wave corresponding to the calculation result.