JPS6059809B2 - Phase comparison relay device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase comparison protective relay device for detecting a failure occurring in a power system by comparing phases between terminal electrical quantities.

FIG. 1a is a conceptual diagram showing how a power system is protected by a phase comparison relay device (hereinafter referred to as a relay).

In the figure, PHR-A and PHR-B are phase comparison protective relays, and the terminal current IA of the power transmission line Tl extracted by the instrument current transformers CT-A and CT-B installed at the A terminal and B terminal, respectively, By inputting the IB and comparing them with each other, a failure occurring between the two installation points, that is, within the protected area is detected. As is well known, PHR-A receives the transmission signal from PHR-B, and PHR-B receives the transmission signal from PHR-A, and compares the phase of this with the phase of the input current signal detected by itself. An output is obtained when the signals overlap by a predetermined electrical angle.

Incidentally, in order to perform phase comparison between PHR-A and PHR-B, transmission and reception is performed by a communication device, but a delay occurs in the transmission system including the communication device.

Therefore, by delaying the phase comparison signal at its own end by a time equal to this delay time, the influence of the delay caused by the transmission system is avoided. Figure 1b shows PHR-A, PHR-A
How to create HR-B phase comparison signal and transmission signal,
This is a waveform diagram showing the state of phase comparison in PHR-A.

Next, the internal circuit of the PHR will be explained with reference to FIG. Here, TDE-1 and TDE-2 are the delay circuits during operation, and TD
D-1 and TDD-2 represent return delay circuits. The level detection circuit LD outputs an output on the operating side when the instantaneous value of the input current is greater than a predetermined value, and outputs an output on the blocking side during other periods.The output e is sent to the other party as a transmission signal via the transmitter S. Sent out to the bitter end.

The output of the level detection circuit LD is also supplied to the operation delay circuit TDE-1 and the operation recovery circuit TDD- by the delay time of the transmission line.
The signal is delayed by a delay circuit consisting of 1, and its phase is compared with the received signal by an AND circuit AND as an own-end signal. At this time, the overlapping angle of the operating side outputs at both ends is the judgment angle θ (usually 600
) The above is an output from the operating delay circuit 1T)E-2, and a continuous output is obtained from the operating return circuit TDD-2.

Incidentally, it is the operating delay circuit TT)E-2 that determines the overlapping angle of the operating side output of the self-end signal and the received signal, but the operating side output longer than the judgment angle θ is output from the level detection circuit LD. Even if the transmission delay time is large, it will be erased by TDE-1, making it impossible to obtain correct characteristics.

This is illustrated in Figures 3a and 3b.

In Fig. 3a, the input current 1 is large compared to the detection level,
Therefore, the active side output of the level detection circuit LD is longer, indicating that the transmission delay time TD is accurately compensated and output. On the other hand, in Fig. 3b, the input current is 1
becomes smaller, and as a result, the operating side output of the level detection circuit LD becomes shorter, and even if its length is longer than the judgment angle θ for obtaining the PHR output, it will be erased by TDE-1 and the normal state will not be normal. This shows that the characteristics of PHR cannot be obtained. In order to eliminate the above-mentioned drawbacks, another conventional technique is to connect the TDE-1 and TDD-1 configurations in reverse to form TDD-1 and TDE-1. was.

However, in such a configuration, although the above-mentioned problems are eliminated, the following problems occur.

In other words, when a sudden change in phase occurs in the input current, there is a risk that although the operating side output of the level detection circuit is an intermittent waveform, it becomes a continuous signal due to TDD-1 and TDE-1. This will lead to PHR malfunction.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase comparison relay device that can compensate for transmission delays that occur in a transmission system when transmitting and receiving phase comparison signals without adversely affecting the characteristics of a phase comparison section. shall be.

FIG. 4 is a circuit diagram showing an embodiment of a phase comparison relay device using the present invention. The level detection circuit LD detects the level of the AC input current 1, converts it into a rectangular wave signal of an operating side output and a blocking side output, and inputs this signal to the transmitter S and the transmission delay time compensator CDC. This transmission delay time compensation device CD
C is constructed by connecting a plurality of delays in series according to the transmission delay time of the system in which the phase comparison relay device PHR is installed.

In this embodiment, two delay circuits T are used for reasons described later.
-1 and T-2 are connected in series. Then, the output signal E4 of the transmission delay time compensator CDC is sent to the AND circuit AN along with the signal FR received by the receiver R.
D, and the coincidence of the active side outputs of both signals is detected here.

When the operating side outputs of both signals E4 and FR match, a signal is output from the AND circuit AND. This signal is measured by the time measuring circuit TDE-3 and produces an output if it continues for a predetermined time O or more. TDD-3 is a continuity circuit provided for a subsequent stage circuit (not shown). Now, as mentioned above, the transmission delay time compensator CDC accurately shifts (delays) by the scheduled time AD even if the width of the operating side output of the output signal EL of the level detector LD is narrow, if it is greater than the judgment angle θ. In order to make this possible, first and second delay circuits T-1 and T-2 are provided in series.

These first and second delay circuits T-1 and T-2 are provided with operating delay circuits TDE-1 and TDE-2 and return delay circuits TDD-1 and TDD-2 in series as shown in the figure. There are things.

When the operating side input is applied to the operating delay circuits TDE-1 and 1T)E-2, the delay circuits TDE-1 and 1T)E-2 delay for a certain period of time TDl and
2, the active side output is generated, and when the active side input is lost, the active side output is immediately lost.

Recovery delay circuit ↑゛DD-1 and TDD-2 immediately produce an active output when the active input is applied, and when the active input is lost, the output is output for a certain period of time, TDl and TD2, respectively.
After that, the operating side output is lost. These fixed times TDl and TD2 have a relationship with the sum of shift amounts and the determination angle θ of the apparatus shown in FIG.

TDl and TD2 may or may not be equal.
The number of delay circuits connected in series is preferably determined as follows.

In other words, the sum of transmission delay times is divided by the phase overlap judgment angle θ,
The number should be greater than or equal to the quotient. For example, 50Hz
In the power system, the phase weight judgment angle θ is 600 (when 600 is converted to time, Tθ = 10/3 (Ms)) and the sum of transmission delay times is 5.
(Ms), the number n of delay circuits in series is n=2≧
'IT)/Tθ. Individual delay circuits T-1, T-2
Even if the delay times TDl and TD2 are 5/2 (Ms),
Alternatively, 11) 1 = 3 (Ms) and TD2 = 2 (Ms) may be used, and the total amount may be equal to 5 (Ms).

The operation of the present invention will be explained with reference to FIGS. 4 and 5.

When the input currents 1A and iB at both the A terminal and the B terminal become larger than the slice level value of the level detection circuit LD, an active side output signal EL is generated.

This signal e is transmitted by the transmitter S to the other party as a signal Fs, and is also sent to the transmission delay time compensator CDC at its own end.
is input to.

First, the first stage delay circuit T-1 is the operating delay circuit TDE.
-1, a signal e1 which is shorter in time than the signal EL by TDl is outputted, and this signal e1 is input to the decoding delay circuit TDD-1 to obtain the signal E2. This signal ♂ is a signal obtained by shifting the output signal EL of the level detection circuit by TDl. Next, the signal E2 is sent to the second stage delay circuit T-2.
The signal E3 is input to the operating delay circuit TDE-2. This signal E3 is shorter than E2 by TD2. This signal E3 is sent to the second return delay circuit '1T)D-
2 to obtain signal E4. This signal is a signal shifted by TD2 with respect to E3, and as a result, E4 is shifted by TD1+TD2=TD compared to EL and is output.
The phase of this signal E4 is compared with the received signal (2) from the other end using an AND circuit AND, and a signal E is output. This signal. is input to the time judgment circuit '11) E-3, and E5 is the judgment angle θ.
(For example, if the angle is 600 degrees) or more, the sheath breaker trip signal E6 is outputted through the continuity circuit TDD-3. In the above operation, if the operating side output signal of the output EL of the level detection circuit is longer than the judgment angle θ, e is changed for a time TDl.
The signal E4, which is longer than TD2, is necessarily EL shifted by the time sum.

When EL is shorter than the determination angle θ, e is shorter than the time TDl or TD2, and the operating side output may not be obtained as the signal E4. However, in this case, even if the operating side output is obtained at E4, its length is shorter than the judgment angle 0, and the output E
Since there is no possibility of causing 6, there is no problem. In the embodiments of the present invention described above, two sets of transmission delay time compensation circuits are connected in series as shown in FIG. Even if the time value or the determination angle θ of the overlap angle of phase comparison changes, there is no problem in implementing the present invention. or,
Although the above description has been made regarding a phase comparison relay device that handles current as an input quantity of electricity, it goes without saying that the present invention can also be applied to a phase comparison relay device that handles voltage in the same way. Furthermore, which of the delay circuits T-1, T-2, T-n
The set value of DE may be in a fixed state and any of them may be in a variable state, or all of them may be in a variable state.

As described above, the present invention connects a plurality of delay circuits with small shift amounts in series so that the sum of the individual shift amounts matches the transmission delay time of the transmission system.

Therefore, even if the input current is small and the width of the output waveform of the level detection circuit is narrow, or the transmission delay time is too long, it is necessary to operate within the transmission delay compensation device as in the past. The operating side signal is never erased. Therefore, the phase comparison of electrical quantities can be performed without being affected by the transmission delay time of the transmission line. ``Brief explanation of the drawings Figures 1A and b are a diagram of the principle of the phase comparison relay device and a time chart for explaining the operation, Figure 2 is a block diagram of a conventional phase comparison relay, Figures 3a and b is a diagram showing the relationship between the level detection circuit output and the transmission delay compensation circuit output of a conventional phase comparison relay, FIG. 4 is a block diagram of the phase comparison relay according to the present invention, and FIG. 5 is a diagram showing the phase comparison relay according to the present invention. FIG. 3 is a diagram showing the relationship between the output of the level detection circuit output of the transmission delay compensation circuit, the received signal, etc. of FIG.

Claims (1)

[Claims] 1. Signals classified into operating and non-operating sides according to the instantaneous value of current or voltage in the power system are obtained at the own terminal and other terminals of the power transmission line, and the signals transmitted from the other terminals and the signal at the own terminal are obtained. In the phase comparison relay device, which operates when the electrical angle of overlap with the signal delayed by the transmission delay time compensator is larger than the judgment angle θ, the transmission delay time compensator is configured to detect a plurality of signals whose delay times are shorter than the judgment angle θ. delay circuits are connected in series, and the delay time as a transmission delay time compensation device is selected to be equal to the transmission delay time of the transmission system.When an input on the operating side is applied, each delay circuit An operating delay circuit that generates an output and immediately loses the operating output when the operating input is lost; and an operating delay circuit that uses the output of this operating delay circuit as an input and immediately produces an output when the operating input is applied, and immediately loses the operating output when the operating input is lost. 1. A phase comparison relay device comprising a recovery delay circuit which loses an output on the operating side after a delay time when the output is lost.