JPS606102B2 - Semiconductor protection circuit device - Google Patents
Semiconductor protection circuit deviceInfo
- Publication number
- JPS606102B2 JPS606102B2 JP50061661A JP6166175A JPS606102B2 JP S606102 B2 JPS606102 B2 JP S606102B2 JP 50061661 A JP50061661 A JP 50061661A JP 6166175 A JP6166175 A JP 6166175A JP S606102 B2 JPS606102 B2 JP S606102B2
- Authority
- JP
- Japan
- Prior art keywords
- protection circuit
- circuit device
- voltage
- mos transistor
- semiconductor protection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
- Electronic Switches (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
この発明は、ＭＯＳＬＳＩの初段ゲートに高電圧が加わ
った場合に、初段ゲートが破壊されるのを防ぐようにし
た半導体保護回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor protection circuit device that prevents the first stage gate of a MOSLSI from being destroyed when a high voltage is applied to the first stage gate.
第１図は従来のこの種の半導体保護回路装置を示す回路
図であり「 Ｒは抵抗、ＴはＭＯＳトランジスタであっ
て、入力信号は抵抗Ｒを通して伝達され、保護効果が十
分表われるためには、抵抗Ｒはある程度以上の値を必要
とし、その結果、浮遊容量Ｃとの積分回路の時定数（Ｃ
，Ｒ）が大きくなり、高速動作が困難である。この発明
は、上記の点にかんがみなされたもので、従来の保護回
路装置以上の保護効果を有し、かつ簡単な構成で高速動
作が可能な半導体保護回路装置を提供するものである。FIG. 1 is a circuit diagram showing a conventional semiconductor protection circuit device of this type. "R is a resistor, T is a MOS transistor, and the input signal is transmitted through the resistor R. In order to fully exhibit the protection effect, , the resistance R needs to have a value above a certain level, and as a result, the time constant (C
, R) becomes large, making high-speed operation difficult. The present invention has been made in consideration of the above points, and it is an object of the present invention to provide a semiconductor protection circuit device that has a protection effect superior to that of conventional protection circuit devices and is capable of high-speed operation with a simple configuration.
次に、図面を参照してこの発明の半導体保護回路装置の
実施例について説明すると、第２図はその一実施例の回
路図であり、この第２図におし、て、ＴはＭＯＳトラン
ジスタである。Next, an embodiment of the semiconductor protection circuit device of the present invention will be described with reference to the drawings. FIG. 2 is a circuit diagram of one embodiment, and in FIG. 2, T is a MOS transistor. It is.
このＭＯＳトランジスタＴは大きなコンダクタンスを有
するものが使用され、ソースフオロアーとして使用され
ている。This MOS transistor T has a large conductance and is used as a source follower.
ＭＯＳトランジスタＴのドレィン１は入力端子ｔ，に接
続されており、この入力端子ｔ，と入力端子ｔ２とは対
をなし、入力端子りま接地されている。ＭＯＳトランジ
スタＴのゲート３は接地され、ソースは抵抗Ｒを介して
接地されているとともに、出力端子ら‘こ接続されてい
る。The drain 1 of the MOS transistor T is connected to the input terminal t, and the input terminal t and the input terminal t2 form a pair, and the input terminal is grounded. The gate 3 of the MOS transistor T is grounded, the source is grounded via a resistor R, and the output terminal is connected.
この出力端子ら‘ま出力端子ｔ４と対をなし、この世力
端子ｔ４は接地されている。ＭＯＳトランジスタＴのゲ
ート４は抵抗Ｒを経て端子ｔ５に接続されており「 こ
の端子らにはＶｏｏの電圧が印加されるようになってい
る。This output terminal forms a pair with output terminal t4, and this output terminal t4 is grounded. The gate 4 of the MOS transistor T is connected to the terminal t5 via the resistor R, and the voltage Voo is applied to these terminals.
抵抗Ｒは出力側が完全に開放されることがなければ、省
略することができる。The resistor R can be omitted unless the output side is completely opened.
次に、以上のように構成されたこの発明の半導体保護回
路装置の動作について説明すると、入力端子ｔ，，ｔ２
間に印放される入力信号の電圧が低い場合には、ＭＯＳ
トランジスタＴは３極管領城で動作するので、ドレイン
１とソース２間の電圧が低く、出力側には入力側の電圧
にほぼ比例した電圧第３図（入力電圧と出力電圧との関
係を示す図）に示すごとく生じ、信号が伝達される。Next, the operation of the semiconductor protection circuit device of the present invention configured as described above will be explained.
If the voltage of the input signal released between
Since the transistor T operates as a triode, the voltage between drain 1 and source 2 is low, and the voltage on the output side is approximately proportional to the voltage on the input side (Figure 3 shows the relationship between input voltage and output voltage). The signal is transmitted as shown in Figure).
入力信号と出力信号との比例関係はディジタル動作を目
的とする場合にはあまり重要でな〈トこの発明はこの点
について満足する。次に、入力電圧が高くなると、ＭＯ
ＳトランジスタＴは飽和領域で動作するようになり、Ｍ
ＯＳトランジスタＴのドレィン１とソース２間を流れる
電流は一定となる。The proportional relationship between the input signal and the output signal is not very important for purposes of digital operation, and the present invention satisfies this point. Next, as the input voltage increases, the MO
The S transistor T now operates in the saturation region, and the M
The current flowing between the drain 1 and source 2 of the OS transistor T is constant.
したがって、出力端子らとｔ４間には一定の電圧しか発
生せず、過大入力電圧が印加された場合でも、ある一定
の出力電圧以下になり「ゲート破壊を防ぐ保護回路装置
として充分な特性を有するものである。なお、次の第１
表は上記第２図の実施例の各素子の値を示すものである
。Therefore, only a constant voltage is generated between the output terminals and t4, and even if an excessive input voltage is applied, the output voltage remains below a certain level, and has sufficient characteristics as a protection circuit device to prevent gate breakdown. In addition, the following
The table shows the values of each element in the embodiment shown in FIG. 2 above.
第１表
以上のように、この発明によれば、ＭＯＳトランジスタ
をソースフオロアーとして使用し、そのドレィンに入力
信号を印加し、ソースを出力端子とし、入力信号の電圧
が低い間は入力電圧に比例した電圧を出力側に生じさせ
、入力電圧が高くなると、ＭＯＳトランジスタを飽和領
域で動作するようにして「出力電圧を一定の出力電圧以
下にするようにしたので、従来のごとく積分回路が不要
となり、簡単な回路で高い入力電圧に対して確実にかつ
高速度で保護動作を行なうことができるものである。As shown in Table 1 and above, according to the present invention, a MOS transistor is used as a source follower, an input signal is applied to its drain, the source is used as an output terminal, and while the voltage of the input signal is low, the input voltage is applied to the MOS transistor. A proportional voltage is generated on the output side, and when the input voltage increases, the MOS transistor operates in the saturation region to keep the output voltage below a certain output voltage, so there is no need for an integrating circuit like in the past. Therefore, the protection operation can be performed reliably and at high speed against high input voltages with a simple circuit.
第１図は従来の半導体保護回路装置の回路図、第２図は
この発明の半導体保護回路装置の一実施例の回路図、第
３図は同上半導体保護回路装置の動作を説明するための
入力電圧と出力電圧との関係を示す図である。
Ｔ・・ＭＯＳトランジスタ、Ｒ，Ｒ′…抵抗Ｌｔ，，ｔ
２・・・入力端子、ら，ｔ４…出力端子。
第１図
第２図
第３図FIG. 1 is a circuit diagram of a conventional semiconductor protection circuit device, FIG. 2 is a circuit diagram of an embodiment of the semiconductor protection circuit device of the present invention, and FIG. 3 is an input diagram for explaining the operation of the same semiconductor protection circuit device. FIG. 3 is a diagram showing the relationship between voltage and output voltage. T...MOS transistor, R, R'...resistance Lt,,t
2...Input terminal, ra, t4...Output terminal. Figure 1 Figure 2 Figure 3
Claims (1)
スタがオン状態となる一定電圧を印加すると共に上前Ｍ
ＯＳトランジスタのドレインに入力信号を印加し、かつ
上記ＭＯＳトランジスタのソースの側に抵抗を接続して
上記ソースと上記抵抗との接続部より出力を取り出すこ
とを特徴とする半導体保護回路装置。1 A constant voltage is applied to the gate of the MOS transistor to turn on the MOS transistor, and the upper and lower M
A semiconductor protection circuit device characterized in that an input signal is applied to a drain of an OS transistor, a resistor is connected to a source side of the MOS transistor, and an output is taken out from a connection between the source and the resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50061661A JPS606102B2 (en) | 1975-05-22 | 1975-05-22 | Semiconductor protection circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50061661A JPS606102B2 (en) | 1975-05-22 | 1975-05-22 | Semiconductor protection circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS51137386A JPS51137386A (en) | 1976-11-27 |
| JPS606102B2 true JPS606102B2 (en) | 1985-02-15 |
Family
ID=13177617
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50061661A Expired JPS606102B2 (en) | 1975-05-22 | 1975-05-22 | Semiconductor protection circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS606102B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5257237U (en) * | 1976-10-13 | 1977-04-25 | ||
| JPS54159188A (en) * | 1978-06-06 | 1979-12-15 | Nec Corp | Semiconductor device |
| JPS61140217A (en) * | 1984-12-12 | 1986-06-27 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
-
1975
- 1975-05-22 JP JP50061661A patent/JPS606102B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS51137386A (en) | 1976-11-27 |
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