JPS60678B2 - electronic timing circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to a circuit for electronically transmitting time signals.

As this type of secondary circuit, for example, a circuit as shown in FIG. 1 is used. In the figure, reference numeral 1 denotes an input terminal, and in order to determine the time interval, time signal pulses arranged at regular intervals are applied to the input terminal 1. This pulse is applied to transfer gate 3 via transfer gate 2 (for example an AND gate). 4 is a pulse generating circuit which generates pulses at regular intervals, and these pulses are applied to the transfer gate 3 mentioned above.

The signal that has passed through the transfer gate 3 is power amplified by transistors 5 and 6, and a time signal is output from a speaker 7. In this circuit, the pulses are converted into sounds and the sound contains high frequency components, so it is not possible to produce a pleasant sound. FIG. 2 is an improved version of the conventional example shown in FIG. 1, and the essential difference from the circuit shown in FIG. 1 is that a resistor 8 and a capacitor 9 are connected in parallel between the output terminal of the transfer gate 2 and the ground. This is because a buffer amplifier consisting of transistor 0, a capacitor 1, and a low-pass filter 13 consisting of a variable resistor 12 are inserted between the transfer gate 3 and the transistors 5 and 6.

In this circuit, the time signal pulse attenuated by the parallel circuit of the resistor 8 and capacitor 9 and the output pulse train of the clock pulse generating circuit 4 are applied to the transfer gate 3. Therefore, when the output pulse train of the clock pulse generating circuit 4 passes through the transfer gate 3, it is shaped into an attenuated train. The attenuated train of the clock pulses is applied to the transistor buffer 10 to undergo impedance conversion, and the output of the transistor buffer 10 is connected to a capacitor 1 and a variable resistor 12.
The signal is applied to a low-pass filter 13 consisting of a parallel circuit.
Since the input impedance of the transistor buffer 1 is high and the output impedance is low, the transfer gate 3 and the low-pass filter 13 are separated in terms of circuitry. The attenuated train of pulses is connected to the transistor 5,
6, the power is amplified, and the speaker 7 emits a ticking sound.
However, the low-pass filter 13 has a large loss, and the circuit separation due to the buffer 01 is incomplete, so that the charge accumulated in the capacitor 11 is transferred to the capacitor 11.

This method has disadvantages such as having a negative effect on the attenuation train of the clock pulse. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks by using an active filter, and to provide an electronic timing circuit that can obtain a first-order sine wave as a time signal output.

The present invention will be explained in detail below with reference to FIGS. 3 and 4.

FIG. 3 shows the timing circuit of the present invention.

In the figure, the input terminal of the inverter 1, to which the time signal pulse is applied, is connected to the control input terminal P of the transfer gate G.
, connect the output terminals of the inverter 1, to the control input terminal P2 of the transfer gate ○, respectively, and connect the positive terminal of the DC power supply VB to the input terminal of the transfer gate G via the resistor R, respectively. Then, the output terminal of the transfer gate ○, is connected to the input terminal of the second transfer gate ○2. Further, the output terminal of the transfer gate ◯ is grounded via a parallel circuit of a resistor R2 and a capacitor C. The inverter 1, transfer gate G. , resistance R, . R2
, C, constitute an attenuation circuit ATT, and when a time signal output pulse from a digital clock shown in FIG. 4A is applied to the input terminal of the inverter 1, the transfer gate G is opened. , the resistor R2, and the capacitor C, an attenuated pulse output of the time signal output pulse shown at the beginning of FIG. 4 is obtained. By changing the resistance R, the rising characteristics of the ablation pulse can be controlled. The control input terminal P2' of the second transfer gate 02 is connected to the output terminal of the second inverter 2,
The control input terminals P,' are connected to the input terminals of the second inverter 12, and the clock pulse generation circuit CL
The transfer gate G2 and the inverter 12 constitute a gate circuit OAT. The clock pulse generation circuit CLK continues the inverters 13, 14, and 15, and the inverter 13
The input terminal is connected to the input terminal of the inverter 14 via a resistor R4, and is connected to the output terminal of the inverter L via a capacitor C2. generates a pulse. The output terminal of the second transfer gate G2 is connected to the base of the transistor Tr2. The base of the transistor Tr2 is grounded via a resistor R3. When the attenuation pulse shown in FIG. 4 is applied to the input terminal of the second transfer gate G2, the second transfer gate G2 of the gate circuit OAT is opened and the clock pulse is applied to the input terminal of the second transfer gate G2. The attenuation waveform of the clock pulse of the generating circuit CLK, that is, the clock pulse train that gradually attenuates as shown in FIG.
is applied to the base of The attenuated pulse will have been modulated by the clock pulse. The collector of the transistor Tr2 is connected to the positive terminal of the DC power supply V via the resistor 5, and the emitter is grounded via a parallel circuit of a series circuit element of a resistor R7 and a capacitor C3, and a resistor RL. . The transistor circuit ACF is an active filter, and when the input pulse of the transistor Tr2 is at the resonant frequency of the resonant circuit made up of the resistor R6, the resistor R7, and the capacitor C3, the transistor Tr2 becomes conductive and a current flows. For anything other than numbers,
It is non-conductive. Therefore, when the attenuated clock pulse train is applied to the base of the transistor Tr2, the transistor Tr2 of the active filter ACF resonates with the frequency of the clock pulse train and becomes conductive. A sine wave with a frequency determined by the resonant circuit of the parallel circuit is generated as shown in the tree in Figure 4. The collector of the transistor Tr2 is connected to the base of the transistor Tr3 of the power amplifier circuit P via a resistor R8. In the power amplification circuit P, collectors of Darlington-connected transistors Tr3 and Tr4 are connected to the positive electrode of the DC power supply VB via a speaker SP,
The emitter of the transistor Tr4 is grounded via a resistor R9. The output of the transistor Tr2 of the active filter ACF is power amplified by the power amplification circuit P, and a sine wave ticking sound is emitted from the speaker SP. As described above, the electronic timing circuit of the present invention uses an active filter to achieve A. You can get a pleasant ticking sound that is close to the sounds of nature.

B. The matching problem that inevitably occurs when using a passive filter as in the conventional example is eliminated, and the degree of freedom in circuit design is increased. and other remarkable effects.

[Brief explanation of drawings]

FIGS. 1 and 2 are electronic timing circuit diagrams of the sub-chamber, FIG. 3 is an electronic timing circuit diagram of the present invention, and FIG. 4 is a waveform diagram of the same operation. 1... Input terminal, 2, 3... Transfer gate, 4... Pulse generation circuit, 5, 6...
...Transistor, 7...Speaker, 8...
...Resistor, 9...Capacitor, 10...Transistor, 11...Capacitor, 12...Variable resistor, 13...Low pass filter, 1, to 15...
...Inverter, Tr2 to Tr4...Transistor, G,
~G2...transfer gate, P,,P2,P,
', P2'...Transfer gate control input terminal,
R (~R9...Resistor, C, ~C3...Capacitor, SP...Speaker, VB...DC power supply, ATT...Attenuation circuit, CLK ...Clock pulse generation circuit, CAT'...Gate circuit, ACF...Active filter, P...
・Power amplifier circuit. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. Attenuation circuit AT that provides attenuated pulse output of input pulse
T, a gate circuit GAT to which the output of the attenuation circuit and the output of the clock pulse generator are applied, an active filter ACF of a transistor when the output of the gate circuit is applied, and a power amplification of the output of the active filter to drive a speaker. An electronic timing circuit characterized by comprising a power amplification circuit P. 2. The transistor of the active filter ACF has a collector connected to a DC power supply via a resistor, an emitter connected via a parallel resonant circuit, and a base grounded via a resistor. Electronic timing circuit.