JPS60699B2 - data processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing system that can quickly find errors in programs and the like.

The cost of producing a program does not increase proportionally to the number of program steps, but rather increases exponentially.

In order to reduce the production cost of programs, it is desired to debug programs quickly and inexpensively. However, with the prior art, it has been impossible to debug programs quickly and inexpensively. Furthermore, in order to improve the reliability of a computer system, particularly important program modules, such as an OS dispatcher, must be completely insect-free. The present invention is based on the above considerations, and aims to provide a highly reliable data processing system that can quickly find errors in programs and the like.

Therefore, the data processing system of the present invention has multiple types of distinct programs that perform the same function.
comprising a memory device storing a series of programs including modules and module switching instructions, and a processor; when the discrete module switching instruction is read, the plurality of discrete modules specified by the module switching instruction is read. Kutfu. . gram module is configured to be executed. Hereinafter, the present invention will be explained with reference to the drawings.
The figure is a block diagram of one embodiment of the present invention, in which 1 is a central processing unit, 2 is a comparator, 3 is an instruction register, 4 is a control register (for example, a fake W register), 5 is a local memory, and 6 is a block diagram of an embodiment of the present invention. is the main memory, 7 is absent, and 1 is the AND circuit, 1
2 None, 1 4 is a latch, MA, and MA2 are distinct program modules, AD is the start address of distinct program module MA, AD2 is the start of distinct program module A2 Address, DPE is error signal bit, D
P is a distinct program mode display bit, D, and D2 are diagnostic areas, F is a positive scale area, P, and P2 are distinct program processing areas, 1
indicate the input data area, respectively. Note that in this specification, a distinct program is
Refers to program modules that have the same processing functions but different hardware and software configurations.
"EC, DD, AD,
, AD2'' indicates a module switching command, and when the above module switching command is read, the data processing system operates in discrete program mode.

In distinct program mode, "distinct program specified by address AD,
Module MA is executed first, and its processing results are written to discrete program processing module P. Next, the distinct program module M is executed, and the processing result is
It is written to the program processing area P2. Input data·
Area 1 stores the processing results of the previous module. As for the processing results of the areas P and P2, the comparison result of the comparator 2 is valid when the display bit DP is "1". The display bit DP can be turned on and off manually from the operation panel, and can also be turned on and off by command. Then, if both processing results match, the processing result is AN
It is written to the correct answer area F via the D circuit 10, latch 14 and AND circuit 9. Writing to the correct answer area F is performed independently of the execution of the next module's processing. If the comparison result of comparator 2 indicates a mismatch, Elya P,
The processing results are sent to the diagnostic data via the latch 12 and the AND circuit 7. Further, the processing result of the area P2 is written to the diagnostic area D2, and at the same time, the error display bit DPE is set to "1". In the above embodiment, the processing for the distinct program P
, , P2 are provided in the local memory 5, but the processing area for the distinct program may be provided in a working register or a file.

The reason for providing the distinct program processing area is to prevent the calculation speed from decreasing. Further, in this embodiment, the distinct program mode indication bit DP is provided in the control register, but it may be provided in the memory.

Further, in this embodiment, the correct answer F is provided in the main memory 6, but the correct answer may be provided in a file. The reason why the process of writing the correct answer value is performed independently of the execution of the process of the next module is to reduce the execution speed of the central processing unit when a distinct program is executed. Further, in this embodiment, the input data area 1 is provided in the local memory 5, but the input data area 1 may be provided in a register, a file, or the main memory. The processing results of the distinct program modules MA and M~ are written in the processing area P or P2, but the processing results are transferred to the input data area 1 by the hardware mechanism or firmware. Alternatively, a switching mechanism may be provided in which the processing result storage portion in area P or P2 is used as the input data area for the next module. The reason why a dedicated input data area is provided to store the processing results of the previous module is to eliminate the need to access the main memory each time and improve the processing speed of the central processing unit. In the above embodiment, two distinct program modules are provided, but more than two distinct program modules may be provided.

In this case, a majority logic circuit may be used instead of the comparator 2, and the larger value may be taken as the positive value. As is clear from the above description, according to the present invention, programs and hardware can be debugged easily and quickly.

The present invention can also be used to improve the reliability of particularly important program modules, such as the OS dispatcher.

[Brief explanation of drawings]

The figure is a block diagram of one embodiment of the present invention. 1...Central processing unit, 2...Comparator
3...Instruction register, 4...Control register,
5... Local memory, 6... Main memory, 7 None, 11... AND circuit, 12 to 14... Latch, MA, and MA2... Distinct program module, AD, and AD2... Day Stained...
Start address of program module MA,,M,
DP... Destinct pu.

Claims (1)

[Scope of Claims] 1. A processor comprising a memory device storing a series of programs including a plurality of types of distinct program modules and module switching instructions that perform the same function, and a processor; A data processing system characterized in that, when a switching instruction is read, a plurality of distinct program modules instructed by the module switching instruction are executed. 2. The data processing system according to claim 1, wherein if the plurality of processing results do not match, an error signal bit is set in the control register. 3. The data processing system according to claim 1, wherein a majority vote is taken from a plurality of processing results. 4. The data processing system according to claim 1, 2, or 3, characterized in that when a discrepancy occurs between the plurality of processing results, the plurality of processing results are written in a diagnostic area. 5. The processing results of multiple discrete programs are compared only when a discrete program mode indication is prepared in the control register or memory and the discrete program mode indication bit is on. Claims 1 and 2 are characterized by
3. The data processing system according to item 3 or 4. 6. Claims 1, 2, 3, and 4, characterized in that an area for storing each of a plurality of processing results is prepared for a discrete program.
5. The data processing system according to item 5. 7. Claims 1, 2, and 3, characterized in that the correct value of the processing result is written to a file or memory independently of the execution of the next program module process.
6. The data processing system according to item 4, item 5, or item 6. 8. Claims 1, 2, and 3, characterized in that it has a dedicated input data work area, and the processing result of the immediately preceding program module is stored in the dedicated input data work area. The data processing system according to item 4, 5, 6, or 7. 9. The data processing system according to any one of claims 1 to 8, wherein one processor sequentially processes a plurality of discrete program modules one by one.