JPS607302B2 - buffer memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer memory device in a data processing device.

With recent advances in hardware technology, the processing power of central processing units in data processing systems has improved, and as a result, the proportion of time spent accessing main memory compared to calculation time in system processing power has increased. The problem is that the overall processing capacity is limited by the access time of the main memory.

As a means to solve this problem, a cache memory (cache memory or buffer memory), which has a small capacity and can be accessed at high speed and stores a copy of the data on the main storage device, has been adopted.

When using a cache memory, when the central processing unit reads new data from the main memory, it reads the preceding and succeeding information including that information, retains it in the cache memo, and uses it for subsequent access. If the information required by the system is held in the cache memory, reading the data from the cache memory eliminates the need to access the main memory, reducing the actual main memory access time to the cache memory access. A method to increase the speed is being explored. In this case, when it is necessary to write data to the main memory, at the same time as writing the data to the main memory, if the data at the address in the cache memo is stored, the contents of the cache memory are also rewritten. ing.

Furthermore, due to the combination of access requests to the main memory layer from other central processing units or input/output transfer control units, access requests are not immediately accepted by the main memory.
There may be cases where you are forced to wait for a meeting, which can lead to performance degradation. As a way to solve this problem, since the performance of the central processing unit does not depend mainly on the write access time to the main memory, but is affected by the read access time, a write buffer that temporarily holds write access information is used. If a read access request is issued from the central processing unit to the main memory while the write access request is not accepted by the main memory and is waiting, the read access request is transferred to the write buffer. A method is adopted in which access requests are given priority.

However, at this time, there is a possibility that a read access request that occurs later will be made to the same main memory area as the write access request held in the write buffer, and the read access will be performed after the write access is completed and the main memory This must be done after the content inside has been rewritten with new content.

Traditionally, the methods used to handle this have been to have special comparison circuits to check for a match between the address of each word in the write buffer and the address of the read access;
Or, by configuring the write buffer's address storage with a special associative memory, we check for a match between the address held in the write buffer and the address by the proposed access, and if a read access is outside the same data as a pending write access. When this is detected, the write access in the write buffer is processed first, and then the proposed access is performed.

However, as mentioned above, as the number of words in the write buffer increases, the circuit for detecting whether the proposed access to the main memory and the write access in the write buffer are accessing the same area of the main memory is difficult. Accordingly, a large amount of hardware is required, which is a major drawback in the write buffer control method.

An object of the present invention is to solve the above-mentioned drawbacks by also managing write access information registered on the write buffer using a memory for storing address information provided in the cache memory. To provide a means for detecting a collision between a write access in a buffer and a proposed access to a main memory device, and a data buffer device having a write buffer realized without having special hardware such as an associative memory. It is in.

According to the present invention, the data storage means is accessed by an instruction control unit and stores data on the main memory in units of blocks, the write buffer means holds write access information to the main memory, and the data storage means Corresponding to each block of the means ~ first information indicating address information on the main storage device of the block data; second information indicating the case where the block data is stored in the data storage means; A third block data indicating a case where the block data corresponds to the access information registered in the write buffer means.
and an address information storage means for storing the information, and when block data including write data is not registered in the data storage means at the time of registering write access information to the write buffer means, the address information storage means stores the information. means for registering the first information and the third information corresponding to the block data; write access means for performing write access to the main storage device according to the contents of the write buffer means; and the write access means means for resetting the corresponding third information of the address information storage means during the operation of the address information storage means; is set, a buffer memory device is obtained which is characterized by comprising means for waiting for the third information to be reset and performing read access to the main storage device.Next. The present invention will now be described in detail with reference to the drawings.

A cache memory device 2, which is an embodiment of the present invention shown in FIG. A data storage unit 21 consisting of a data storage section 21 (which is configured by the cache memory) and its peripheral circuits, and a bit corresponding to each block of the cache memory that indicates the validity of the block data (that is, whether or not the block data is stored in the cache memory). A, a memory serving as an address information storage means for storing the address of the block data on the main storage device 3 and a valid bit B indicating whether the block data corresponds to the access information registered on the write buffer; (hereinafter referred to as an address array) and its peripheral circuit; a write buffer control unit 23 including a write buffer that holds write access information for the main memory 3; It is composed of a main memory access control section 24 that performs access control, and a selection circuit 22 that switches data from either the cache memory or the main memory device 3 and sends it to the instruction control section 1 upon a proposed access from the instruction control section 1. be done.

The instruction control unit 1 reads and executes instructions stored in the main storage device 3, and when an instruction or operand needs to be accessed from the main storage device 3, access information is placed on paths 100 and 101 and accessed. make a request.

In the case of read access, the address array of the address information storage control unit 20 is searched based on the address information of the main memory device 3 sent from the path 1001, and if the address is registered and the valid bit A is logic "1". If so, it indicates that the target data is stored on the cache memory (referred to as a cache hit), and the read data from the cache memory is sent to the instruction control unit 1 via the selection circuit 22.

When an address is registered on the address array and the valid bit B is logic “1”, it indicates that a write access is registered on the write buffer, and the valid bit B is reset from the write buffer control unit 23. After waiting for the corresponding valid bit B to be reset by the operation, it requests the access control unit 24 to request access to the main storage device 3.

If no address is registered on the address array, it immediately requests read access to the access control unit 24.

The path 107 is accessed from the main storage device 3 by the above read access.
When the proposal data is sent, the data is sent to the instruction control unit 1 via the selection circuit 22, the data is stored in the cache memory, and the address on the address array is set and the valid bit A is set.

In the case of write access from the instruction control unit 1, address information is sent from the path 10 and write data is sent from the path 101.

The address array is searched in the same way as in the case of proposed access using address information, and if there is a cache hit, the data stored in the cache memory is updated with the write data and the write access information is registered on the write buffer. do.

If data is not registered on the cache memory (referred to as a cache miss), address information is registered on the address array and its valid bit B is set to logic “1”.
” and registers the access information in the write buffer. At this time, bit E on the write buffer indicating that the address of the access is registered on the address array is set to logic “1”, and Information indicating a position on the address array is registered in bit LOC.

The write access information registered on the write buffer is F.
It is read using the IF○ (FirstInFshiptOut) method, and sends write access to the sender storage device to the access control unit 24.

The bit E read from the write buffer is logic “
1”, the write access and the bus 1
04 sends position information on the address array, and the valid bit B on the address array indicated by it is set to logic “
0''.Next, the operation of this embodiment will be explained in detail with reference to FIGS. 2 to 4.

FIG. 2 shows the configuration of the address array 30 and cache memory 50, and this cache memory is shown in the case of a four-level set associative system.

Each memory consists of 256 sets x 4 entries, and the address array 30 has a valid bit A for each entry.
The cache memory 50 is composed of a valid bit B and a bit for storing an address, and stores data. When valid bit A is logic ``1'', the address and data part are valid, and when valid bit B is logical ``1'', only the address part is valid.Valid bit A and valid bit B
is used by setting it exclusively. FIG. 3 shows the structure of the write buffer 60, which has an 8-word structure controlled by a FIFO.

Each word contains an access command for the main memory 3,
Access information consisting of main memory address - write data and a mark bit indicating the write byte position when specifying partial write, and bit E indicating that the address of the address array 3 is registered is logic "1" It has a bit LOC that indicates which position among the four blocks when . Valid bit B of address array 30 is logic “1”
At this time, bit E of the write buffer 60 is at logic "1". FIG. 4 is a block diagram showing the configuration of this embodiment shown in FIG. 1 in more detail.

In FIG. 4, the instruction control unit 1 sets the main memory address in register 13 and the access command in register 11 when requesting access, and sets the address in register 13 and the access command and mark bit information in register 1 during write access. Then, it also sets the write data in register 2 and requests access. In the case of a read access, the selection circuit 31 selects the lower bit 1002 of the address information in the register 13, and a read access to the address array 30 is performed via the path 201.

Each of the four blocks of input data 206, 207, 208 and 209 from address array 30 is compared with the upper bits 1001 of the address in hit detection circuit 36. In the hit detection circuit 36, for each of the four pieces of data from the address array 30, the valid bit A is logic "1" and the address and data 10
01 match, or valid bit B is logic “1”,
Also, it is checked whether the address and data 1001 match or whether the above-mentioned match cannot be obtained for all the data.

In parallel with this operation, address 1002 is used to control which block data is to be evicted among the four blocks when registering new data with the cache memory 50, and a memory that stores bits for placement control. 4
0 read access is being performed. If the valid bit A is logical "1" and both address data match, it means a cache hit, and the four block data 221, 222 extracted from the cache memory 50
, 223 and 224 is selected by the selection circuit 53, set in the register 54, and then passed through the selection circuit 22 and passed through the path 109 to the instruction control unit 1.
send to If the valid bit B is logic "1" and both address data match, it means that a write access request for the outside of the block data has been registered in the write buffer 6, and the write is performed using the address of path 231. The operation of the instruction control section 1 is stopped until the buffer control section 23 performs a rewrite access to the address array.

When an access from the write buffer control section 23 occurs, in the next cycle after the address array is rewritten, the address information from the instruction control section 1 causes access to the address array 30 and the hit detection circuit 3 to the same machine.
Perform the check in step 6.

In this check, if a match of the valid bit B being logic "1" is detected again, an access from the write buffer control section 23 is awaited again, and the same operation is repeated.

Effective bit B by rewriting the write buffer control unit 23
When the logic "1" no longer matches, the access command and address of the main memory device 3 from the instruction control unit 1 are selected by the selection circuits 75 and 72 of the main memory access control unit 24, respectively, and set in the registers 74 and 73. Thereafter, an access request is made to the main storage device 3. When the request data from the main storage device 3 is sent via the path 107 in response to this request, the data is sent to the instruction control unit 1 via the selection circuit 22 and sent from the selection circuit 51 to the register 52. and also writes it into the cache memory 50. At this time, the block position to be written is the address from the instruction control unit 1,
The block to be evicted is determined based on the contents of the IJ placement control bit in the memory 40, and the data from the main memory device is transferred to the cache memory 50 at the location of the block, and the address array 30' stores the data from the upper bits 1001 of the main memory address. Set valid bit A to logic "1" and valid bit B to logic "0". At this time, the contents of the memory 40 are also rewritten, but their operation is not related to the present invention and will therefore be omitted. If no match is detected in any block during access from the instruction control unit 1, the main storage device 3 is immediately accessed in the same way as described above.
Data is sent to the instruction control unit 1 and registered in the cache memory. In the case of a write access from the instruction control unit 1, the access information on paths 110, 101 and 100 is sent to the write buffer 6, and the word indicated by the register 61 with an adder indicating the input word position of this buffer is At the same time as writing to the location, the address array 30 is accessed using the address on path 1002 in the same way as in the access access, and the hit detection circuit 36 performs a match check.

When a match based on valid bit A is detected, the write data of pass 101 is also written to the hit block position of cache memory 50, and logic "0" is written to bit E of the write buffer by write pass 212. In cases other than the above, writing to the cache memory 50 is not performed, and the path 110,
The contents of 101, 100 and 212 are written to the write buffer 601 indicated by register 61.

At this time, path 212 has bit E of write buffer 60.
A logic "1" data is generated for the bit LOC, and a bit indicating the position of the block determined by the eviction block determining circuit 42 is generated by the circuit 37. Further, address information is written to the above-mentioned block position of the address array 30, logic "0" data is written to the valid bit A, and logic "1" data is written to the valid bit B.

When writing access information to the write buffer 60, the contents of the register 61 are incremented by 11. Register 62 is buffer 6
This register holds the word position for subtracting 0, and this register also has a 11 addition function. Based on the contents of the contents 235 and 236 of both registers, the buffer control circuit 63 detects that access information is held in the write buffer 60, and issues an access request to the main memory access control unit 24 asynchronously with the instruction control unit 1. Do the following.

If there is a read access request to the main storage device 3, the access control unit 24 processes it with priority, and if there is no request, the access control unit 24 stores the access information in the registers 74, 71 and 73 to perform write access to the main storage device 3.

When the write buffer control unit 23 makes a write access request, if bit E of the word is logic "1",
The lower bit 231 of the main memory address is designated as the address 201 of the address array 30 via the selection circuit 31, the contents of the bit DOC of the bus 230 are sent to the valid bit B control circuit 34, and the address array 30 indicated by the contents is Reset the valid bit B of the block to logic "0".

When a write access to block data outside the block data not registered in the cache memory 50 is registered in the write buffer 60 due to the above operation, when an argument request for that data is received from the instruction control unit 1, the main memory The logical access to 3 will be performed after the write access to the write buffer 60 is completed. As explained above, the present invention is configured so that the access information registered in the write buffer is registered on the address information storage means (address array), so that the access operation of the address information storage means at the time of a logical access is achieved. This has the effect that the function of guaranteeing the order of write and logical access to the same data in the main memory can be easily realized with a small amount of hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing the configuration of an address array 30 and cache memory 50 used in this embodiment, and FIG. 3 is a diagram showing the structure of a write buffer 60 used in this embodiment. FIG. 4 is a block diagram showing the detailed configuration of FIG. 1. In FIGS. 1 to 4, 1... command control unit, 2...
...Cache memory device, 3...Main storage device, 20
...Address information storage control unit, 21...Data storage section, 22...Selection circuit, 23...
Write buffer control unit, 24...Main memory access control unit, 30...Address array, 40...Memory,
50... Cache memory, 60... Write buffer, 11, 12, 13, 33, 35, 52, 54,
61, 62, 71, 73, 74...Register, 31, 5
1, 53, 72, 75...selection circuit, 32...
... Valid bit A control section, 35... Valid bit B control section, 36... Bit detection circuit, 37...
...Flock position creation circuit, 41...Rebracement memory control circuit, 42...Evicted block determination circuit, 63...Write buffer control circuit, 101-110, 1001, 1002 , 201-21
2,214~217,219~226,230~236
, 239, 241, 242, 1060-1062...
...Connection line. Figure 1 Figure 2 Figure 3 Ax diagram

Claims (1)

[Claims] 1. A data storage means that is accessed from the instruction control unit and stores data on the main memory in units of blocks, a write buffer means that retains write access information to the main memory, and each block of the data storage means. Correspondingly, first information indicating the address information of the block data on the main storage device, second information indicating the case where the block data is stored in the data storage means, and whether the block data is stored in the write address. and third information indicating that it corresponds to the access information registered in the buffer means.
address information storage means for storing, and when block data including write data is not registered in the data storage means at the time of registering write access information in the write buffer means, the address information storage means corresponds to the block data. means for registering the first information and the third information; write access means for performing write access to the main storage device according to the contents of the write buffer means; and write access means for registering the address information when the write access means operates. means for resetting the corresponding third information of the storage means; upon read access from the instruction control unit;
If the third information of the address information storage means corresponding to the read address is set, means for waiting for the third information to be reset and performing read access to the main storage device; A buffer memory device comprising: