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JPS607424B2 - Time division multidirectional multiplex synchronization circuit - Google Patents
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JPS607424B2 - Time division multidirectional multiplex synchronization circuit - Google Patents

Time division multidirectional multiplex synchronization circuit

Info

Publication number
JPS607424B2
JPS607424B2 JP16518979A JP16518979A JPS607424B2 JP S607424 B2 JPS607424 B2 JP S607424B2 JP 16518979 A JP16518979 A JP 16518979A JP 16518979 A JP16518979 A JP 16518979A JP S607424 B2 JPS607424 B2 JP S607424B2
Authority
JP
Japan
Prior art keywords
output
phase
voltage
circuit
carrier wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP16518979A
Other languages
Japanese (ja)
Other versions
JPS5687956A (en
Inventor
忠 岩田
一彦 関川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16518979A priority Critical patent/JPS607424B2/en
Publication of JPS5687956A publication Critical patent/JPS5687956A/en
Publication of JPS607424B2 publication Critical patent/JPS607424B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20Modulator circuits; Transmitter circuits
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/0014Carrier regulation
    • H04L2027/0016Stabilisation of local oscillators
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/0014Carrier regulation
    • H04L2027/0044Control loops for carrier regulation
    • H04L2027/0053Closed loops
    • H04L2027/0055Closed loops single phase
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/0014Carrier regulation
    • H04L2027/0044Control loops for carrier regulation
    • H04L2027/0063Elements of loops
    • H04L2027/0067Phase error detectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Time-Division Multiplex Systems (AREA)

Description

【発明の詳細な説明】 この発明は時分割多方向多重の同期系の構成に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the configuration of a time division multidirectional multiplexing synchronization system.

第1図は従来の装置の一例を示すブロック接続図であっ
て、1はPSK(位相シフトキーイング:phases
hiftkeying)変調器、2は周波数コンバータ
、3,4はそれぞれ搬送波の発振器でPSK変調器1、
周波数コンバータ2を駆動する。
FIG. 1 is a block connection diagram showing an example of a conventional device, in which 1 indicates PSK (phase shift keying).
(hiftkeying) modulator, 2 is a frequency converter, 3 and 4 are carrier wave oscillators, and PSK modulator 1,
Drives frequency converter 2.

1,2,3,4によって主局の送信系を構成する。1, 2, 3, and 4 constitute the transmission system of the main station.

また5,6はそれぞれスイッチ、7は電圧保持回路であ
るが電圧保持回路7は一つの従局に対しそれぞれ一つあ
て設けられ、スイッチ5,6は主局に対し時分割によっ
て順次通話している従局の切換に同期して当該従局に対
する電圧保持回路7が位相比較器10と電圧制御発振器
8との間に接続されるように切換る。8は電圧制御発振
器、9は搬送波の発振器、10‘ま位相比較器、11は
搬送波再生回路、12はPSK復調器、13はミキサで
位相比較器10、スイッチ5,6、電圧保持回路7によ
って電圧制御発振器8の出力周波数の位相を搬送波再生
回路11の出力位相に位相同期する。
Also, 5 and 6 are switches, respectively, and 7 is a voltage holding circuit. One voltage holding circuit 7 is provided for each slave station, and the switches 5 and 6 communicate with the main station sequentially by time division. In synchronization with the switching of the slave station, the voltage holding circuit 7 for the slave station is switched to be connected between the phase comparator 10 and the voltage controlled oscillator 8. 8 is a voltage controlled oscillator, 9 is a carrier wave oscillator, 10' is a phase comparator, 11 is a carrier wave regeneration circuit, 12 is a PSK demodulator, 13 is a mixer, and is controlled by the phase comparator 10, switches 5 and 6, and voltage holding circuit 7. The phase of the output frequency of the voltage controlled oscillator 8 is synchronized with the output phase of the carrier wave regeneration circuit 11.

5,6,7,8,9,10,11,12,13によって
主局の受信系を構成する。また第1図において14,1
5,16,17,18,19は各従局の受信系を示し、
20,21,22,23,24は各従局の送信系を示し
一つの主局に対し複数個の従局が存在するが第1図には
従局一局分の回路だけを示す。
5, 6, 7, 8, 9, 10, 11, 12, and 13 constitute the receiving system of the main station. Also, in Figure 1, 14,1
5, 16, 17, 18, 19 indicate the receiving system of each slave station,
Reference numerals 20, 21, 22, 23, and 24 indicate the transmission systems of each slave station, and although there are a plurality of slave stations for one master station, only the circuit for one slave station is shown in FIG.

14はミキ/サ、15はPSK復調器、16は搬送波の
発振器「17は電圧制御発振器、18は搬送波再生回路
、19は位相比較器、2川まスイッチ、21は周波数コ
ンバータ、22はPSK変調器「 23,2Mまそれぞ
れ搬送波の発振器である。
14 is a mixer/server, 15 is a PSK demodulator, 16 is a carrier wave oscillator, 17 is a voltage controlled oscillator, 18 is a carrier wave regeneration circuit, 19 is a phase comparator, a two-way switch, 21 is a frequency converter, and 22 is a PSK modulator. 23 and 2M are respectively carrier wave oscillators.

また第1図においてA〜川ま説明の便宜のため用いる記
号であって各導線上の信号を示す。次に動作について説
明する。
Further, in FIG. 1, symbols A to C are used for convenience of explanation and indicate signals on each conducting wire. Next, the operation will be explained.

信号Aはディジタル信号であって、PSK変調器1にお
いて発振器3からの出力に対しPSK変調を行なう。発
振器3の出力電圧をたとえばRcos(山,t十め,)
で表すと、2相PSK変調では信号Aの論理「0ハ「1
」に従って上記の位相少,を00,1800にPSK変
調し、4相PSK変調では信号Aの論理「00」「「0
1」、「10」、「11」に従って位相め,を00ヂ9
007 1800,2700にPSK変調する。実際の
FSK変調の場合、4相以上の多相PSK変調も用いら
れるが「以下の記述においては説明の便宜のため2相P
SK変調について説明する。cos(の,t十180o
)=−cos(■,t十oo)であるからPSK変調器
1の出力信号S,(t)をS,(t)=仏(t)・co
s(の.t+○,)……【1}で表すことができる。
Signal A is a digital signal, and PSK modulation is performed on the output from oscillator 3 in PSK modulator 1 . For example, let the output voltage of the oscillator 3 be R cos (mountain, t tenths,)
Expressed as follows, in two-phase PSK modulation, the logic of signal A is “0”
”, the above phase is PSK modulated to 00,1800, and in 4-phase PSK modulation, the logic of signal A is “00” “0
1”, “10”, “11”, the phase is 00も9
007 PSK modulated to 1800, 2700. In actual FSK modulation, polyphase PSK modulation with four or more phases is also used, but in the following description, for convenience of explanation, two-phase PSK modulation is used.
SK modulation will be explained. cos(of,t180o
)=-cos(■, t0oo), so the output signal S, (t) of PSK modulator 1 is S, (t)=French (t)・co
s(.t+○,)... can be expressed as [1}.

ここに仏(t)は信号Aの論理が「0」のとき十1、信
号Aの論理が「1」のとき−1とする。S,(t)の振
幅は一般には1ではないが、1に基準化して考える。(
以下すべての信号の振幅を1に基準化して考える。)デ
ィジタル信号Aと発振器3の出力電圧Rcos(■,t
十◇,)とから信号S,(t)を得る回路としてはたと
えばリング変調器が用いられる。周波数コンバータ2,
21、ミキサ13,14、PSK変調器22に対しても
たとえばリング変調器が用いられる。信号S,(t)は
周波数コンバータ2において発振器4により周波数変換
され、周波数コンバータ2の出力信号BはS,(t)=
り(t)・cos(山2t+◇2)・…・・■となる。
Here, the value (t) is 11 when the logic of the signal A is "0", and -1 when the logic of the signal A is "1". Although the amplitude of S,(t) is generally not 1, it is considered as being normalized to 1. (
In the following, the amplitudes of all signals will be normalized to 1. ) digital signal A and the output voltage R cos of the oscillator 3 (■, t
For example, a ring modulator is used as a circuit for obtaining the signal S, (t) from ◇, ). frequency converter 2,
21, mixers 13 and 14, and PSK modulator 22, for example, ring modulators are used. The signal S,(t) is frequency-converted by the oscillator 4 in the frequency converter 2, and the output signal B of the frequency converter 2 is S,(t)=
ri(t)・cos(mountain 2t+◇2)・・・・・■.

ここに発振器4はの2 −の・,ぐ2−中,の角周波数
及び位相で発振しているものとする。信号Bが通信路を
経て子局で受信され信号Cとなりミキサー14において
発振器16により周波数変換され、ミキサ14の出力信
号S3(t)はSI(t)白舷(t),COS(の3t
+?3).・・.・・【3’となる。
Here, it is assumed that the oscillator 4 is oscillating at an angular frequency and phase of 2-1, 2-, and 2-. Signal B is received by the slave station via the communication channel and becomes signal C, which is frequency-converted by the oscillator 16 in the mixer 14, and the output signal S3(t) of the mixer 14 is SI(t), whiteboard(t), COS(3t)
+? 3).・・・. ...[It becomes 3'.

ここに発振器16はの3一の2,ぐ3一心2の角周波数
及び位相で発振しているものとする。搬送波再生回路1
8では信号S3(t)から搬送波を再生するが、信号S
3(t)をそのままフィル夕に加えたのでは搬送波を抽
出するこができない。
Here, it is assumed that the oscillator 16 is oscillating at an angular frequency and phase of 31-2, 3-3 and 2. Carrier wave regeneration circuit 1
8, the carrier wave is regenerated from the signal S3(t), but the signal S
If 3(t) is directly added to the filter, the carrier wave cannot be extracted.

その理由は先に述べたように仏(t)は十1又は−1と
なり十1となる頻度と−1となる頻度とは長い時間の間
では同一であり、したがって仏(t)の時間平均値仏(
t)は通常は零になると考えられるからである。このこ
とは4相変調の場合も位相が00となる頻度と1800
となる頻度は等しく90oとなる頻度と270oとなる
頻度は等しいので同様に振幅の時間平均値は零になると
考えられる。したがって搬送波再生回路18ではS旨(
t)の信号を作りこれから搬送波を抽出する。すなわち
S室(t)=仏2(t)・COS2(の3t+で3)=
仏2(t){cos(2の3t+2少3)十1}/2
…・・・【4}となり山2(t
)は常に正で仏2(t)の時間平均値は0にはならない
から信号S妻(t)からcos(2の3t+203 )
の搬送波をフィル夕で取り出すことができる。
The reason for this is that as mentioned earlier, Buddha (t) becomes 11 or -1, and the frequency of 11 and -1 are the same over a long period of time, so the time average of Buddha (t) Value Buddha (
This is because t) is usually considered to be zero. This means that in the case of four-phase modulation, the frequency of the phase being 00 and the frequency of 1800
Since the frequencies of 90o and 270o are the same, it can be considered that the time average value of the amplitude becomes zero in the same way. Therefore, in the carrier regeneration circuit 18, S (
t) and extract the carrier wave from it. In other words, S chamber (t) = Buddha 2 (t) / COS 2 (3 at 3t +) =
Buddha 2 (t) {cos (2 3t + 2 less 3) 11}/2
......[4} and mountain 2 (t
) is always positive and the time average value of 2(t) never becomes 0, so the signal S(t) to cos(2 of 3t+203)
The carrier wave can be extracted using a filter.

搬送波再生回路18ではこうして取り出したcos(2
の3t十203 )の搬送波を2分の1分周してcos
(の3t+で3 )の搬送被を得ている。ところで通信
路等において混入する雑音が信号S3(t)に加わって
いるので、搬送波再生回路18で抽出した搬送波には雑
音によるスプーリアス成分を含んでいる。
In the carrier regeneration circuit 18, the cos(2
The frequency of the carrier wave of 3t + 203
(3t+ = 3) of conveyed objects are obtained. By the way, since noise mixed in the communication path etc. is added to the signal S3(t), the carrier wave extracted by the carrier wave regeneration circuit 18 includes spurious components due to the noise.

このスプーリアス成分を除去するため電圧制御発振器1
7の発振周波数を位相比較器19を介し搬送波再生回路
18の出力により位相同期する。この位相比較器19を
含むAPC(自動位相制御)ループの低域通過フィルタ
作用により搬送波再生回路18の出力に含まれるスプー
リアス成分は電圧制御発振器17の制御電圧としては到
達しないので、電圧制御発振器17の出力は純度の高い
正弦波となる。PSK復調器15においては同期検波が
行われ、その出力信号DはS3(t)・COS(■3t
+で3 )=し(t)・COS2(の3t十○3){1
十C○S(2の3t十2ぐ3 )}/2 ニ仏(t)と
なり低域通過フィル夕を通して仏(t)を抽出する。
In order to remove this spurious component, the voltage controlled oscillator 1
The oscillation frequencies of 7 are phase-synchronized with the output of the carrier wave regeneration circuit 18 via the phase comparator 19. Due to the low-pass filtering effect of the APC (automatic phase control) loop including this phase comparator 19, the spurious component contained in the output of the carrier wave regeneration circuit 18 does not reach the control voltage of the voltage controlled oscillator 17. The output is a highly pure sine wave. Synchronous detection is performed in the PSK demodulator 15, and its output signal D is S3(t)・COS(■3t
+3)=shi(t)・COS2(3t10○3){1
1C○S (2 of 3t 12gu3)}/2 becomes 2 Buddhas (t), and extracts Buddha (t) through a low-pass filter.

PSK変調器22、周波数コンバータ21、発振器24
,23の動作はそれぞれPSK変調器1、周波数コンバ
ータ2、発振器3,4の動作と同一であり、スイッチ2
川ま従局の時分割送信において自局に割当てられた時間
だけ信号を伝送する。
PSK modulator 22, frequency converter 21, oscillator 24
, 23 are the same as those of the PSK modulator 1, frequency converter 2, and oscillators 3 and 4, respectively.
In time-division transmission, the slave station transmits signals only during the time allotted to its own station.

主局の受信系におけるミキサ13、発振器9、搬送波再
生回路11、位相比較器10、電圧制御発振器8、PS
K復調器12の動作はそれぞれミキサー4、発振器16
、搬送波再生回路18、位相比較器19、電圧制御発振
器17、PSK復調器15の動作と同一であるが、ただ
主局においては複数個の従局からの送信を受信して復調
するためスイッチ5,6と電圧保持回路7とを備えてい
る。電圧保持回路7は各従局用のものがそれぞれ1個あ
て備えられ、当該従局に対する受信をしている期間その
従局用の電圧保持回路7がスイッチ5,6により位相比
較器10の出力と電圧制御発振器8の入力との間に接続
され、当該従局に対する受信が終了し他の従局に対する
受信が開始されるとスイッチ5,6によって切りはなさ
れて当該従局に対する位相比較器10の出力を記憶して
おり、次に当該従局に対する受信が再開されるとそれに
対応する電圧保持回路7に記憶されている電圧によって
電圧制御発振器8の制御を開始する。ところで、電圧保
持回路7に記憶されている電圧によって電圧制御発振器
8を制御するので、一つの従局から別の従局に切換わる
際、周波数は正しく制御されても位相誤差が存在するの
で、位相比較器10、電圧保持回路7、電圧制御発振器
8によって構成される位相同期ループは高速で引き込み
動作をするよう設計しなければならないが、高速で引き
込み動作をするためには位相同期ループのループ利得を
高い周波数領域まで拡げておかねばならず、そうすると
雑音を抑圧することができないので、実際の回路の設計
が困難になるという欠点があった。この発明は上記のよ
うな従来のものの欠点を除去するためになされたもので
、主局と全従局を含めすべての搬送波を同期系とし主局
においては露圧制御位相変調回路を電圧保持回路を用い
て制御することによって引込み動作を不必要にしたもの
で、多方向多重に通した搬送波再生回路を提供すること
を目的としている。
Mixer 13, oscillator 9, carrier wave regeneration circuit 11, phase comparator 10, voltage controlled oscillator 8, PS in the receiving system of the main station
The operation of the K demodulator 12 is the mixer 4 and the oscillator 16, respectively.
, the carrier wave regeneration circuit 18, the phase comparator 19, the voltage controlled oscillator 17, and the PSK demodulator 15. However, in the main station, in order to receive and demodulate transmissions from a plurality of slave stations, the switch 5, 6 and a voltage holding circuit 7. One voltage holding circuit 7 is provided for each slave station, and during reception for that slave station, the voltage holding circuit 7 for that slave station controls the output of the phase comparator 10 and the voltage by switches 5 and 6. It is connected between the input of the oscillator 8, and when reception for that slave station ends and reception for another slave station starts, it is disconnected by switches 5 and 6, and the output of the phase comparator 10 for the slave station is stored. Then, when reception to the slave station is resumed, control of the voltage controlled oscillator 8 is started using the voltage stored in the corresponding voltage holding circuit 7. By the way, since the voltage controlled oscillator 8 is controlled by the voltage stored in the voltage holding circuit 7, when switching from one slave station to another, even if the frequency is controlled correctly, there is a phase error, so phase comparison is necessary. The phase-locked loop composed of the voltage control circuit 10, the voltage holding circuit 7, and the voltage-controlled oscillator 8 must be designed to perform a high-speed pull-in operation. This has the disadvantage that it has to be extended to a high frequency range, and then noise cannot be suppressed, making it difficult to design an actual circuit. This invention was made to eliminate the above-mentioned drawbacks of the conventional system, and all carrier waves including the main station and all slave stations are synchronized, and the main station is equipped with an exposure pressure control phase modulation circuit and a voltage holding circuit. The purpose of the present invention is to provide a carrier wave regeneration circuit that can perform multi-directional multiplexing, thereby eliminating the need for a pull-in operation.

以下この発明の一実施例を図について説明する。An embodiment of the present invention will be described below with reference to the drawings.

第2図はこの発明の一実施例を示すブロック接続図であ
って、第1図と同一符号は同一又は相当部分を示すが、
ただ発振器4,9は発振器3の出力により制御されこれ
によって位相同期され、発振器16,29は電圧制御発
振器17の出力により制御されこれによって位相同期さ
れる。この意味で発振器3を主発振器という。また25
は電圧制御位相変調回路である。第2図の回路において
も信号の変換過程は第1図の回路におけると同様である
のでその説明を省略する。
FIG. 2 is a block connection diagram showing an embodiment of the present invention, and the same reference numerals as in FIG. 1 indicate the same or corresponding parts.
However, oscillators 4 and 9 are controlled by the output of oscillator 3 and are phase-locked thereby, and oscillators 16 and 29 are controlled by and phase-locked by the output of voltage-controlled oscillator 17. In this sense, the oscillator 3 is called the main oscillator. 25 again
is a voltage controlled phase modulation circuit. Since the signal conversion process in the circuit shown in FIG. 2 is the same as that in the circuit shown in FIG. 1, its explanation will be omitted.

発振器3,4,9,16,17,23の出力周波数をそ
れぞれf3,L,,f9,f,6,f,7,f23とし
、L;k,f3,f,6=k,f,?のように選んでお
けば信号Bの周波数はたとえばf4十もとなり、ミキサ
14の出力周波数はf4十f3−f,6となるが、位相
比較器19と電圧制御発振器17とで構成する位相同期
ループによってf4十f3−f,6=f,7となり、f
4十ら=f.7十f.6,(1十k.)f3=(1十k
.)f,7からf3=f,7となり、上記位相同期ルー
プのループ利得を大きくしておけば、位相比較器19の
両入力の位相差が小さくなる。またら3=k2f,7,
ら:k2f3のように選んでおけばミキサ13の出力周
波数はf,7+ら3−f9となるがf,7=f3である
からf,7十f23−f9=f3となり発振器3の出力
周波数と一致する。
Let the output frequencies of oscillators 3, 4, 9, 16, 17, and 23 be f3, L,, f9, f, 6, f, 7, and f23, respectively, and L;k, f3, f, 6=k, f,? If selected as follows, the frequency of the signal B will be f40, for example, and the output frequency of the mixer 14 will be f40 f3-f,6. Through the loop, f4 + f3-f,6=f,7, and f
40 et al. = f. 70f. 6, (10k.) f3 = (10k
.. ) from f,7, f3=f,7, and if the loop gain of the phase-locked loop is increased, the phase difference between both inputs of the phase comparator 19 becomes smaller. Also 3=k2f,7,
If selected as: k2f3, the output frequency of the mixer 13 will be f,7+3-f9, but since f,7=f3, f,7+f23-f9=f3, and the output frequency of the oscillator 3. Match.

したがって位相比較器10の両入力の周波数は同一とな
り、第1図の回路のように位相比較器10の出力により
発振周波数を制御する必要はなくなる。すなわち第2図
の回路では位相比較器10の出力によって電圧制御位相
変調回路25を制御する。電圧制御位相変調回路25と
位相比較器10とによって構成するフィ−ドバツク制御
ループのループ利得を大きくして位相比較器10の両入
力の位相誤差を4・さくする。スイッチ5,6と電圧保
持回路7の動作は第1図の場合と同じであるが、電圧保
持回路7に保持される電圧は前に当該従局を受信してい
たとき電圧制御位相変調回路25の制御電圧として加え
られその出力の位相を搬送波再生回路11の出力位相と
ほぼ等しくするよう制御していた電圧であるから、その
同じ従局を再び受信するときこの電圧をスイッチ5,6
を介して電圧制御位相変調回路25に加えれば、切換わ
り時点での引込み動作を行わないでも電圧制御位相変調
回路25の出力位相はそのときの搬送波再生回路11の
出力位相とほとんど同一となりPSK復調回路12にお
いて信頼度の高い復調をすることができる。
Therefore, the frequencies of both inputs of the phase comparator 10 are the same, and there is no need to control the oscillation frequency by the output of the phase comparator 10 as in the circuit shown in FIG. That is, in the circuit shown in FIG. 2, the voltage control phase modulation circuit 25 is controlled by the output of the phase comparator 10. The loop gain of the feedback control loop constituted by the voltage controlled phase modulation circuit 25 and the phase comparator 10 is increased to reduce the phase error between both inputs of the phase comparator 10 by 4. The operations of the switches 5 and 6 and the voltage holding circuit 7 are the same as in the case of FIG. This voltage is applied as a control voltage and is controlled so that the phase of its output is almost equal to the output phase of the carrier wave regeneration circuit 11. Therefore, when receiving the same slave station again, this voltage is applied to the switches 5 and 6.
If it is applied to the voltage controlled phase modulation circuit 25 via the voltage controlled phase modulation circuit 25, the output phase of the voltage controlled phase modulation circuit 25 will be almost the same as the output phase of the carrier wave regeneration circuit 11 at that time, even if no pull-in operation is performed at the switching point, resulting in PSK demodulation. Demodulation with high reliability can be performed in the circuit 12.

以上のように、この発明によれば時分割多方向多重の従
局の切換わり時点での位相同期引込み動作の必要性をな
くすることができて、PSK復調における同期検波の場
合の信頼度を格段に向上することができる。
As described above, according to the present invention, it is possible to eliminate the need for a phase synchronization pull-in operation at the time of switching of slave stations in time division multidirectional multiplexing, and the reliability in the case of coherent detection in PSK demodulation is greatly improved. can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の装置の一例を示すブロック接続図L第2
図はこの発明の一実施例を示すブロック接続図である。 図において1,22はそれぞれPSK変調器、2,21
はそれぞれ周波数コンバータ、3は主発振器、4,9,
16,23はそれぞれ搬送波の発振器、5,6はそれぞ
れスイッチ、7は電圧保持回路、10,19はそれぞれ
位相比較器、11,18はそれぞれ搬送波再生回路、1
2,15はそれぞれPSK復調器、13,14はそれぞ
れミキサ、17は電圧制御発振器である。なお各図中同
一符号は同一又は相当部分を示す。第1図 第2図
Figure 1 is a block connection diagram L2 showing an example of a conventional device.
The figure is a block connection diagram showing one embodiment of the present invention. In the figure, 1 and 22 are PSK modulators, 2 and 21 respectively.
are frequency converters, 3 is the main oscillator, 4, 9,
16 and 23 are carrier wave oscillators, 5 and 6 are switches, 7 is a voltage holding circuit, 10 and 19 are phase comparators, respectively, 11 and 18 are carrier wave regeneration circuits, and 1
2 and 15 are PSK demodulators, 13 and 14 are mixers, and 17 is a voltage controlled oscillator. Note that the same reference numerals in each figure indicate the same or equivalent parts. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1 主局と複数の従局との間に時分割多方向通信路を構
成する場合の上記主局に設けられる主発振器と、上記主
局内で用いられるすべての搬送波を上記主発振器の出力
周波数に対し位相同期する手段と、上記各従局に設けら
れる電圧制御発振器と、上記各従局において上記主局か
らの送信を受信してその受信出力から搬送波を再生する
搬送波再生回路と、この搬送波再生回路の出力により上
記電圧制御発振器の出力周波数の位相を同期する位相同
期ループと、上記各従局内で用いられるすべての搬送波
を上記電圧制御発振器の出力周波数に対し位相同期する
手段と、上記主局において上記主発振器の出力を入力し
調整可能な移相量を与えて出力する電圧制御位相変調回
路と、上記主局において上記各従局からの送信を受信し
てその受信出力から搬送波を再生する搬送波再生回路と
、この搬送波再生回路の出力と上記電圧制御位相変調回
路の出力との位相差を検出する位相比較器と、この位相
比較器の出力により上記電圧制御位相変調回路をフイー
ドバツク制御する手段と、各従局送信に対する位相比較
器の出力を各従局別に記憶する電圧保持回路と、一つの
従局からの送信を受信中は当該従局に対応する電圧保持
回路を介し上記位相比較器の出力を上記電圧制御位相変
調回路に加えるスイツチとを備えたことを特徴とする時
分割多方向多重同期回路。
1 When a time-division multidirectional communication path is configured between a main station and multiple slave stations, the main oscillator installed in the main station and all carrier waves used within the main station are set to the output frequency of the main oscillator. means for phase synchronizing, a voltage controlled oscillator provided in each of the slave stations, a carrier wave regeneration circuit for receiving transmission from the master station in each of the slave stations and regenerating a carrier wave from the received output, and an output of the carrier wave recovery circuit. a phase-locked loop for synchronizing the phase of the output frequency of the voltage-controlled oscillator, means for phase-synchronizing all carrier waves used in each of the slave stations with the output frequency of the voltage-controlled oscillator; a voltage-controlled phase modulation circuit that inputs the output of the oscillator, gives an adjustable phase shift amount, and outputs the output; and a carrier wave regeneration circuit that receives transmissions from each of the slave stations in the main station and reproduces a carrier wave from the received output. , a phase comparator for detecting a phase difference between the output of the carrier wave regeneration circuit and the output of the voltage-controlled phase modulation circuit, means for feedback-controlling the voltage-controlled phase modulation circuit using the output of the phase comparator, and each slave station. A voltage holding circuit stores the output of the phase comparator for transmission for each slave station, and when a transmission from one slave station is being received, the output of the phase comparator is subjected to the voltage control phase modulation via the voltage holding circuit corresponding to that slave station. A time division multidirectional multiplex synchronization circuit characterized by comprising a switch added to the circuit.
JP16518979A 1979-12-18 1979-12-18 Time division multidirectional multiplex synchronization circuit Expired JPS607424B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16518979A JPS607424B2 (en) 1979-12-18 1979-12-18 Time division multidirectional multiplex synchronization circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16518979A JPS607424B2 (en) 1979-12-18 1979-12-18 Time division multidirectional multiplex synchronization circuit

Publications (2)

Publication Number Publication Date
JPS5687956A JPS5687956A (en) 1981-07-17
JPS607424B2 true JPS607424B2 (en) 1985-02-25

Family

ID=15807522

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16518979A Expired JPS607424B2 (en) 1979-12-18 1979-12-18 Time division multidirectional multiplex synchronization circuit

Country Status (1)

Country Link
JP (1) JPS607424B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60183861A (en) * 1984-03-02 1985-09-19 Fujitsu Ltd Burst signal compensating circuit
CN111198532B (en) * 2020-01-20 2021-06-22 北京韬盛科技发展有限公司 A time-division multiplexing cross-start-stop system and its control method

Also Published As

Publication number Publication date
JPS5687956A (en) 1981-07-17

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