JPS608553B2 - MIS type semiconductor memory device - Google Patents

Description

[Detailed description of the invention] The present invention relates to an MIS type semiconductor memory device.

Generally used as a skin S-type semiconductor memory device is a pair of memory cells for transmitting true and bar signals to each column of memory cells arranged in a matrix, as shown in FIGS. 4a and 4b. Digit line D・、DL・、Dshi2、DL
It is made by arranging 2. In the case shown in Figure a, all memory cells belonging to a row selected by word signals X, , X2 (row selection signal) are connected to a digit line.
Consumes electricity. On the other hand, in the case shown in Figure b', only one memory cell selected by the word signal and the Y (column) selection signal is connected to the digit line. “On the other hand,
Compared to a in the same figure, two more MISFETs are required for each memory cell, and the area occupied by the memory cell becomes larger.
This has the disadvantage that the overall chip size becomes large. Therefore, an object of the present invention is to eliminate unnecessary power consumption without increasing the chip size.

One embodiment of the present invention for achieving the above object is a flip-flop, a MISFE driven by a row selection signal.
In a MIS type semiconductor memory device in which memory cells configured with T are arranged in a matrix, the outputs of a plurality of memory cells selected by a row selection signal are selectively sent to one digit line arranged in a column direction. The device is characterized in that it has a MISFET driven by a column selection signal that is extracted as a signal.

Another embodiment of the present invention is a "flip-flop" in which memory cells each composed of a pair of MSFETs driven by a column selection signal and a MISFET driven by a row selection signal are arranged in a matrix, and In an MIS type semiconductor memory device in which a flip-flop in one memory cell specified by a column selection signal and a column selection signal is electrically connected to a digit line in a column direction via the MISFET, an adjacent one of the digit lines For those located between rows, place only one book at a time,
The device is characterized in that each digit line arranged between columns is used as an electrical connection means between memory cells belonging to columns on both sides and a common data line.

In another embodiment of the present invention, memory cells each including a flip-flop, a pair of MISFETs driven by a column selection signal, and a MISFET driven by a row selection signal are arranged in a matrix, and the flip-flops in one memory cell are arranged in a matrix. The digit lines are electrically connected to the digit lines in the column direction through the MISFETs, and the digit lines located between adjacent digit lines are arranged one by one, and a voltage is applied when selecting a memory cell. The digit lines on both sides of the selected column are electrically connected to a pair of common data lines through MISFETs controlled by the selected column selection signal.

Yet another embodiment of the present invention is to connect a plurality of memory cells in the row direction, each consisting of a flip-flop and a pair of MISFETs connected to both terminals thereof and driven by a column selection signal, and further provide a plurality of columns. The memory cell array is configured in a matrix, and one digit line is arranged for each digit line located between adjacent columns in the column direction, and each connection point between memory cells connected in the row direction is The flip-flop in the memory cell is electrically connected to the digit line through a single SFET driven by a row selection signal, which is connected one by one to the digit line.

The present invention will be explained below with reference to Examples.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

M.S. ．． ~MS3.4 are memory cells, respectively.

Taking MSM as an example, the explanation is as follows. R, is a load resistance, and M, is a drive skin SFET, both of which constitute one inverter, and the load resistance R2 and drive MIS.
It is cross-connected to an inverter made up of FETs to form a flip-flop. M3, M are MISFETs driven by column selection signal Y, M5, M
6 is a MISFET driven by the row selection signal X. MISFETs M42 to M4 are used to precharge the digit lines DL and DL5.

o connects the digit line DL to the common data line (Common
This is a MISFET for connecting to the DataLine. In this memory cell array, instead of arranging a pair of digit lines DL and DL for each column as in the conventional case, only one digit line is arranged between memory cells in each column. , when it is one digit line, the right memory cell and the common data line are connected, and when there are other digit lines, the left memory cell and the common data line are connected. For example, focusing on digit line DL2, if the first column (Y,) is selected, M42
At the same time, M43 is turned on, and OL, is connected to one of the common data lines through M42 to transmit, for example, a true signal, while DL2 is connected to the other common data line through M43, and transmits, for example, a bar signal. do.

When the second column (Y2) is selected, M44 as well as M45 are turned on, and DL3 is connected to one side of the common data line through M Street to transmit, for example, a toru signal, while DL2 is connected to the ground is connected to the other common data line through the common data line to transmit the bar signal. In this way, when there is one digit line, the memory cell on the left side is connected to the common data line, and when there is another digit line, the memory cell on the right side is connected to the common data line, so the number of digit lines is It only takes about half of the conventional cost. Therefore, the area occupied by the memory cell array can be made smaller than in the circuit shown in FIG. 4b. Of course, there is no disadvantage that wasteful power consumption as shown in FIG. 2a occurs in the digit line of only one memory cell specified by the X selection signal. FIG. 2 is a waveform diagram showing the x selection signal, the Y selection signal, and the digit line readout signal. FIG. 3 is a circuit diagram showing an embodiment in which the area occupied by the memory cell array is made smaller.

This allows memory cells to be connected in the row direction without intervening MISFETs driven by an
They are connected via one MISFET driven by a selection signal.

When this embodiment is compared with the embodiment shown in FIG.
The number of T's is the same. This is for example M6 and M, . . . in the embodiment shown in FIG. This is because, in this embodiment, one MISFET M6 is used for both of the two MISFETs. Therefore, according to this embodiment, not only the number of digit lines is reduced by almost half, but also the number of MISFETs is reduced by one per memory cell, so that the circuit occupies almost the same area as the circuit shown in FIG. 4a. Similarly to FIG. 4b, wasteful power consumption can be eliminated. As explained above, according to the present invention, wasteful power consumption can be eliminated without increasing the occupied area, and it is extremely effective. Although each of the above embodiments uses a resistor as a load means for a flip-flop constituting a memory cell, it goes without saying that the present invention can also be applied to an MISFET as a load means.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a time chart thereof, and FIG. 3 is a circuit diagram showing another embodiment of the present invention. It is a circuit diagram showing M, ~M5o... R to MISFET, ~R, 2
·…··resistance. Departure diagram Younger brother Z diagram Younger brother 3 diagram Younger brother I diagram

Claims (1)

[Claims] 1. A flip-flop, a pair of MISFETs driven by a column selection signal, and an MI driven by a row selection signal.
Memory cells composed of SFETs are arranged in a matrix, and a flip-flop in one memory cell specified by a row selection signal and a column selection signal is connected to the above-mentioned MISF.
In a MIS type semiconductor memory device which is electrically connected to digit lines in the column direction via ET, only one digit line is arranged between adjacent columns among the digit lines. A MIS type semiconductor memory device characterized in that each digit line arranged between the digit lines is used as an electrical connection means between memory cells belonging to columns on both sides and a common data line. 2 flip-flop, a pair of MISFETs driven by the column selection signal and a pair of MISFETs driven by the row selection signal.
Memory cells configured with SFETs are arranged in a matrix, and a flip-flop in one memory cell is electrically connected to a digit line in the column direction via the MISFET, and one of the adjacent digit lines The digit lines on both sides of the selected column are electrically connected to a pair of common data lines through MISFETs that are controlled by the column selection signal applied when selecting a memory cell. 1. An MIS type semiconductor memory device, characterized in that the MIS type semiconductor memory device is connected to each other. 3 A pair of MISFETs driven by a column selection signal connected to a flip-flop and its pair of input/output terminals
A memory cell array is formed in a matrix by connecting a plurality of memory cells in the row direction and further providing a plurality of columns, and one digit line in the column direction located between adjacent columns. The memory cells are arranged in rows and driven by a row selection signal connected to each connection point between memory cells connected in the row direction.
A MIS type semiconductor memory device characterized in that a flip-flop in a memory cell and a digit line are electrically connected through an ISFET.