JPS608624B2 - Manufacturing method of semiconductor device - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method suitable for manufacturing a semiconductor device in which the base, emitter, or source and drain are formed shallowly in order to increase the speed. Generally, as a means to increase the speed of semiconductor devices such as bipolar or MIS, it is practiced to form base emitters, sources, drains, etc. shallowly. Additionally, aluminum (
It is known that when using AI) electrodes, silicon and aluminum react and the aluminum penetrates into regions of the silicon bulk, causing various problems. For example, aluminum used as an emitter electrode may penetrate the emitter region and reach the base region, causing a so-called E-B short circuit. Such accidents are
As mentioned above, it is natural that the shallower the base emitter, etc., the more likely it is to occur. Therefore, in high-speed semiconductor devices such as those mentioned above, chemical vapor deposition (CVD) is used to form each electrode window.
It is said to be effective to form a polycrystalline silicon layer by applying a vapor deposition method, a sputtering method, etc., and then form an electrode thereon. For example, in the case of a bipolar semiconductor device,
A polycrystalline silicon layer containing an impurity of the same conductivity type as the impurity forming the emitter region may be interposed below the emitter electrode, or a polycrystalline silicon layer containing no impurities may be formed and the polycrystalline silicon layer may be formed later. Methods such as diffusing impurities into the silicon layer are being explored. By the way, when the base emitter etc. become shallower, the E-B due to the emitter electrode becomes smaller.
Not only short circuits but also base-collector short circuits due to the base electrode are becoming a problem. Therefore, it is necessary to interpose a polycrystalline silicon layer under the base electrode, but since the emitter region and the base region have different conduction types,
Introducing impurities into the polycrystalline silicon layer formed thereon becomes extremely troublesome. In such a case, although it is not impossible unless an increase in the number of manufacturing steps is avoided, it will lead to a decrease in the performance of the semiconductor device, a worsening of the manufacturing process, and the like. An object of the present invention is to make it possible to form an impurity-containing polycrystalline silicon layer in the same process at least on electrode contact windows in the emitter region and base region, and if necessary on electrode contact windows in other regions, (1) An electrode contact window is formed in the insulating film covering the surface of the semiconductor layer or semiconductor substrate in which various impurity regions are formed, and then a polycrystalline silicon layer is formed covering at least the interior of the window, and then heat treatment is performed to A method for manufacturing a semiconductor device, comprising a step of making the polycrystalline silicon layer conductive by causing impurities to creep up from the impurity region into the polycrystalline silicon layer, (2) making the polycrystalline silicon layer conductive. The method for manufacturing a semiconductor device according to item 1, which includes the steps of forming an aluminum layer on a polycrystalline silicon layer and performing heat treatment to react a part of the polycrystalline silicon layer with aluminum; This will be explained in detail below. FIGS. 1 and 2 show the main steps of an embodiment of the present invention, and will be described next with reference to these figures. still,
This example is a case of a bipolar semiconductor device, in which 1 is a p-type silicon substrate, 2 is an n-type silicon epitaxial layer, 3 is a silicon dioxide (Si02) layer, 4 is a base region, 5 is an emitter region, 6 is a bipolar semiconductor device. is a polycrystalline silicon layer containing no impurities, and conventional techniques can be applied as is until the formation of the base region 4 and the formation of the emitter electrode contact window, so the next step will be explained. Furthermore, it is assumed that the base region 4 has a conductivity type of P type by introducing, for example, a shelf element (B).See Figure 1 '1]. Contains mold impurities of 2 to 7 x 1 pi. At a high concentration of about 3 atomic particles, and 1000
The emitter region 5 is formed by introducing it shallowly to the extent of [A].
In the case of the present invention, it is desirable to prevent the formation of a silicon dioxide layer on the emitter electrode contact window.
The introduction of impurities is preferably carried out in a non-oxidizing atmosphere by applying a closed tube method (vacuum capsule method) or by applying an ion implantation method. In that case, the dose should be about 1×1 5 [atomic arc-2]. '2} The silicon dioxide layer 3 is patterned by applying a normal photo-etching method to form a base electrode contact window. During this time, the emitter electrode contact window is covered with a layer of photoresist. A polycrystalline silicon layer 6 is formed by applying a vapor phase growth method, for example, by thermal decomposition of monosilane (SiH4). The temperature in this case is 700-800

[00], the growth rate is, for example, 300 [A/min], and the layer thickness is 800 to 4000 [A/min].
]. See Figure 2 {41 Heat treatment for adjusting the current amplification factor hfe, that is, drive. Perform the login. The conditions at this time are 1000 [℃] × 30
[minutes], and the current amplification factor hfe is therefore 6
Adjusted to 0-8 bait saturation. ``At the same time, the impurities present in the base region 4 and emitter region 5 are also diffused into the polycrystalline silicon layer 6 due to a so-called creep-up phenomenon.
That part becomes conductive. In the figure, this is represented by sandy pattern portions 6B and 6E. It goes without saying that the portion 6B is of P type and the portion 6E is of N type. by the way,
When the heat treatment is performed, there is a possibility that impurities penetrate the polycrystalline silicon layer 6 and diffuse outward. To prevent this, the heat treatment is performed in a dry oxidizing atmosphere. For example, 100 to 3
It is preferable to form a silicon dioxide film as thin as 0.00 [A] to suppress loss of impurities. '5) For example, a vapor deposition method is applied to form an aluminum layer, and a normal photo-etching method is applied to pattern the aluminum layer to form a base electrode 7B, an emitter electrode 78, and other electrodes. If a thin silicon dioxide film is formed on the surface of the polycrystalline silicon layer in the step '4--, aluminum is deposited after this silicon dioxide film is removed. See Figure 3 {6) After that, using each aluminum electrode as a mask,
Selective etching of the polycrystalline silicon layer is performed using a hydrofluoric acid-based etching solution to form an electrode in which a polycrystalline silicon layer is disposed under each aluminum layer. In the semiconductor device manufactured as described above, despite the presence of the polycrystalline silicon layer 6 that does not contain impurities, the base electrode 7B is connected to the base region 4, and the emitter electrode 78 is connected to the emitter region 5, and the portion 6B or via section 6E,
Good ohmic contact can be found with each. By the way, in the above embodiment, only the base region and the emitter region were explained, but a polycrystalline silicon layer is formed on the entire surface including other regions, such as the collector/contact region, the isolation region between elements, and the resistance region. If conductivity can be imparted to the necessary portions as described above, there will be no need to selectively form a polycrystalline silicon layer, and the number of steps will be reduced. However, in such a case, it is extremely difficult to make the polycrystalline silicon layer uniformly conductive in parts or even in each part by heat treatment. The reason for this is that the amount of impurities creeping up differs from region to region depending on the predetermined heat treatment. Therefore, in such a case, it is necessary to perform further appropriate operations. This will be explained with reference to FIGS. 4 to 6. In addition, in FIGS. 4 to 6, the same parts as those explained with respect to FIGS. 1 to 3 are indicated by the same symbols.
Refer to FIG. 4') Heat treatment is carried out in exactly the same manner as explained by the engineer 5) in the previous embodiment to cause impurities to creep up into the polycrystalline silicon layer 6. Incidentally, the impurities that have climbed up are shown in a sandy pattern as in Figure 2, but the way they have climbed up is not uniform. In addition, in FIG. 3, 8 is an n-type buried layer, 9 is an n-type collector/contact region, and 10 is a P+-type element isolation region.
11 indicates resistance regions, respectively. See Figure 5.
For example, an aluminum layer is formed by applying a vapor deposition method. The aluminum layer is patterned by applying a common photo-etching method, and the electrodes 71S for element isolation region, the collector/contact electrode 7CC, the emitter electrode 7E, the base electrode 7B, the resistor electrodes 7R, 7R2, etc. form. 6. A heat treatment is performed to infiltrate aluminum from each electrode into the polycrystalline silicon layer 6 to compensate for the non-uniform creep-up of the impurities and obtain good ohmic contact. Note that when the temperature is set to 450 [°C] and the treatment is performed for 30 [minutes] in a nitrogen (N2) atmosphere, aluminum penetrates into the polycrystalline silicon layer 6 by 600 [A], and only the temperature increases by 500 [A]. When the same process is performed as [0], aluminum penetrates into the polycrystalline silicon layer 6 by 1000 [A]. Refer to FIG. 6. Thereafter, the polycrystalline silicon layer is selectively etched using the aluminum layer as a mask to form electrodes in which the polycrystalline silicon layer is disposed under each aluminum layer. As described above, the present invention is applicable not only to the base area and the emitter area but also to all other areas. Although each of the above embodiments relates to a bipolar type semiconductor device, the present invention is also useful for an MIS type semiconductor device. That is, conventionally, when making a short channel in an MIS type semiconductor device, a wide area between the source region and the drain region where the channel is to be formed is explored, and then the gap is reduced through heat treatment. things are being done. However, devices manufactured in this way have drawbacks such as increased capacitance between the gate, source, and drain, reducing switching speed, and short circuits.
The effect of making it a channel will be diminished. Therefore, in recent years, the space between the source region and the drain region is formed narrow from the beginning, and heat treatment is not performed. In that case, since each region is very shallow, the problem of penetration of the aluminum electrodes arises as in the bipolar semiconductor device. Therefore, the present invention can be advantageously applied to this case as well. As can be seen from the above explanation, according to the present invention,
By interposing the polycrystalline silicon layer between the aluminum electrode and the impurity region formed in the silicon bulk, short circuits caused by the reaction between aluminum and the silicon substrate are prevented, and the polycrystalline silicon layer is made conductive. Although,
Since the creeping up of impurities from the impurity region is utilized, even if the impurity regions have different conductivity types, they can be processed in the same process. In addition, since there are a wide variety of types of impurity regions, the creeping up of impurities is not uniform even if only a predetermined heat treatment is performed, resulting in good ohmics. If contact is not possible, a heat treatment after forming the aluminum electrode can cause the aluminum to penetrate into the polycrystalline silicon layer to ensure reliable ohmic contact. Furthermore, in bipolar semiconductor devices, it may be possible to perform both heat treatment for making impurities creep up into the polycrystalline silicon layer to make it conductive and heat treatment for adjusting the current amplification factor. In that case, the process becomes simpler.

[Brief explanation of drawings]

Figures 1 to 3 are process explanatory diagrams of one embodiment of the present invention;
6 to 6 respectively represent process explanatory diagrams of another embodiment. In the figure, 1 is a substrate, 2 is an epitaxial layer, 3 is a silicon dioxide layer, 4 is a base region, 5 is an emitter region,
6 is a polycrystalline silicon layer, 6B and 66 are parts where impurities have climbed up, 7E is an emitter electrode, and 7B is a base electrode. Figure 1 Soup 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. Forming a plurality of electrode contact windows in contact with the various impurity regions in an insulating film covering the surface of a semiconductor layer or a semiconductor substrate in which a plurality of impurity regions are formed,
Next, a polycrystalline silicon layer is formed covering at least the interior of the window, and then heat treatment is performed to cause impurities to creep up from at least one of the impurity regions into the polycrystalline silicon layer, thereby forming the polycrystalline silicon layer. forming a conductive region that reaches an intermediate position, then forming an aluminum layer on the polycrystalline silicon layer and performing a heat treatment to cause the polycrystalline silicon and aluminum to react and contact the conductive region; A method of manufacturing a semiconductor device, comprising: 2. The plurality of impurity regions are emitter regions and space regions constituting a transistor, and heat treatment is performed to form a conductive region in a part of the polycrystalline silicon layer and for adjusting the current amplification factor of the transistor. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed at the same time.