JPS608678B2 - Multiple signal extraction device - Google Patents

Description

[Detailed Description of the Invention] VIR signal for correcting distortion in the transmission path of luminance signals and chromaticity signals during the direct retrace period of television signals, various test signals, still image signals (facsimile), etc. It has been proposed to insert multiplexed signals.

The present invention relates to a multiplex signal extracting device that extracts a multiplex signal from a television signal into which the multiplex signal is inserted in the vertical retrace interval, and in particular, without being affected by weak electric fields or noise such as impulse noise. Also, 0. of the first field and the second field. This multiplexed signal can be reliably extracted regardless of field differences between groups (horizontal periods).

At present, it has been proposed to insert a VIR signal into the first horizontal period of the vertical retrace period of a television signal, as shown in FIGS. 1A and 1B.

This VIR signal has a reference signal inserted to correct transmission distortion at the brightness level of skin color, which has the best color discrimination ability in terms of human visual characteristics. The level is 0, the maximum white level is 100, the amplitude peak-to-peak value of burst signal 1 is 40, and a 3.58Mz sine wave with a phase of -(B-Y) is superimposed on the vedestal level, and the reference color The signal 2 has the same amplitude and phase as the burst signal, and is superimposed on a luminance level 70 corresponding to the average skin color luminance level, and is superimposed on the reference white signal 3.
is a brightness level of 50, and the level of the reference signal 4 is determined to be a brightness level of 7.5. Here, FIGS. 1A and 1B show signals in the vicinity of the vertical blanking period of the first and second fields of a color television signal, respectively. Conventionally, in order to extract this VIR signal, the number of horizontal synchronization signals including equalization pulses is counted from the vertical synchronization signal, and the number of burst signals is determined from the vertical synchronization signal. It has been proposed to detect the first baron's inserted horizontal period and extract this VIR signal. In devices that count burst signals, malfunctions occur in the case of weak electric fields or when noise such as impulse noise is inserted, and this VI
There was a drawback that the R signal could not be extracted.

Also, the positions where this VIR signal is inserted are the first field and the second field, and are 0. Because there are differences in spots,
This 0. There were various difficulties in extracting this VIR signal due to the difference in height. In view of this, the present invention is designed to accurately extract the VIR signal even in a relatively weak electric field and when noise such as impulse noise is inserted.

Hereinafter, one embodiment of the multiplexed signal extracting device of the present invention will be explained with reference to FIG.

In FIG. 3, reference numeral 5 indicates an input terminal to which a color television signal as shown in FIG. Then, the output signal of this sync separation circuit 6 is passed through a low-pass filter 7 that constitutes a vertical sync signal separation circuit.
The vertical synchronizing signal is supplied to the vertical synchronizing signal delay circuit 8 via the vertical synchronizing signal delay circuit 8.

Here, 7a is a vertical synchronization signal output terminal. This vertical synchronization signal delay circuit 8 is configured so that the green signal after the vertical synchronization signal is 0. Hu~
The IH is delayed, and in this example, the IH is delayed by 0.
Try to delay it by 7 beats. This vertical synchronization signal delay circuit 8
The output signal of 0 is supplied to the clear pulse forming circuit 9, and the vertical synchronizing signal is 0 on the output side of the clear pulse forming circuit 9.
．． After the 7th delayed signal, a synchronized clear pulse signal is obtained in green. Further, the output signal of the synchronization separation circuit 6 is transmitted to the automatic frequency control circuit 11 via a differentiation circuit 10 that constitutes a high-pass filter circuit that passes the horizontal synchronization signal.
is supplied to one input terminal of the Further, the output signal of this automatic frequency control circuit 11 is supplied to the horizontal oscillator 12, and the output signal of this automatic frequency control circuit 11 causes the horizontal oscillator 1 to
The oscillation frequency of 2 is controlled. Further, the output signal of this horizontal oscillator 12 is supplied to the other input terminal of the automatic frequency control circuit 11 as a comparison signal. On the output side of the horizontal oscillator 12, a horizontal frequency pulse signal is obtained as in the conventional case. The output signal of this horizontal oscillator 12 is supplied to one input terminal of an AND circuit 13 constituting a gate circuit, and the output signal of this AND circuit 13 is supplied to a clock terminal of a counter circuit 14. Further, the output signal of the clear pulse forming circuit 9 is supplied to the clear terminal of this counter circuit 14 to perform initial setting. The output signal of this counter circuit 14 is supplied to the VIR signal gate pulse output terminal 16 via an AND circuit 15 constituting an n decoder circuit, and the output signal of this counter circuit 14 is supplied to an (n+1) decoder circuit. The output signal of the NAND circuit 17 is supplied to the other input terminal of the AND circuit 13. In this example, this counter circuit 14 is 8-4-2-1.
The "1" output terminal 14a and "1" signal from the four output terminals of the counter circuit 14 are
"4" output terminal 14c and "8" from which a signal of "4" is obtained
The "8" signal output terminals 14d from which the signals are obtained are connected to the input side of the NAND circuit 17, respectively. Also, “1” output terminal 1
4a is connected to the input side of the AND circuit 15 via the inverter circuit 18, and the "4" signal output terminal 14c and "
8" signal output terminals 14d are respectively connected to the input side of the AND circuit 15. 14b is an output terminal for the "2" signal.

Further, in FIG. 3, Vcc is a power supply terminal. The example in FIG. 3 is configured as described above, so that when an odd field signal as shown in FIG. A vertical synchronizing signal as shown in FIG. 1D is obtained, and the vertical synchronizing signal as shown in FIG. 1D is delayed by the vertical synchronizing signal delay circuit 81 as shown in FIG. At the output side of the circuit 8, a vertical synchronizing signal delayed by 0.7 degrees as shown in Fig. 1 H' is obtained. The falling edge of the vertical synchronization signal as shown is 0.
At a time delayed by 79 days, a clear pulse signal 9a as shown in FIG. 1J is obtained at the output of the clear pulse forming circuit 9,
The counter circuit 14 is cleared by this clear pulse 9a. Further, a horizontal pulse signal synchronized with the horizontal synchronizing signal as shown in FIG. 1C is obtained as the output of the horizontal oscillator 12. This is supplied to the input side of the AND circuit 13 as a clock pulse. Further, the output side of the NAND circuit 17 is "1" after the counter circuit 14 is cleared until the output of this counter circuit 14 counts "1y".
'', that is, at a high level, the AND circuit 13 maintains the conductive state until the counter circuit 14 counts ``1y''. That is, when this counter circuit 14 is supplied with a clear pulse 9a as shown in FIG. 1J, this counter circuit 14 is cleared, and a signal as shown in FIG. 1Q is obtained at the output of the NAND gate circuit 17. At this time, a horizontal pulse as shown in FIG. 1C is supplied through the AND circuit 13, and therefore the counter circuit 14
A first
Signals as shown in FIG. At the output of the circuit 15, as shown in FIG.
A “1” signal is obtained during one horizontal period counting
This signal of one horizontal period as shown in FIG.
The R signal can be extracted. In addition, the first
When an even field video signal is supplied as shown in FIG. B, a vertical synchronizing signal as shown in FIG. The vertical synchronizing signal is delayed by the vertical synchronizing signal delay circuit 8 as shown in FIG. 1G, and the vertical synchronizing signal as shown in FIG.
A vertical synchronizing signal delayed by 7 minutes is obtained, and this is supplied to the clear pulse forming circuit 9, so that the rising edge of the vertical synchronizing signal as shown in FIG. 1 or the falling edge of the vertical synchronizing signal as shown in FIG. A clear pulse 9b is obtained at a position delayed by 0.7 units, and this is supplied to the counter circuit 14,
This counter circuit 14 is cleared. In this case, the clear pulse 9b differs from the clear pulse 9a by 0. Since there is a difference in speckles, but in the same corresponding horizontal period, the counter circuit 14 operates in the same manner as when an odd field color television signal is provided. That is, when this clear pulse 9b is supplied to the counter circuit 14, the output of the NAND gate circuit 17 rises as shown by the broken line in FIG. 1Q, and the output of this NAND gate circuit 17 becomes "
1", the AND circuit 13 becomes conductive and the first
A horizontal pulse obtained from the output of the horizontal oscillator 12 as shown in FIG. C is supplied to a counter circuit 14, and this horizontal pulse is counted by the counter circuit 14. in this case,
The signals obtained at the output side of the counter circuit are shown in Fig. 1L,
As shown in M, N, 0, it rises 0.9 days earlier than when an odd field color television signal is supplied, because there is no horizontal pulse during this time.
Thereafter, as shown in FIG. 1 L, M, N, 0, the operation is the same as when an odd field color television signal is supplied. Therefore, in this case as well, the counter circuit 14 as shown in FIG. A VIR gate signal for one horizontal period can be obtained. That is, in this example, since the clearing pulse signal of the counter circuit 14 is obtained by delaying the falling edge of the vertical synchronizing signal by 0.7 units, horizontal pulses are counted regardless of even fields and odd fields. Since the VIR signal corresponds to one horizontal period after counting the horizontal pulses, the VIR signal can be extracted accurately. Further, in the present invention, the horizontal pulses obtained at the output side of the horizontal oscillator 12, ie, the horizontal pulses at the output side of the horizontal oscillator 12 controlled by the automatic frequency control circuit 11, are used as clock pulses to be counted. Since it is designed to count, there is an advantage that it can be accurately counted even in a weak electric field or even if noise such as impulse noise is included in the video signal. In this third column of the diagram, the horizontal oscillator 12
Although it has been described that the horizontal pulses obtained at the output side of the horizontal oscillator 12 are directly counted, it goes without saying that the horizontal ranking signal formed by the output signal of the horizontal oscillator 12 may also be counted. Further, FIG. 4 shows another embodiment of the present invention, in which the circuit is simplified by using a staircase wave generation circuit without using the counter circuit 14 in FIG. 3. It was designed to make the

In FIG. 4, parts corresponding to those in FIG. 3 are given the same reference numerals, and detailed explanation thereof will be omitted. In this FIG. 4, the output signal of the horizontal oscillator 12 is supplied to the horizontal output circuit 19,
The secondary winding of the horizontal output transformer of this horizontal output circuit 19 is connected to a power supply terminal 2 through which a DC operating voltage is obtained via a rectifier circuit 20.
Connect to 1.

Further, the output signal of the vertical synchronization signal delay circuit 8 is supplied to the clear terminal of the staircase wave generation circuit 22, and the horizontal output circuit 19
A signal synchronized with the horizontal pulse obtained on the output side of is supplied to the staircase wave generation circuit 22, so that the staircase wave generation circuit 22 obtains a voltage that falls in a stepwise manner in synchronization with the horizontal pulse. . The output signal of this staircase wave generation circuit 22 is sent to the trigger pulse forming circuit 23 which generates a trigger pulse when the output of this staircase wave generation circuit 22 falls to a predetermined value. The trigger pulse obtained as an output is supplied to a trigger terminal of a monostable multivibrator 24 constituting a gate pulse generation circuit. In this case, this monostable multivibrator 2
A time constant of 4 is configured so that a pulse signal of one horizontal period can be obtained at the output terminal 16. In this case, the relationship among the vertical synchronizing signal delay circuit 8, horizontal output circuit 19, and staircase wave generation circuit 22 is as follows. While the vertical synchronizing signal is supplied to the base of the transistor 8a of the vertical synchronizing signal delay circuit 8, this transistor 8a is conductive, and the potential on the collector side of this transistor 8a decreases. When the level drops to a predetermined level, the transistor 22a of the staircase wave generation circuit 22 becomes conductive, and the potential on the collector side of this transistor 8a is held at a predetermined potential. , the resistor 8b and capacitor 8c of this vertical synchronization signal delay circuit 8, and the transistor 2
The transistor 22a is conductive for a predetermined time determined by the base-emitter potential of the transistor 22a. This transistor 22
In this example, the optimum period of a is set to 0.7 molars. In addition, in the staircase wave generation circuit 22, when the transistor 22a becomes conductive, the capacitor 22b is discharged, and the transistor 2
The potential at the connection point d between the emitter 2a and the capacitor 22b rises to approximately the power supply voltage ycc (here, Vcc is the output voltage of the rectifier circuit 20). When the potential at point d becomes high, the diode 22c is reverse biased, so the transistor 22d is connected to the power supply voltage y via the resistor 22e.
Since cc is supplied, this transistor 22d becomes conductive.
The collector potential of is a low potential. Also, horizontal output circuit 1
Since the pulse obtained on the secondary side of the horizontal output transformer 9 has a negative polarity, the potential at point d decreases each time this negative pulse is supplied. What happens is that the capacitor 22d is connected to the power supply terminal - capacitor 2
2d - diode 22f - variable resistor 22g - resistor 2
This is because the voltage is charged by the circuit constituted by one end C of the secondary winding of the horizontal output transformer of the 2h-horizontal output circuit 19. In this case, when there is no horizontal pulse at one end C of the secondary winding of the horizontal output transformer of the horizontal output circuit 19, the potential at point C is approximately the potential Vcc of the power supply terminal, so the diode 22f is not normally biased. Therefore, capacitor 22b is not charged through this diode 22f. Therefore, the potential at point d decreases each time a horizontal pulse arrives. In this case, the degree of fall in the potential at point d is the power supply voltage Vcc obtained at the power supply terminal 21,
The potential during the horizontal pulse period at point c at one end of the secondary winding of the horizontal output transformer of the horizontal output circuit 19 is determined by the capacitor 22b, the variable resistor 22g, and the resistor 22h. In this staircase generating circuit 22, when this point d drops to a predetermined potential, the diode 22c becomes conductive, and the transistor 22c becomes conductive.
The base potential of d is lowered to make this transistor 22d non-conductive. In this case, the degree of potential drop at point d is appropriately selected so that when the twelfth horizontal pulse arrives, this transistor 22d becomes non-conductive. In this case, the power supply voltage Vcc and the potential during the horizontal pulse period at point c change in proportion to the power supply voltage, so when point d reaches a predetermined level, changes in the power supply voltage, load, temperature, etc. It has the advantage of being less likely to fluctuate. When this transistor 22d becomes non-conductive, a trigger pulse is obtained from the output of the trigger pulse forming circuit 23, and this is supplied to the monostable multivibrator 24 as a trigger signal. In the example shown in FIG. 4, when the input terminal 5 is supplied with an odd field color television signal as shown in FIG. At the point, a negative horizontal pulse as shown in FIG. 5C is obtained, and at the output of the vertical synchronization signal delay circuit 8, a vertical synchronization signal as shown in FIG. A signal delayed by 7 h is obtained.

This is supplied to the staircase wave generation circuit 22, and as shown in FIG. 5D, the vertical synchronization signal is delayed by 0.7 beats, and
By charging the capacitor 22b, the voltage at point d of the staircase wave generation circuit 22 is increased as shown in FIG. 5F. The voltage at point d is reduced by a predetermined voltage each time this horizontal pulse is supplied, due to the horizontal pulse obtained at point c as described above. That is, as shown in FIG. 5, the output side of the staircase wave generation circuit 22 is activated by the trigger pulse generation circuit 2 when 12 horizontal pulses are supplied from green after the vertical synchronization signal delayed by 0.7 units.
3, and this trigger pulse forming circuit 23 supplies a trigger pulse to the monostable multivibrator 24. That is, the collector of the transistor 22d is 0,
As shown in FIG. 5G, the output side of the staircase wave generation circuit 22 becomes a low voltage when a vertical synchronizing signal is supplied, and becomes a high level when a predetermined number of horizontal pulse signals are supplied, and the trigger pulse forming circuit 23 As shown in FIG. 5 H', when the output side of the staircase wave generation circuit 22 becomes high level, a trigger pulse is generated on the output side of the monostable multivibrator 24, that is, the VIR signal gate. As shown in FIG. 5, the pulse output terminal 16 rises when the 12th horizontal pulse signal is obtained from the trailing edge of the vertical synchronizing signal delayed by 0.7 spots, and the horizontal pulse signal of the 1st half is generated. A gate signal that appears to fall is obtained. That is,
The VIR signal can be extracted using this gate signal. Furthermore, when an even field color television signal is supplied to the input terminal 5 as shown in FIG. Similarly, a horizontal pulse signal as shown in FIG. 5C is obtained, and a vertical synchronization signal delayed by 0.7 as shown in FIG. 5E is obtained on the output side of the vertical synchronization signal delay circuit 8. . In this case, compared to the odd field vertical synchronization signal, 0. However, the trailing edge of this vertical sync signal is inserted corresponding to the period of the horizontal pulse to which the trailing edge of the vertical sync signal of the odd field corresponds, so a staircase wave is generated. The circuit 22 operates in the same manner as described above, and therefore the trigger pulse forming circuit 23 and the monostable multivibrator 24 also operate in the same manner as described above,
A gate signal as shown in FIG. 5 is obtained at the VIR signal gate pulse output terminal 16. In this case, the voltage at point d of the staircase wave generation circuit 22 and the voltage at the collector of the transistor 22d have rising and falling edges of 0.0 and 0.5, respectively, as shown by broken lines in FIG. 5F and G. It only makes the porridge faster,
Other operations are the same as for odd fields. That is, it goes without saying that the embodiment of FIG. 4 has the same effects as the embodiment of FIG. 3. Furthermore, the example shown in FIG. 4 has the advantage that the construction is simpler since no counter circuit is provided compared to the example shown in FIG. In the above embodiment, the vertical synchronizing signal is delayed by 0.7 steps, but the delay time of the vertical synchronizing signal delay circuit 8 is set to 0.7 steps. Group~
It goes without saying that even if the IH is delayed, the same effect as described above is obtained, and even if this delay circuit is configured to be delayed by (m+0.5)H to (m+1) days, the same effect as described above is obtained. be.

In this case m is a positive integer including 0, and in the embodiment described above m is less than 12. In addition, in the above embodiment, the trailing green of the vertical synchronizing signal is delayed and the horizontal pulses are counted from the trailing edge of the delayed vertical synchronizing signal, but the leading green of the vertical synchronizing signal is delayed. Of course, horizontal pulses may be counted from the delayed position of this edge. Furthermore, in the above embodiment, the vertical synchronization signal separation circuit 7 and the vertical synchronization signal delay circuit 8 are provided separately. Of course, it is also possible to use an integrated version. In addition, in the above embodiment, an example was described in which the VIR signal is inserted into the horizontal period of the first baron of the vertical retrace period and taken out, but this is limited to the horizontal period of the first baron. Of course, the present invention can be used not only for the VIR signal but also for extracting multiplexed signals such as test signals and facsimile signals inserted into the horizontal period of the vertical retrace period. Further, the present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations may be adopted without departing from the gist of the present invention.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are diagrams for explaining the present invention, respectively;
FIG. 3 is a block diagram showing one embodiment of the multiplexed signal extraction device of the present invention, FIG. 4 is a block diagram showing another embodiment of the present invention, and FIG.
The figure is a diagram for explaining FIG. 4. 5 is a television signal input terminal, 6 is a synchronization separation circuit, 7
8 is a vertical synchronization signal separation circuit, 8 is a vertical synchronization signal delay circuit,
9 is a clear pulse forming circuit, 1 is a high-pass filter, 11 is an automatic frequency control circuit, 12 is a horizontal oscillator, 1
4 is a counter circuit, and 16 is a VIR signal gate pulse output terminal. One leopard and two legs? G8 Zukan 4 Zutoku 8 Kyou

Claims (1)

[Claims] 1 means for deriving horizontal pulses from an input television signal; a counting circuit for counting the derived horizontal pulses;
a delay circuit that delays the leading edge or trailing edge of the vertical synchronization signal of the input television signal by (m+0.5)H to (m+1)H (where m is a positive integer including 0 and H is one horizontal period); and initializing the counting circuit based on the leading edge or trailing edge of the delayed vertical synchronizing signal obtained from the delay circuit, and generating a multiplexed signal inserted into the vertical blanking period by the output of the counting circuit. A multiple signal extraction device characterized in that it extracts.