JPS608956B2 - Diode array for thermal head - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an in-line integrated diode array implemented in a thermal head.

In recent years, thermal recording methods have come into widespread use as a means of hard copying, and efforts are being made to improve the dot density of thermal heads in order to improve resolution in thermal recording.

Usually, a diode is inserted in series with the heating element of a thermal head, and the individual heating dots in a matrix configuration are electrically isolated from each other.

Fig. 1 shows the electrical connection method of the thermal head. It will be done. In order to generate heat from this heating element, a signal is applied to the transistor switch group Q,, Q2...Q32 and the transistor switch group Q,', Q2'...Q%' to make them conductive. For example, Q,
When only Q,′ and Q,′ are turned on, Q,→R33→
In order to prevent the flow from passing through R34→R2→Q,', a group of diodes shown as D, , D2, . . ., D64 must be inserted in series with each heating element. This group of diodes is usually mounted on the thermal head board integrally with the heating element, but for this purpose, an arrangement density that is almost the same as the thermal head density is required, so for example, in the example shown in the figure, D, ~ D32, D33 24 semiconductor chips of 32 in-line diode arrays integrated as D64 are arranged to form a total of 768 diodes.

Conventional diode arrays have been constructed using conventional integrated circuit technology as shown in FIG.

That is, to explain FIG. 2, an N-type epitaxial layer 2 is formed on a P-type silicon crystal substrate, islands 4 and 5 are formed by a P-type separation layer 3, and a P-type diffusion layer 6, 7, a P-type electrode 8 and an N-type electrode 9 constitute a diode D, and a P-type electrode 10 and an N-type electrode 11 constitute a diode D2. Since FIG. 2 is a conceptual diagram for explaining the structure of a conventional diode array substrate, actual surface oxide films, metal wiring, etc. are omitted. Also, in reality, an N+ diffusion layer or colleter wall is formed to take out the N-type electrode, and a buried layer is formed to prevent parasitic effects, but these are also omitted in the diagram. Conventionally, a diode array with the above configuration was used, but as the thermal head to be mounted becomes 4-inch and the density of printed dots becomes higher, the arrangement density of the diode array has to be increased. First, as density increases, parasitic effects have become impossible to ignore.In other words, if a current of about 40 mA is applied to D, ?R, in order to generate heat only in P, in Figure 1, the heat generated in other areas will increase. It is a problem if the body generates heat, but if 40mA is applied to D in Figure 2,
If hFE of the parasitic PNP transistor constituted by the P-type diffusion layer 6, the N-type island region 4, and the P-type substrate 1 is 0.02, 0.8 mA flows into the substrate, and this
It flows out to the N-type electrode 11 of the diode D2 through the PN diode formed by the mold island 5. This causes a problem in that it becomes a parasitic leakage current and causes R2 to generate heat. Also, not only D, but also D3 to D32 are energized at the same time, and when only D2 is in the off state, almost 0
．． A leakage current of 8 mA x 31 = 24.8 A flows out of the N-type electrode 11 of ○2 and flows through R2, so that the heating element R2 generates heat, and a predetermined portion of the thermal paper that should not appear in the first place develops color. In order to prevent parasitic transistor effects in integrated semiconductor devices, it is necessary to increase the impurity concentration of the N-type epitaxial layer, increase the thickness, add a buried layer or collector wall, or add Au to the substrate. Attempts have been made to do things such as diffusion, but these measures are constrained by other design conditions, such as forward on-voltage and breakdown voltage, and the arrangement density of these diodes is limited to 10
When the pitch becomes 0 micron, the parasitic hFE becomes 0.0.
It becomes impossible to keep it below 2.

SUMMARY OF THE INVENTION In view of these conventional drawbacks, it is an object of the present invention to provide a diode array structure and its subsequent method that prevents the parasitic leakage current that becomes a problem due to increased density of diode arrays.

The present invention completely separates the diode connected in series to the heating element to be printed from the parasitic circuit that runs through the semiconductor substrate to other resistors that do not normally generate heat, so that the printing current drives the parasitic current. The aim is to completely prevent this from happening.

Normally, in order to prevent the generation of parasitic circuits that occur in semiconductor integrated circuits, electrically isolated island regions are formed in the substrate using PN junctions, and the substrate is placed at the lowest potential (preferably ground potential). Fix the area to the highest potential.

However, due to the structural limitations of the diode array for thermal heads, which are arranged and installed on the thermal head, it is difficult to set the substrate at a fixed potential. Figure 1 and 2
The equivalent circuit including the parasitic circuit shown in the figure is as shown in FIG. 3. The number 5 in the figure corresponds to FIGS. 1 and 2. now,
If Q2 is open, no current will flow through the diode D2, which is made up of 7 and 5, and the NPN transistor, which is made up of the island region 4, the substrate turtle, and the island region 5, usually has an extremely small hFE. , this 0 equivalent circuit of FIG. 3 can be further simplified and expressed as shown in FIG. 4. That is, when Q and Q,' become conductive, the main current flowing through the PN junction formed by the P-type diffusion layer 6 and the N-type island region 4 flows through R, causing the heating resistor R to generate heat. But, P
Some of the holes injected into the N-type island region 4 from the N junction also reach the substrate 1.

In other words, the P-type diffusion layer 6, the N-type island region 4, and the P-type substrate 1 constitute a parasitic PNP transistor, and a part of the injection hole 0 becomes a collector due to the current increase rate hFE of this parasitic transistor. It flows into the substrate 1. Board 1 and neighboring island 5
is a PN diode and is biased in the forward direction, so carriers flowing into the substrate 1 directly flow into the adjacent island 5, causing R2 to generate heat. In other words, when the main current flows through the heating element R, a parasitic effect leakage current also flows through the heating element R2 according to the hFE of the parasitic transistor.

This shows that the normal printing current becomes the base current of the parasitic PNP transistor 0, and this ME times the current also flows into the adjacent heating element.

This means that the parasitic current is driven by a normal current.The reason for this is that the normal diode PN junction constitutes the emitter-base junction of the parasitic transistor. Its feature is that the normal current path and the parasitic circuit are completely separated.

The present invention uses well-known means as a general semiconductor device manufacturing technique and provides a configuration in which conventional parasitic leakage current is completely suppressed. Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings. FIG. 5 is a schematic cross-sectional view of a diode array showing an embodiment of the present invention and a method of connecting the diode array to a heating element resistor. A plurality of P-type island regions 31, 32, 33 are formed on one surface of an N-type silicon substrate 30, and are separated from each other.
N+ type regions 34, 35, 3 within the P type island region, respectively.
A diode array D, . ,D22,
D33, each P-type island region 31, 32, 3
3 includes transistors Q, , Q that constitute the image signal switch.
2, Q are connected, and the respective N+ type regions 34, 35,
36 is a heating element resistor R, . , R22, and R33 are connected.

When Q, and Q,′ become conductive, the power supply Vcc reduces Q.
, one P region 31-N ten regions 34-resistance R, . A current flows through the circuit called -Q,'. For this reason, R, . generates heat and gives color to the thermal recording paper, so if Q2 and Q are off, R22 and R33 will not develop color and R, . Only that part will be included. In this case, diodes D, . A parasitic circuit is connected in parallel to the diodes D, . The junction of is P
Since this is the interface between the region 31 and the N+ region 34, the PNPN of the parasitic circuit, that is, the P region 31, the N type substrate 30, and the P region 3
2. It is completely separated from the N+ region 35, and the normal current does not drive the parasitic PNPN circuit as in the conventional case. Here, in the present invention, since the N side of the diode is set to N+, the series resistance of the diode is low, and the characteristics as a diode for a thermal head are improved.
In order to make the N side N+, an N type substrate must be used. Further, if the structure is as shown in FIG. 2, the surface concentration of boron is low and the N side is an island region, so it has the disadvantage that it is not possible to increase the concentration of both P and N. FIG. 6 shows an equivalent circuit of this embodiment.

A comparison with FIG. 4 will make the gist of the present invention clear. That is, in the example of the slave shown in FIG. 4, the diode D is parasitic PN.
A current E times the electric current flowing through R, which forms the emitter base of the P transistor, flows into the collector of the parasitic transistor, and this current flows into R2. On the other hand, in the case of FIG. 6, the diodes D, . Since the current flowing through R and the parasitic circuit current are separated, R, . The current flowing through R22
Q, if the parasitic PNPN turn-on voltage is higher than Vcc.
No current flows into R22 when the switch is turned on. The parasitic PNPN includes a P-type island region 31, an N-type substrate 30,
It is composed of an adjacent P-type region 32 and an N+ region 35, but since it is easy to reduce Q and N+Q2 to 1 or less, turn-on can be easily prevented. For example, the specific resistance of the N-type silicon substrate 30 of the diode array shown in FIG.
The specific resistance of the type island regions 31, 32, and 33 is 0.50 mm, the thickness is 6 microns, the diffusion depth of the N+ type regions 34, 35, and 36 is 2 microns, and a separation diffusion layer separating each island (Fig. In this case, the width of the N-type region between the islands was set to 10 microns on the mask, and the pitch of the diode array was set to 100 microns. Introduce the killer by diffusing at 1000 qo for 20 minutes.

) using a diode array, the resistance value of the heating resistor is 3000, and the power supply voltage Vcc is 16.5V, then Q,
, Q,' are both 0.5V and the diodes D, . When the forward voltage drop of D, . For the forward characteristic of R, . Characteristics with the load line drawn, that is, 5
The current at A of 0 is R, . flows to As previously explained, in the case of Fig. 2, when this much current flows, a current times hFE flows into the adjacent resistor which is in the OFF state, and the value E becomes 0.0.
If it is 2, 1 A will flow into the neighboring area as a leakage current. However, in this embodiment, as is clear from FIG. 6, the parasitic circuits are D, . Since the parasitic PNPN and R22 are simply connected as a load to Vcc, there is only a simple junction leakage current unless the PNPN is turned on.

In this embodiment, the P-type island region 31-N-type substrate 30-adjacent P-type island region 31-N-type substrate 30-
The current increase rate Q of the parasitic PNP transistor composed of the type region 32 is 0.001, and the parasitic NP transistor composed of the N type substrate 30 - the adjacent P type island region 32 - the N0 region 35 therein
The current increase rate Q2 of the N transistor is 0.02, and Q
, 10Q2《1, so the current flowing through R22 is R, . Even if the current flowing through the tube was 50 A, it was slightly less than 0.001 A. Therefore, the difficulty of the manufacturing process in the case of FIG. 2 and the case of FIG. 5 is almost the same, and the leakage current is reduced to one thousandth, which is a remarkable effect. Moreover, with even higher density, the Q of the parasitic NPN transistor
Even if 2 becomes considerably high, for example, 0. There is almost no change in the leakage current even when the temperature becomes fertile.In the conventional method, if Q becomes 0.8 (4 for hFE), the leakage current is actually 4 times the printing current of the main button (actually Current feedback is applied due to the power source), and the effect of the present invention becomes more pronounced as the density increases.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the electrical connection method of the thermal head, Fig. 2 is a cross-sectional view of a diode explaining an example of a diode array for the thermal head, Figs. 3 and 4 are equivalent circuit diagrams, and Fig. 6 The figure is a circuit diagram of an embodiment showing a method of connecting a diode and a heating element according to the present invention, and FIG. 6 is a diagram showing an equivalent circuit thereof. 30 states. ．． . N-type semiconductor substrate, 31, 32, 33...P-type island region, 3
4, 35, 36...N+ type region "R,.HoriR22,R
33... Resistor for heating dots. Section 1 Neighboring Leopard 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1 A plurality of diodes formed by a plurality of P-type island regions formed separately from each other in an N-type semiconductor substrate and an N^+-type region formed within the P-type island region, A diode array for a thermal head, characterized in that a resistance group for heating dots is connected to each N^+ region side.