JPS6110978B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a self-alignment MS type integrated circuit. In the manufacturing process of self-alignment MS type integrated circuits, the source and drain regions are diffused after the gate electrode is formed. Therefore, if wiring is made using the electrode material when forming the gate electrode, the source and drain regions are formed under the wiring. It was not possible to form a diffusion layer during diffusion of the region. In other words, the wiring formed by the electrode material formed when forming the gate electrode and the wiring formed from the impurity diffusion region formed when forming the diffusion of the source and drain regions could not intersect.
Therefore, in order to form an impurity diffusion region under the wiring made of the gate electrode material, it is necessary to perform diffusion before forming the gate electrode. An object of the present invention is to diffuse impurities under the wiring for forming source and drain regions without diffusing impurities under the wiring using a gate electrode material before forming the gate electrode. It is to form layers.

According to the present invention, it is possible to intersect the wiring made of the electrode material performed when forming the gate electrode with the wiring made of the impurity diffusion layer performed when forming the source and drain regions without performing another impurity diffusion step. Impurities in semiconductors are displaced by supplying energy through high temperatures or other methods. This fact is utilized to connect impurity regions of the opposite conductivity type to a semiconductor substrate of one conductivity type, which are inadvertently separated from the substrate.

The present invention will be explained in detail below using the drawings. Examples of P-channel silicon gate MS transistors are shown in FIGS. 1 and 2. N-type silicon substrate 1
A thermal oxide film 7 of approximately 1 .mu.m thick is formed on the entire surface of the substrate, and the thermal oxide film in the region where the P-type impurity is to be diffused and the region where the gate is to be formed is removed by photo-etching. Then about
A gate oxide film of 1000 Å and polycrystalline silicon of about 0.5 μm are applied to the entire surface of the substrate, and by photo-etching, the polycrystalline silicon other than the portions that will become the gate electrodes 5 and interconnections 6 is removed, and then the polycrystalline silicon is removed except for the gate oxide film 4 directly under the polycrystalline silicon. excluding the gate oxide film.
Thereafter, by diffusing P-type impurities, polycrystalline silicon 5 and 6 become P-type, and P-type regions are formed in required regions 2 and 3 of the silicon substrate. During the diffusion of this P-type impurity, if the amount is small, the P-type impurity layer will be separated by polycrystalline silicon as shown in Figure 1, but if the width of the polycrystalline silicon is narrow enough, diffusion will be sufficient. For example, as shown in FIG. 2, the P-type impurity layer 3 under the polycrystalline silicon wiring 6 is not separated by the polycrystalline silicon wiring. In other words, the wiring 6 made of polycrystalline silicon,
Intersection with the wiring 3 is possible due to the P type impurity layer formed at the same time as the source and drain regions. In addition, in this method, the width of the polycrystalline silicon at the wiring intersection needs to be sufficiently narrow, but this increases the resistance of the polycrystalline silicon wiring by using as many polycrystalline silicon wirings according to this embodiment in parallel. This can be prevented by: Further, the source/drain of a field effect transistor or the final channel spacing is formed to have a predetermined channel spacing.

[Brief explanation of the drawing]

FIGS. 1 and 2 are cross-sectional views of a P-channel silicon gate MS transistor during manufacture. In these figures, 1 is an N-type silicon substrate,
2 is a source and drain region, 3 is a P-type impurity diffusion layer used for wiring, 4 is a gate oxide film, 5 is a silicon gate, 6 is polycrystalline silicon used for wiring, 7 is a thermal oxide film with a thickness of about 1 μm It is.

Claims (1)

[Claims] 1. A step of simultaneously and separately forming a gate electrode made of polycrystalline silicon and a wiring layer made of the same type of polycrystalline silicon on a semiconductor substrate of one conductivity type via a thin insulating film; A step of introducing opposite conductivity type impurities toward the substrate from both sides, and also introducing opposite conductivity type impurities into the gate electrode and both sides thereof, and diffusion wiring using the opposite conductivity type impurities introduced from both sides of the wiring layer. A heat treatment is performed to form the layer, whereby the diffusion layers on both sides of the wiring layer are formed so as to be continuous under the wiring layer, and the diffusion layers on both sides of the gate electrode are spaced apart from each other with the gate electrode in between. A method of manufacturing a semiconductor device, comprising the step of forming source and drain regions at the same time as the diffusion wiring layer.