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JPS6111391B2 - - Google Patents
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JPS6111391B2 - - Google Patents

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Publication number
JPS6111391B2
JPS6111391B2 JP13959478A JP13959478A JPS6111391B2 JP S6111391 B2 JPS6111391 B2 JP S6111391B2 JP 13959478 A JP13959478 A JP 13959478A JP 13959478 A JP13959478 A JP 13959478A JP S6111391 B2 JPS6111391 B2 JP S6111391B2
Authority
JP
Japan
Prior art keywords
relay
load device
load
controlled
control output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13959478A
Other languages
Japanese (ja)
Other versions
JPS5565184A (en
Inventor
Koji Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP13959478A priority Critical patent/JPS5565184A/en
Publication of JPS5565184A publication Critical patent/JPS5565184A/en
Publication of JPS6111391B2 publication Critical patent/JPS6111391B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 本発明は2系統以上の制御出力端子を有し、そ
の制御出力信号を組合せて使用可能となしたタイ
マー装置に関する。 従来のタイマー装置は、複数の系統を制御可能
となしたタイプのものがあるが、これらは単に該
複数の系統を個々に制御するだけであり、設定時
刻の組合せにより、他の系統を動作させることは
できなかつた。そこで本発明は上述の点に鑑みな
された新規なタイマー装置を提供するものであ
り、以下図面に従つて説明する。 第1図は本発明のタイマー装置を示すブロツク
図、第2図イ〜ニは同ブロツク図のための波形図
である。 図においては複数の制御出力端子2,3,4
を有する制御回路、5,6は電源ライン、
は各々第1、第2及び第3リレーで各々リ
レー接点10,11、12,13及び14,1
5、並びに第1リレー駆動回路16、第2リレー
駆動回路、17及び第3リレー駆動回路18を有
する第1リレー、第2リレー及び第3リレーであ
る。19は被制御装置20,21,22を有する
第1負荷装置、23は選択手段24に設けた選択
スイツチ25,26,27の切換に応じて制御さ
れる第4リレー駆動回路28を有する第4リレー
で、該第4リレー23の動作に伴い、リレー接点
29,30は閉成され、これにより第2負荷装置
31が動作する。 次に本発明の一実施応用例について説明する
と、被制御装置20,21,22として各々カセ
ツトテープレコーダー、ELカセツトテープレコ
ーダー及びオープンリールテープレコーダ、第2
負荷装置31としてチユーナーを接続した場合、
上述の被制御装置20,21,22としての各テ
ープレコーダーを各々ポピユラー、セミクラシツ
ク及びクラシツクの音楽を録音するとする。 先ず制御回路の各制御出力端子2,3,4が
ローレベルの場合は各リレーはオフ
で、第1負荷装置19及び第2負荷装置31は共
に不動作状態となつている。 いま制御回路の動作により第2図イに示す設
定時刻に応じて期間t1及び期間t5に制御出力端子
2がハイレベルになると、これに伴い、第1リレ
が動作してリレー接点10,11が閉じ、被
制御装置20に電源が供給される。 このとき選択手段24の選択スイツチ25,2
6,27を図示の通り閉じてあれば、制御出力端
子2からの制御出力信号はダイオード32及び上
記選択スイツチ25を介して第4リレー23を動
作せしめ、これに伴いリレー接点29,30が閉
じ、第2負荷装置31に電源が供給される。即ち
被制御装置20としてのカセツトテープレコーダ
ー及び第2負荷装置31としてのチユーナーが期
間t1と期間t5に電源がライン5,6から供給され
ることになり、これに従つて上記第2負荷装置
1としてのチユーナーで受信した受信信号は上記
被制御装置20としてのカセツトテープレコーダ
ーにライン33を介して加えられ、カセツトテー
プに上記受信信号が録音される。 次に第2図ロに示す期間t2及び期間t4において
は被制御装置21に、第2図ハに示す期間t3にお
いては被制御装置22に電源が供給され第1図に
示す状態に選択手段24がセツトされていると
き、第2図ニの通り期間t1,t2,t3,t4及びt5
間、第2負荷装置31に電源が供給される。 従つてカセツトテープレコーダー、ELカセツ
トテープレコーダー及びオープンリールテープレ
コーダーに各々所定の信号が録音される。 なお選択手段24の各選択スイツチ25,2
6,27は第2負荷装置31の各被制御装置に応
じて選択設定すればこれに伴いダイオード32,
33,34が各々オンになつて、第4リレー駆動
回路28が動作し、一方第1図とは異なり、例え
ば被制御装置21とは切離したい場合には、選択
スイツチ26をオフにしておくと、第2負荷装置
31は選択スイツチ25,27のオンに対応した
各期間に応じて電源が供給される。 以上の通り本発明によれば2系統の負荷装置に
制御回路の動作に応じて所定の期間、所定組合せ
により対応動作が可能となる。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timer device that has two or more systems of control output terminals and can use a combination of control output signals. Some conventional timer devices are capable of controlling multiple systems, but these simply control the multiple systems individually, and operate other systems based on a combination of set times. I couldn't do that. Therefore, the present invention provides a novel timer device that has been made in view of the above points, and will be described below with reference to the drawings. FIG. 1 is a block diagram showing a timer device of the present invention, and FIGS. 2A to 2D are waveform diagrams for the same block diagram. In the figure, 1 indicates multiple control output terminals 2, 3, 4.
5, 6 are power lines, 7 ,
8 and 9 are the first, second and third relays, respectively, and the relay contacts 10, 11, 12, 13 and 14, 1, respectively.
5, and a first relay, a second relay, and a third relay each having a first relay drive circuit 16, a second relay drive circuit, 17, and a third relay drive circuit 18. 19 is a first load device having controlled devices 20, 21, and 22; 23 is a fourth load device having a fourth relay drive circuit 28 that is controlled in response to switching of selection switches 25 , 26, and 27 provided in selection means 24; With the operation of the fourth relay 23 , the relay contacts 29 and 30 are closed, thereby causing the second load device to close.
31 works. Next, an example of an embodiment of the present invention will be described. The controlled devices 20, 21, and 22 are a cassette tape recorder, an EL cassette tape recorder, an open reel tape recorder, and a second
When a tuner is connected as the load device 31 ,
It is assumed that the tape recorders serving as the above-mentioned controlled devices 20, 21, and 22 record popular, semi-classical, and classical music, respectively. First, when each control output terminal 2, 3, 4 of the control circuit 1 is at a low level, each relay 7 , 8 , 9 is off, and both the first load device 19 and the second load device 31 are in an inoperable state. There is. When the control output terminal 2 becomes high level during the period t1 and the period t5 according to the set time shown in FIG. 2A due to the operation of the control circuit 1 , the first relay 7 accordingly becomes The relay contacts 10 and 11 are operated, and power is supplied to the controlled device 20. At this time, the selection switches 25, 2 of the selection means 24
6 and 27 are closed as shown, the control output signal from the control output terminal 2 operates the fourth relay 23 via the diode 32 and the selection switch 25, and the relay contacts 29 and 30 are accordingly closed. , power is supplied to the second load device 31 . That is, the cassette tape recorder as the controlled device 20 and the tuner as the second load device 31 are supplied with power from the lines 5 and 6 during periods t1 and t5, and accordingly, the second load is Device 3
The received signal received by the tuner 1 is applied to the cassette tape recorder as the controlled device 20 via the line 33, and the received signal is recorded on the cassette tape. Next, power is supplied to the controlled device 21 during the period t 2 and period t 4 shown in FIG. 2B, and to the controlled device 22 during the period t 3 shown in FIG. When the selection means 24 is set, power is supplied to the second load device 31 during periods t 1 , t 2 , t 3 , t 4 and t 5 as shown in FIG. 2D. Therefore, predetermined signals are recorded on each of the cassette tape recorder, EL cassette tape recorder, and open reel tape recorder. Note that each selection switch 25, 2 of the selection means 24
6 and 27 are selectively set according to each controlled device of the second load device 31 , and accordingly the diodes 32,
33 and 34 are respectively turned on, and the fourth relay drive circuit 28 is operated.On the other hand, unlike in FIG. , second load device
31 is supplied with power in accordance with each period corresponding to when the selection switches 25 and 27 are turned on. As described above, according to the present invention, the two systems of load devices can perform corresponding operations in a predetermined combination for a predetermined period according to the operation of the control circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のタイマー装置のブロツク図、
第2図イ〜ニは第1図の説明波形図を示す。 主な図番の説明、……制御回路、5,6……
電源ライン、……第1リレー、……第2リレ
ー、……第3リレー、19……第1負荷装置、
20,21,22……被制御装置、31……第2
負荷装置、24……選択手段、23……第4リレ
ー。
FIG. 1 is a block diagram of the timer device of the present invention;
2A to 2D show explanatory waveform diagrams of FIG. 1. Explanation of main drawing numbers, 1 ... Control circuit, 5, 6...
Power line, 7 ...first relay, 8 ...second relay, 9 ...third relay, 19 ...first load device,
20, 21, 22...Controlled device, 31 ...Second
Load device, 24 ... Selection means, 23 ... Fourth relay.

Claims (1)

【特許請求の範囲】[Claims] 1 所定の設定時刻毎に制御回路の制御信号によ
り被制御装置を有する第1負荷装置を駆動するタ
イマー装置において、電源ラインと上記第1負荷
装置の各被制御装置との間に各々リレーを接続す
ると共に、上記制御信号を発生する制御回路に設
けた複数の制御出力端子と上記各リレーの駆動手
段の入力側とを接続し、上記電源ラインと第2負
荷装置との間にリレーを接続すると共に、上記複
数の制御出力端子のうちの少くとも2以上の該制
御出力端子を上記リレーの駆動手段の入力側に選
択手段を介して接続し、上記複数の第1負荷装置
のうち少くとも2以上の被制御装置の動作時間に
対応して上記第2負荷装置を動作せしめることを
特徴としたタイマー装置。
1. In a timer device that drives a first load device having a controlled device according to a control signal from a control circuit at predetermined set times, a relay is connected between the power supply line and each controlled device of the first load device. At the same time, a plurality of control output terminals provided in the control circuit that generates the control signal are connected to the input side of the driving means of each of the relays, and a relay is connected between the power supply line and the second load device. At least two of the plurality of control output terminals are connected to the input side of the driving means of the relay via a selection means, and at least two of the plurality of first load devices are connected to the input side of the driving means of the relay. A timer device characterized in that the second load device is operated in accordance with the operating time of the controlled device.
JP13959478A 1978-11-10 1978-11-10 Timer unit Granted JPS5565184A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13959478A JPS5565184A (en) 1978-11-10 1978-11-10 Timer unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13959478A JPS5565184A (en) 1978-11-10 1978-11-10 Timer unit

Publications (2)

Publication Number Publication Date
JPS5565184A JPS5565184A (en) 1980-05-16
JPS6111391B2 true JPS6111391B2 (en) 1986-04-02

Family

ID=15248896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13959478A Granted JPS5565184A (en) 1978-11-10 1978-11-10 Timer unit

Country Status (1)

Country Link
JP (1) JPS5565184A (en)

Also Published As

Publication number Publication date
JPS5565184A (en) 1980-05-16

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