JPS6113305B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sector clock detection scheme in a rotating magnetic memory device.

A conventional sector clock generation method will be described with reference to FIGS. 1 and 2.

FIG. 1 shows an outline of the general structure of a rotating magnetic memory device, and FIG. 2 shows an example of the principle waveform of clock generation.

In FIG. 1, a clock track 2 and a plurality of data tracks 3 are located on the circumference of the surface of a rotating magnetic recording medium 1.
are arranged, and a clock head 4 and a data head 5 are provided corresponding to each track. In such a device, an index signal written on clock track 2 and a timing signal following this are used as timing signals for recording information on data track 3 or reproducing information from data track 3. is read out by the clock head 4, amplified and shaped by the clock amplifier 6, and then a sector clock is generated by the sector clock discrimination circuit 7 and the master clock generation circuit 8. Here, the sector clock is a clock pulse that is generated a plurality of times during one revolution in order to divide one revolution of the track into desired data lengths.

By the way, in the conventional clock generation method, as shown in FIG.
A “1” NRZ waveform 9 is recorded, a continuous “0” NRZ waveform 10 is recorded in the sector clock section, and the continuous “0” portion of the sector clock logic waveform 11 that is converted into logic from this waveform is mastered. clock 1
A sector clock of 13 was generated by counting at 2. This method has the disadvantage that noise tends to occur in the "0" NRZ waveform 10, and this noise clears the counter, leading to erroneous discrimination of the sector clock.

The object of the present invention is to discriminate the phase inversion of all "1"s using a phased locked clock synchronized with the clock track, thereby creating a sector clock that has sufficient redundancy against incorrect discrimination due to noise, peak shifts, etc. The purpose is to provide a generation method.

In order to achieve the above object, the present invention
Write 1-bit “0” to the clock section, and
The magnetization phase of all "1"s before and after the clock section is reversed, and this is distinguished by counting the phase reversal time using a phased lock clock synchronized with the clock track, and noise and peaks within 1 to 2 bits are detected. It is characterized by providing redundancy against incorrect discrimination caused by the sheet.

Hereinafter, the content of the present invention will be explained in detail with reference to Examples. FIG. 3 shows an example of the contents of a signal according to the present invention, and FIG. 4 shows an example of a concrete implementation circuit.

A clock track output 14 containing a 1-bit sector "0" field 15 for each sector is written in advance on the clock track, and at the same time,
It is assumed that a phased locked clock 16 is made that is synchronized with this clock track output 14.

In FIG. 4, the phase inversion discriminator 23 has a data input terminal D to which the clock track output 14 is input, and a trigger input terminal T to which the phased lock clock 16 is input. The phase inversion discriminator 23 performs inversion every time the "0" sector portion 15 of the clock track output 14 arrives. even·
Counter 24 counts phased locked clock 16 and is initialized and cleared by the Q output _S7 of counter distributor 27. Odd counter 25 also counts phased locked clock 16, and initialization and clearing are conditioned by _S8 of counter distributor 27. The counter distributor 27 is set by an initial set pulse 29 at the start of operation,
The Q output _S5 of the sector clock presetter 26 is input to its trigger input terminal T and is inverted. The sector clock presetter 26 receives the outputs S ₃ of the even counter 24 and the odd counter 25,
S ₄ is set via the OR gate G ₃ , and its output S ₅ is input to the data input terminal D of the sector clock generator 28 and at the same time to the trigger terminal T of the counter distributor 27 . Sector clock generator 28 receives phased locked clock 16 at tri-input terminal T, generates sector clock 22 at its Q output, and generates sector clock 22 at output _S6 .
Reset the clock presetter 26.

Now, when the "0" sector part (high pulse) 15 of the clock track output 14 arrives at the data input terminal D of the phase inversion discriminator 23, the phased
It is inverted at the rising edge of locked clock 16, and a high pulse _S1 is generated at the Q output. At this time, the counter distributor 27 is set by the initial set pulse 29, and a high pulse _S7 is generated at its Q output, which is input to the AND gate _G1 . On the other hand, since the Q output S ₁ of the phase inversion discriminator 23, which is another input of the AND gate G ₁ , is also a high pulse, a low pulse is input to the reset terminal R of the even counter 24, and this even counter 24 has a high clear signal. Therefore, it is never cleared. or,
It will not be cleared even by a single noise. Therefore, the clock track output 14 is “0”.
The even counter 24 starts counting the phased locked clock 16 due to the inversion of the sector portion 15 from low to high. If the phased locked clock 16 continues to be inverted by 4 bits or more, the even counter 24 outputs the ²² output S3, which sets the sector clock presetter ₂₆ and then the sector clock generator 28 to start the sector clock. A clock 22 is generated. The counter distributor 27 is the output of the sector clock presetter 26.
Triggered by _S5 , it is inverted, the low pulse of its Q output _S7 resets the even counter 24, and the high pulse of output _S8 sets the odd counter 25 on standby so that it will be reset at the next phase inversion. .

Next, the next “0” of clock track output 14
When the sector section (high pulse) 15 arrives, the phase inversion discriminator 23 is inverted, a high pulse is output to the output S ₂ , the AND of the AND gate G ₂ is removed, and a low pulse is input to the reset input terminal R of the odd counter 25 . Ru. Otsudo counter 25 is also not cleared because it is high clear. It is not cleared even by isolated noise. Therefore, by inverting the "0" sector portion 15 of the clock track output 14 from high to low, the odd counter 2
5 starts counting phased lock clock 16. The subsequent operation is the same as that of the even counter 24 described above.

Here, to touch on redundancy, if in the above state, noise causes the phase inversion discriminator 23
Even if the bit is reversed, the next bit always returns to the original state. Therefore, erroneous discrimination will not occur unless noise of 4 consecutive bits or more occurs. Again, even if the waveform of the “0” sector portion 15 undergoes a peak shift due to adjacent magnetization interference, from the next “0” sector portion 15,
Since all phases are inverted, there will be some bit shift, but no erroneous discrimination will occur.

As described above, according to the present invention, it is possible to obtain a highly reliable sector clock with sufficient margin against noise, Peter shift, etc.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of the general configuration of a rotating magnetic memory device, FIG. 2 is a waveform diagram of a conventional sector clock generation method, FIG. 3 is a waveform diagram of a signal according to the present invention, and FIG. FIG. 1 is a block diagram showing one embodiment of the present invention. 14...Clock/track output, 15...
"0" sector section, 16...phased locked clock, 22...sector clock, 23
... Phase inversion discriminator, 24 ... Even counter, 25 ... Odd counter, 26 ... Sector clock presetter, 27 ... Counter distributor, 28 ... Sector clock generator.

Claims (1)

[Claims] 1. In a rotating magnetic memory device having a clock track, one bit of "0" is written on the clock track where the sector clock is obtained by a frequency modulation method, and all "1"s are written before and after that, and the clock track is 1. A sector clock generation method, characterized in that the 1-bit "0" is discriminated by one edge of a phase detection clock obtained by phase detection of a clock, and a sector clock is generated.