JPS6113320B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a specific configuration of a semiconductor memory test circuit incorporated in a semiconductor memory device formed into a semiconductor integrated circuit. The following describes an example of a fuse-type bipolar PROM (programmable read-only memory). First, regarding Figure 1, the 1x4 bit configuration
The basic configuration of PROM and its basic operation will be explained. In the figure, 1 is a power terminal, 2 is a ground terminal,
3 is a first input terminal to which input signal A is input, 4 is a second input terminal to which input signal B is input, 5 is an output terminal for memory read signal X, and 6 and 7 are inverters that sequentially invert input signal A. , 8 and 9 are inverters that sequentially invert the input signal B; 10,
11, 12 and 13 are logical products, respectively.
AND circuits 14, 15, 16 and 17 for a decoder to obtain A. , 19, 20, and 21 are inserted in the emitter circuits of transistors 14, 15, 16, and 17, respectively. 22, 23, 24, and 25 are inserted in series with fuses 18, 19, 20, and 21, respectively, and when the fuses are cut, 26 is a collector resistor connected between the commonly connected collectors of transistors 14 to 17 and power supply terminal 1;
7 is an emitter resistor connected between the common connection side terminal of the fuses 18 to 21 and the ground terminal 2, and 28 is an output inverter to which the voltage drop across the emitter resistor 27 is input. Inverters 6 to 9 and
AND circuits 10 to 13 constitute a decoder circuit. In the circuit shown in FIG. 1, when both input signals A and B have a logic value of "0" (hereinafter, logic values are simply expressed as "1" and "0"), the output of the AND circuit 10 is "1".
The transistor 14 becomes conductive, and the fuse 1
8 is selected. Next, when the input signal A is "1" and the input signal B is "0", the output of the AND circuit 11 becomes "1", the transistor 15 becomes conductive, and the fuse 19 is selected. Similarly, when input signal A is "0" and input signal B is "1", fuse 20 is selected, and when both input signals A and B are "1", fuse 21 is selected. 1st
Although not shown in the figure, fuse-type PROM
has a built-in writing circuit, and the user writes information (programming) by cutting off any one of the fuses 18 to 21. Therefore, in an unwritten state, all the fuses 18 to 21 are connected, and in this case, regardless of whether the input signals A and B are "1" or "0", the emitter resistor 26 is connected to the collector resistor 26.
7, the input level of the output inverter 28 becomes "1", and the output X to the output terminal 5 becomes "0". If the fuse 18 is disconnected, when the input signals A and B are both "0" and the fuse 18 is selected, the current flowing through the emitter resistor 27 will be immediately cut off, so the input level of the output inverter 28 will be reduced. becomes “0” and the output X to output terminal 5 is “1”
becomes. In this way, information can be programmed to any address by cutting the desired fuse on the user's side. The above is the basic operation of fuse type PROM. In this way, since PROM is used by writing desired information on the user side, the fuse cannot be cut off on the manufacturer side. That is, in FIG. 1, inverters 6 to 9 and AND circuit 1 are connected without cutting fuses 18 to 21.
It is necessary to test the operation of the decoder circuit consisting of transistors 0 to 13 and the output circuit consisting of transistors 14 to 17. Therefore, manufacturers add dummy memory cells (hereinafter referred to as dummy cells) and use these to test the operation in an unwritten state. Figure 2 is a connection diagram during the above operation test to explain the dummy cell for 2-bit PROM.
Diodes 31 and 32 and fuse 33
Using a dummy cell 100 [including an emitter resistor 29], the output X becomes "0" when the input signal A is "0", and the output X becomes "1" when the input signal A is "1". , the fuse selected by transistor 15 has been removed. By using such dummy cells, desired operation tests can be performed. In the dummy cell 100, the fuse 3 is connected to the column selected by the transistor 14.
3 was left, but this was removed and transistor 1
A similar operation test can be performed using a dummy cell with a fuse left in the column selected in step 5. Figure 3 shows this dummy cell 100 as a 4-bit
In the connection diagram during the operation test applied to PROM, the first dummy cell 100a is the dummy cell 100 in Fig. 2.
The second dummy cell 100b has a similar structure, but consists of diodes 34 and 35 and a fuse 36. However, in this configuration, the relationship between input signal A, input signal B, and output signal X is as follows.

【table】

【table】

【table】

【table】

[Table] In other words, Table 1 shows the operation pattern during normal operation, Table 2 shows the operation pattern when the output of inverter 6 is fixed at "0", output of inverter 7 is fixed at "1", and Table 3 shows the operation pattern when the output of inverter 6 is fixed at "1". Table 4 shows that when the output of inverter 8 is fixed at "0" and the output of inverter 9 is fixed at "1", Table 5 shows that the output of inverter 8 is "1" and the output of inverter 9 is "0".
This is the operation pattern at the time of failure that is fixed. As described above, there is a problem in that the cases shown in Table 4 and the cases shown in Table 5 cannot be distinguished from normal operation. Therefore, Fig. 4 is a connection diagram during an operation test in which a dummy cell is applied to a 4-bit PROM to improve this point.
A third dummy cell 100c is used instead of cell 00b. That is, instead of fuse 36 in the column selected by transistor 16, fuse 37 is left in the column selected by transistor 17. With this configuration, the relationship between input signals A and B and output signal X is as follows.

【table】

【table】

【table】

【table】

[Table] In other words, Table 6 shows the operation pattern during normal operation, and Table 7 shows the operation pattern during a failure when the output of inverter 6 is fixed at "0" and the output of inverter 7 is fixed at "1", as in Table 2. Table 8 shows the inverter 6 as well as Table 3.
In the event of a failure, the output of inverter 8 is fixed at "1" and the output of inverter 7 is fixed at "0", as in Table 4, Table 9 shows that the output of inverter 8 is fixed at "0" and the output of inverter 9 is fixed at "1". At the time of a fixed failure, Table 10 shows that the output of inverter 8 is "1" and the output of inverter 9 is "1", as in Table 5.
This is an operation pattern at the time of a failure in which the output of is fixed to "0". Furthermore, in the event of a failure in which the outputs of inverters 6 and 7 are both fixed at "0", or both the outputs of inverters 8 and 9 are fixed at "0", or the outputs of inverters 6 to 9 are all fixed at "0", the output X is always "0". 1", and in the event of a failure, the outputs of inverters 6 and 7 are both "1", or the outputs of inverters 8 and 9 are both "1", or the outputs of inverters 6 to 9 are all fixed to "1". X is always "0". In this way, by providing a dummy cell as shown in FIG. 4, it becomes possible to test the operation of the decoder circuit and the output circuit. Figure 5 is a connection diagram showing the entire circuit in which a dummy cell is added to the circuit in Figure 1 to enable the manufacturer to test its operation before shipping.
is a switch that is connected to the dummy cell side during an operation test, and connected to the opposite memory element side after the test, and is actually formed of a semiconductor element. That is, the structure of the dummy cell may be formed according to the following rules. address (memory column)
If there are two columns, one column is set to “1” and the other column is set to “0.” Generally, when there are 2 ⁿ columns, the first column is set to “1” and the other column is set to “0.”
The configuration from the 2nd ^n-1th column to the 2nd ^{n-1th column may be the same as that in the case where all the memory columns are 2n-1} columns, and the configuration from the 2nd ^n-1 +1st column to the 2nd ^nth column may be reversed. Figure 6 is a configuration diagram showing an example of a dummy cell in the case of 16 bits (16 memory columns).
200-215 are transistors 14-1 in FIG.
The first column to the 16th column are driven by transistors corresponding to 7, and 216 to 231 are diodes inserted in each column to prevent current leakage, and fuses are connected to the 1st and 4th columns according to the above rules. ,6,7,10,
232, 233, 2 in rows 11, 13 and 16 respectively
34, 235, 236, 237, 238 and 2
39 are provided. Of course, an inverted pattern configuration may be used in which fuses are not provided in these columns and fuses are provided in other columns. Now, the circuit in Figure 5 is number 7 on the pattern drawing.
The result will be as shown in the figure. In FIG. 7, 101 is a location where inverters 6 to 9 and AND circuits 10 to 13 are placed, and 102 is a location where an output circuit is placed.
Generally the columns are arranged in order, transistors 14-
17 are arranged in sequence. By the way, usually
The wiring patterns connected to the emitters of the transistors 14 to 17 are extremely narrow, with a mutual spacing of about 4 to 7.5 μm, and as the memory capacity increases, the wiring length becomes longer (several mm). The probability of short circuit occurring is very high. For example, even if the wires of the emitters of transistors 15 and 16 are short-circuited, the failure cannot be detected at output X because there are no fuses in any of these columns of dummy cells. For the same reason, in the 16-bit configuration shown in FIG.
5 and 206, columns 207 and 208, column 20
Even if there is a wiring short circuit in any of columns 9 and 210 and columns 213 and 214, this dummy cell cannot detect it. This disadvantageous tendency becomes more pronounced as the memory capacity increases. FIG. 8 is a circuit diagram for explaining the conventional means for detecting the wiring short circuit. In addition to the circuit shown in FIG. and dummy cell 100d with fuses 43 to 46 connected
The fuses 43 to 46 were sequentially cut off one by one to check for the wiring short circuit. However, 6 bits of X direction address information (number of addresses
64), Y direction address information 6 bits (number of addresses
For a 4kbits PROM with 64), 128 fuses must be disconnected in sequence; for a 16kbits PROM, the number is 256. This not only requires a large amount of testing time, but also has the drawback of increasing the memory chip size. This invention was made in view of the above-mentioned points. Wiring short circuits occur between adjacent wiring lines, and in the conventional dummy cells shown in FIGS. 5 to 7, the rows with fuses are Because wiring short circuits that occur in adjacent lines or lines without fuses cannot be detected, lines with fuses and lines without fuses should be arranged alternately. By doing so, it is an object of the present invention to provide a semiconductor memory device that has a simple configuration and can be tested before shipping without increasing the memory chip size. FIG. 9 is a circuit diagram showing an embodiment in which the present invention is applied to the circuit of FIG. 5. FIG. 10 is a pattern layout diagram of the output section in this embodiment corresponding to FIG. 7. As shown, the electrical connections are kept exactly the same as in FIG. 5, but by changing the arrangement of AND circuits 12 and 13, transistors 16 and 17, and the third and fourth columns of dummy cells, respectively. There are no consecutive rows without fuses or rows with fuses, so that even a wiring short circuit can be reliably detected. for example,
When a short circuit occurs between the emitters of adjacent transistors 15 and 16 in the configurations of FIGS. 5 and 7, the relationship between input signals A and B and output signal X is as shown in Table 11. Although it cannot be distinguished from the normal operation pattern shown in Table 6, the
When a short circuit occurs between the emitters of transistors 15 and 17 adjacent to each other in the configuration shown in FIG. 0, the relationship between input signals A and B and output signal X is as shown in Table 12, and the short circuit can be detected.

【table】

[Table] Furthermore, in the case of 16 bits as shown in Figure 6, change the arrangement order of the 1st to 16th columns appropriately,
By arranging rows with fuses and rows without fuses alternately, it is possible to detect short circuits between adjacent wires. Therefore, there is no need to provide a special dummy cell for detecting wiring short circuits as shown in FIG. 8, thereby improving inspection efficiency and reducing memory chip size. In the above embodiment, data is given to the dummy cell depending on the presence or absence of a fuse, but data can also be given in other ways, such as by removing the diode. We also have more fuse type bipolar
I explained about PROM, but it is a diode destruction type.
PROM, fuse type and diode destruction type
It can be applied to PLA as well as testing rewritable PROMs such as EPROM and EAROM. Of course, the way data is given to the dummy cells differs depending on each case. As detailed above, the present invention keeps the chip size of the memory device small by adding ingenuity to the write information and physical arrangement of dummy cells provided for shipping tests of destructive programmable semiconductor memory devices. In addition, a semiconductor memory device in which the above test can be efficiently performed can be realized.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the basic configuration of a PROM with a 1 x 4 bit configuration, Figure 2 is a connection diagram showing a conventional example in which dummy memory cells are applied to a 2-bit PROM, and Figure 3 is a circuit diagram showing the basic configuration of a PROM with a 1 x 4 bit configuration. ×4 bit PROM
4 is a connection diagram showing a conventional example applied to the circuit of FIG. 3, FIG. 5 is a connection diagram showing the conventional example of FIG. 4 together with the original memory cell, Figure 6 is a configuration diagram of a dummy memory cell when there are 16 memory columns, Figure 7 is a pattern diagram of the output section of the circuit in Figure 5, and Figure 8 is a conventional means for detecting wiring short circuits. A circuit diagram for explanation, FIG. 9 is a circuit diagram showing an embodiment of the present invention, and FIG.
The figure is a pattern diagram of the output section. In the figure, 3 and 4 are address input terminals, and 6 to
9 is an inverter that forms part of the address decoder; 10 to 13 are AND circuits that form part of the address decoder; 14 to 17 are transistors that drive each memory column; 18 to 21 are memory cells;
3 and 37 are dummy memory cells. In addition,
The same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A read device having a plurality of memory cell rows having memory cells in an unwritten state so that arbitrary memory contents can be written and used on the user side, and an address decoder for selecting any of the above memory cell rows. In the dedicated semiconductor memory device, when the number of the memory cell arrays in which dummy memory cells are provided for each memory cell array is two, the first
Information “1” (or “0”) is written to the dummy memory cell in the column, information “0” (or “1”) is written to the dummy memory cell in the second column, and generally the number of columns in the memory cell column is When is ²ⁿ , the dummy memory cells from the first column to the second ^2-1 column have an information pattern that is equal to the information pattern of each dummy memory cell when the number of memory cell columns is 2n ^-1. is written, and an inverted information pattern of the above information pattern is written in the dummy memory cells from the 2nd ^n-1+ 1st column to the 2nd ^nth column, and the physical arrangement of each memory cell column is changed to the above column number order. A semiconductor memory device characterized in that the write information of the dummy memory cells in each column is inverted between adjacent columns.