JPS6113378B2 - - Google Patents
Info
- Publication number
- JPS6113378B2 JPS6113378B2 JP7056480A JP7056480A JPS6113378B2 JP S6113378 B2 JPS6113378 B2 JP S6113378B2 JP 7056480 A JP7056480 A JP 7056480A JP 7056480 A JP7056480 A JP 7056480A JP S6113378 B2 JPS6113378 B2 JP S6113378B2
- Authority
- JP
- Japan
- Prior art keywords
- ribbon
- electrode
- semiconductor element
- electrodes
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
- H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
この発明は、電極を一主面に有する半導体素子
の電極とリード導体との接続方法を改良すること
によつて生産性の向上と集積度の改善を図つた半
導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor device that improves productivity and integration by improving the connection method between the electrodes and lead conductors of a semiconductor element having an electrode on one main surface. It is related to.
以下、高周波回路に用いるシヨツトキバリア形
電力用電界効果トランジスタ(以下、「高出力
SBFET」と呼ぶ」を例に取つて説明する。 Below, we will discuss short-barrier type power field effect transistors (hereinafter referred to as "high-power field effect transistors") used in high-frequency circuits.
This will be explained using an example of "SBFET".
第1図は従来の高出力SBFETの一例の平面図
である。従来の高出力SBFETは、第1図に示す
ように、半導体基体1の一主面上にソース電極
2、ゲート電極3およびドレイン電極4の三種類
の電極を交互に多数配列した構造を有している。
そして、ボンデイングワイヤ5によつて、複数個
のソース電極2同士またはソース電極2とパツケ
ージのソースボンデイングエリア6とが電気的に
接続されている。ゲート電極3同士またはゲート
電極3とパツケージのボンデイングエリア7およ
びドレイン電極4同士またはドレイン電極4とパ
ツケージのドレインボンデイングエリア8につい
ても同様である。10は半導体基体1、ソース電
極2、ゲート電極3およびドレイン電極4によつ
て構成された半導体素子である。 FIG. 1 is a plan view of an example of a conventional high-output SBFET. As shown in FIG. 1, a conventional high-power SBFET has a structure in which a large number of three types of electrodes, a source electrode 2, a gate electrode 3, and a drain electrode 4, are arranged alternately on one main surface of a semiconductor substrate 1. ing.
The bonding wires 5 electrically connect the plurality of source electrodes 2 to each other or the source electrodes 2 and the source bonding area 6 of the package. The same applies to the bonding area 7 between the gate electrodes 3 or between the gate electrode 3 and the package, and the drain bonding area 8 between the drain electrodes 4 or between the drain electrodes 4 and the package. 10 is a semiconductor element constituted by a semiconductor substrate 1, a source electrode 2, a gate electrode 3, and a drain electrode 4.
このような高出力SBFETにおいて、出力電力
を増大させるためには配列数を増やす必要があ
り、その場合、第1図に示すような従来の構成で
は、ボンデイングワイヤ5の数が増加することか
ら、ボンデイング作業時間が増大し生産性が低く
なると言う問題があつた。 In such a high-output SBFET, in order to increase the output power, it is necessary to increase the number of arrays, and in that case, in the conventional configuration shown in FIG. 1, the number of bonding wires 5 increases. There was a problem that bonding work time increased and productivity decreased.
また、電極寸法は、ボンデイングワイヤの線径
に依存しているため、減少させるのに限界があ
り、集積度が低い欠点があつた。 Furthermore, since the electrode dimensions depend on the wire diameter of the bonding wire, there is a limit to how much they can be reduced, and there is a drawback that the degree of integration is low.
この発明は、上記の点に鑑みてなされたもので
あり、ほぼ同一平面上にある複数のリボン状導電
体と、複数の電極が突起状をなして一主面上に配
列された第1および第2の半導体素子とを具備
し、第1の半導体素子と第2の半導体素子とが電
極配列面を内方に向けて互いに対向しており、第
1の半導体素子と第2の半導体素子との間に前記
各リボン状導電体の一部が挟まれて第1および第
2の半導体素子の前記各突起状電極が前記複数の
リボン状導電体のいずれかに接着されている構造
とすることによつて、生産性の向上と集積度の改
善を図つた半導体装置を提供することを目的とし
たものである。 The present invention has been made in view of the above points, and includes a plurality of ribbon-shaped conductors that are substantially on the same plane, and a first and second electrode that has a plurality of protruding electrodes arranged on one principal surface. a second semiconductor element, the first semiconductor element and the second semiconductor element face each other with electrode arrangement surfaces facing inward, and the first semiconductor element and the second semiconductor element A part of each of the ribbon-shaped conductors is sandwiched between them, and each of the protruding electrodes of the first and second semiconductor elements is adhered to any of the plurality of ribbon-shaped conductors. The object of the present invention is to provide a semiconductor device with improved productivity and degree of integration.
以下、実施例に基づいてこの発明を説明する。
第2図はこの発明の構成要件の一つである半導体
素子の一例であつて高出力SBFETを示す斜視
図、第3図は第2図の半導体素子の複数組の相対
応する突起電極上にそれぞれ一つのリボン状導電
体を接着させた状態を示す斜視図、第4図は複数
のリボン状導電体の上面にもそれぞれ他の半導体
素子の複数組の相対応する電極を接着させた状態
を示す斜視図である。第2図〜第4図において、
第1図と同一符号は第1図にて示したものと同様
のものを表わしている。10aは第1の半導体素
子、10bは第2の半導体素子、21,31およ
び41はそれぞれソース電極2、ゲート電極3お
よびドレイン電極4の所要部分を厚くして形成し
たソース突起電極、ゲート突起電極およびドレイ
ン突起電極、51,52および53は金リボン線
などからなりそれぞれ複数のソース突起電極2
1、ゲート突起電極31およびドレイン突起電極
41に接着した第1、第2および第3のリボン状
導電体である。 The present invention will be explained below based on examples.
FIG. 2 is a perspective view showing a high-output SBFET, which is an example of a semiconductor device that is one of the constituent elements of the present invention, and FIG. FIG. 4 is a perspective view showing a state in which one ribbon-like conductor is adhered to each of the ribbon-like conductors, and FIG. FIG. In Figures 2 to 4,
The same reference numerals as in FIG. 1 represent the same components as shown in FIG. 10a is a first semiconductor element, 10b is a second semiconductor element, and 21, 31, and 41 are source protrusion electrodes and gate protrusion electrodes formed by thickening required portions of the source electrode 2, gate electrode 3, and drain electrode 4, respectively. and drain protrusion electrodes 51, 52, and 53 are made of gold ribbon wires, etc., and each have a plurality of source protrusion electrodes 2.
1, first, second and third ribbon-shaped conductors bonded to the gate protrusion electrode 31 and the drain protrusion electrode 41;
上記の高出力SBFETの製作方法の一例のこの
発明の要点に関連のある主要工程を次に説明す
る。 The main steps related to the main points of the present invention in one example of the method for manufacturing the above-mentioned high-output SBFET will be described next.
まず、第2図に示すように、従来と同様の方法
により内部にソース領域、ゲート領域、ドレイン
領域などの機能領域が形成され一主面にソース電
極2、ゲート電極3およびドレイ電極4が形成さ
れた半導体素子の各電極の所要部分をメツキなど
によつて肉盛りしてソース突起電極21、ゲート
突起電極31およびドレイン突起電極41を形成
して第1の半導体素子10aとする。次に、第3
図に示すように、第1、第2および第3のリボン
状導電体51,52,53をそれぞれ複数個のソ
ース突起電極21、ゲート突起電極31およびド
レイン突起電極41上に接着させてリード導体を
形成する。つづいて、第1の半導体素子1aと同
一の構成を有する第2の半導体素子10bを作製
し、第4図に示すように、そのソース突起電極2
1、ゲート突起電極31およびゲート突起電極4
1をそれぞれ第3図に示す状態の第1、第2およ
び第3のリボン状導電体51,52,53の上面
に接着させることによつて、実施例の高出力
SBFETが完成する。 First, as shown in FIG. 2, functional regions such as a source region, a gate region, and a drain region are formed inside using a method similar to the conventional method, and a source electrode 2, a gate electrode 3, and a drain electrode 4 are formed on one main surface. Required portions of each electrode of the semiconductor element thus prepared are built up by plating or the like to form a source protrusion electrode 21, a gate protrusion electrode 31, and a drain protrusion electrode 41 to form the first semiconductor element 10a. Next, the third
As shown in the figure, first, second, and third ribbon-shaped conductors 51, 52, and 53 are bonded onto a plurality of source protruding electrodes 21, gate protruding electrodes 31, and drain protruding electrodes 41, respectively, to form lead conductors. form. Subsequently, a second semiconductor element 10b having the same configuration as the first semiconductor element 1a is manufactured, and as shown in FIG.
1. Gate protrusion electrode 31 and gate protrusion electrode 4
1 to the upper surfaces of the first, second and third ribbon-shaped conductors 51, 52, 53 in the state shown in FIG.
SBFET is completed.
上記のように構成された実施例の高出力
SBFETでは、電極配列を増大した場合において
も、複雑なワイヤボンデイング作業を必要としな
いため、従来装置と比較して生産性が大幅に向上
する。さらに、実施例装置では、複数の同一種類
の電極の突起電極を一括してリボン状導電体に接
着させるため、電極寸法の減少が可能であり、集
積度が向上し、従来装置より小形化できる利点を
有している。 High output of the embodiment configured as above
SBFETs do not require complicated wire bonding operations even when increasing the electrode array, resulting in significantly improved productivity compared to conventional equipment. Furthermore, in the example device, since the protruding electrodes of multiple electrodes of the same type are bonded to the ribbon-shaped conductor all at once, the electrode dimensions can be reduced, the degree of integration is improved, and the device can be made smaller than the conventional device. It has advantages.
上記の製造工程では、二つの半導体素子とリボ
ン状導電体との接着を個々に実施したが、両方の
半導体素子の間にリボン状導電体を挾んで同時に
接着させても、同様の構造が得られる。 In the above manufacturing process, the two semiconductor elements and the ribbon-shaped conductor were bonded individually, but the same structure can be obtained even if the ribbon-shaped conductor is sandwiched between both semiconductor elements and bonded at the same time. It will be done.
また、上記の実施例では、この発明を高出力
SBFETに適用した場合について述べたが、この
発明は、これに限定されるものでなく、バイポー
ラトランジスタ、MOSトランジスタ、各種のダ
イオードなどにも適用することができるものであ
る。 In addition, in the above embodiment, the present invention is applied to high output power.
Although the case where the present invention is applied to an SBFET has been described, the present invention is not limited thereto, and can also be applied to bipolar transistors, MOS transistors, various types of diodes, and the like.
さらに、上記の実施例においては、2個の同一
種類の半導体素子をリボン状導電体の両主面に同
一種類の電極を相対応させて接着させた場合につ
いて述べたが、複数個の種類の異なる半導体素子
を混在させてリボン状導電体の両主面に接着させ
てもよい。 Furthermore, in the above embodiment, a case was described in which two semiconductor elements of the same type were bonded to both main surfaces of a ribbon-shaped conductor with electrodes of the same type corresponding to each other. Different semiconductor elements may be mixed and adhered to both main surfaces of the ribbon-shaped conductor.
以上説明したように、この発明による半導体装
置は、ほぼ同一平面上にある複数のリボン状導電
体と、複数の電極が突起状をなして一主面上に配
列された第1および第2の半導体素子とを具備
し、第1の半導体素子と第2の半導体素子とが電
極配列面を内方に向けて互いに対向しており、第
1の半導体素子と第2の半導体素子との間に前記
各リボン状導電体の一部が挟まれて第1および第
2の半導体素子の前記各突起状電極が前記複数の
リボン状導電体のいずれかに接着されている構造
としているので、複雑なワイヤボンデイング作業
が不要となるから、生産性の向上および集積度の
改善が可能となり、実用上大きな利点を有する。 As explained above, the semiconductor device according to the present invention includes a plurality of ribbon-shaped conductors that are substantially on the same plane, and a plurality of first and second electrodes that are arranged in a projection shape on one main surface. the first semiconductor element and the second semiconductor element face each other with their electrode arrangement surfaces facing inward, and there is a gap between the first semiconductor element and the second semiconductor element. Since the structure is such that a part of each of the ribbon-shaped conductors is sandwiched and each of the protruding electrodes of the first and second semiconductor elements is adhered to one of the plurality of ribbon-shaped conductors, it is not complicated. Since wire bonding work is not required, productivity can be improved and the degree of integration can be improved, which has a great practical advantage.
第1図は従来の高出力SBFETの一例の平面
図、第2図はこの発明の構成要件の一つである半
導体素子の一例であつて高出力SBFETを示す斜
視図、第3図は第2図の半導体素子にリボン状導
電体を接着させた状態を示す斜視図、第4図は本
発明の一実施例の外観を示す斜視図である。
図において、1は半導体基体、2はソース電
極、3はゲート電極、4はドレイン電極、10
a,10bは半導体素子、21はソース突起電
極、31はゲート突起電極、41はドレイン突起
電極、51,52,53はリボン状導電体であ
る。なお、図中同一符号はそれぞれ同一または相
当部分を示す。
FIG. 1 is a plan view of an example of a conventional high-output SBFET, FIG. 2 is a perspective view of a high-output SBFET, which is an example of a semiconductor element that is one of the components of the present invention, and FIG. FIG. 4 is a perspective view showing a state in which a ribbon-shaped conductor is adhered to the semiconductor element shown in the figure, and FIG. 4 is a perspective view showing the appearance of an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a source electrode, 3 is a gate electrode, 4 is a drain electrode, and 10
10b are semiconductor elements, 21 is a source protrusion electrode, 31 is a gate protrusion electrode, 41 is a drain protrusion electrode, and 51, 52, and 53 are ribbon-shaped conductors. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
と、複数の電極が突起状をなして一主面上に配列
された第1および第2の半導体素子とを具備し、
第1の半導体素子と第2の半導体素子とが電極配
列面を内方に向けて互いに対向しており、第1の
半導体素子と第2の半導体素子との間に前記各リ
ボン状導電体の一部が挟まれて第1および第2の
半導体素子の前記各突起状電極が前記複数のリボ
ン状導電体のいずれかに接着されていることを特
徴とする半導体装置。1 comprising a plurality of ribbon-shaped conductors that are substantially on the same plane, and first and second semiconductor elements in which a plurality of electrodes are arranged in a protrusion shape on one main surface,
A first semiconductor element and a second semiconductor element face each other with electrode arrangement surfaces facing inward, and each ribbon-shaped conductor is disposed between the first semiconductor element and the second semiconductor element. A semiconductor device, wherein each of the protruding electrodes of the first and second semiconductor elements is adhered to one of the plurality of ribbon-shaped conductors with a portion sandwiched therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7056480A JPS56167342A (en) | 1980-05-26 | 1980-05-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7056480A JPS56167342A (en) | 1980-05-26 | 1980-05-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56167342A JPS56167342A (en) | 1981-12-23 |
| JPS6113378B2 true JPS6113378B2 (en) | 1986-04-12 |
Family
ID=13435154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7056480A Granted JPS56167342A (en) | 1980-05-26 | 1980-05-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56167342A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10948899B2 (en) | 2017-06-14 | 2021-03-16 | Fanuc Corporation | Motor controller that uses an acceleration/deceleration time constant of the motor |
-
1980
- 1980-05-26 JP JP7056480A patent/JPS56167342A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10948899B2 (en) | 2017-06-14 | 2021-03-16 | Fanuc Corporation | Motor controller that uses an acceleration/deceleration time constant of the motor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56167342A (en) | 1981-12-23 |
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