JPS6113607B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram branching method in an information processing apparatus that performs microprogram control.

FIG. 1 is a block diagram illustrating a conventional microprogram branching system for an information processing apparatus that employs a microprogram control system. In the figure, 1 is a control storage that stores microprograms, 2 is a data register (hereinafter referred to as CSDR) that sets microinstructions, and 5 is an address register (hereinafter referred to as CSAR) that sets the address to be read from the control storage. , 3 is a resource (for example, an arithmetic unit) in the information processing device controlled by the microinstruction, and 4 is a logic circuit (hereinafter referred to as a test matrix) that examines information from the resource 3 in order to determine the branch address of the microinstruction to be executed next. ).

CSAR the microinstruction address to be executed next
When set to 5, the specified microinstruction is read from CS1 and stored in CSDR2.
The BA part in CSDR2 is the upper bit of the address of the next microinstruction, and the upper part 5-
Set to A. The T part in CSDR2 is called a branch field (test field), and is a branch field (test field).
are input to the test matrix 4 together with the output line group 100. The test matrix 4 is specified by the branch field section T, and the output line group 100 of the resource 3 is
Check the status of predefined signal lines from among
The result is set in lower bit 5-B of CSAR5. That is, in FIG. 1, the specified contents of the output line group 100 of the resource 3 are reflected in the next instruction address via the test matrix 4 by specifying the T part in the CSDR 2, thereby making it possible to branch the microprogram. There is. Part A in CSDR2 is BA
It is a general term for microinstruction fields other than the part and T part, and is used to control the transfer between the arithmetic control registers of the arithmetic unit.
It performs memory control, etc., and consists of multiple independent microinstruction fields.

FIG. 2 is also a block diagram explaining the conventional microprogram branching method. This is a microinstruction control method called a bank control method, and the control storage 1 has multiple banks (in the example of FIG. 2, two banks). ), and microinstructions are read simultaneously from banks 0, 1-A and banks 1, 1-B according to the address set by CSAR5. In this method, the output of test matrix 4 under the control of branch field section T of CSDR2 is
It is input to the input gate section of CSDR2, not to CSAR5, and is input to bank 1 of control storage 1.
1 of the microinstructions read from -A, 1-B
Select one and set it to CSDR2.

The difference between FIG. 1 and FIG. 2 is that in FIG. 1, the output of the test matrix 4 is directly input to the address register 5 that accesses the control storage itself, whereas in FIG. The point is to select read data from CS1 of multiple banks. As the machine cycle of the processing device improves, the time occupied by the control storage access time within the machine cycle increases, but even if you add the judgment time of test matrix 4 and the access time of control storage 1, Note that the first method is used for machines with sufficient machine cycle time, and the second method is used for machines that do not have sufficient machine cycle time.
The method shown in the figure is used.

Now, of the conventional microinstruction branching method described above, consider the case of FIG. 2, in which the time allocated to one machine cycle is taken as an example. Now, as one resource in the microinstruction controlled part 3 shown in FIG.
Assume a main adder and shifter in a computing unit as shown in FIG. In Figure 3, 6, 7,
8 and 9 are registers A, B, C, and D, and data specified by the instruction at the start of the instruction is set from a data input path (not shown). The data in this register group 6-9 is applied to the main adder 10 to shifter 12, the result of the operation is set in the output latch 11-13 of each arithmetic unit, and then the contents of this register are returned to the registers 6-9. In the case of the example shown in FIG. 3, it is necessary to include the time for the contents of the register groups 6 to 9 to return to the register groups 6 to 9 via the main adder 10 to the shifter 12 within the standard machine cycle of the processing device. Also, in Figure 2
The microinstruction read into the CSDR 2 controls the data output from the register groups 6 to 9 until they are returned to the register groups 6 to 9.

FIG. 4 shows the time allocation between the control storage section shown in FIG. 2 and the calculation section shown in FIG. 3. Fourth
In the figure, one microinstruction in _E0 cycle controls the data from registers 6, 7, 8, and 9 through the arithmetic unit until it returns to registers 6, 7, 8, and 9 in time zone X. . That is, input data is set in registers 6, 7, 8, and 9 at time T ₀ at the beginning of time period It is assumed that register groups 6, 7, 8, and 9 are set at T ₀ later. At this time, the set timing of CSDR2 is determined as follows. Main adder 1
Which of the register groups 6, 7, 8, and 9 should the input data to shift 0 to shift 12 be input from _?
must be determined. In order to make such a decision at this time, the setting timing of CSDR2 is determined after a time period sufficient to decode the corresponding microinstruction. In FIG. 4, it is assumed that this decoding time requires 1/2 cycle. CSAR5 settings are CSDR2 for the amount necessary to access control storage.
is determined before the set time of . In Fig. 4, 3/4 cycle is assumed.

Next, consider the influence of the operation result of E ₀ cycle on microinstruction branch control. Referring to FIGS. 2 and 4, the operation result of the E ₀ cycle is transferred to the micro instruction of the next cycle E ₂ after E 0 under the control of _the branch field section T of the micro instruction E ₁ next to the E ₀ cycle. Involved in determining orders. In other words, when the specified operation of _E0 cycle starts execution in X time period, 1/
After 2 cycles have passed, the E ₁ cycle microinstruction is set in CSDR2. Then, the branch field T part of CSDR2 is input to the test matrix 4,
E The calculation result of ₀ cycles is judged at the end of X time period, and the judgment result is 1/1 from the end of X time period.
After two cycles have elapsed, that is, by the time when the microinstruction controlling the _E2 cycle is set, the data is sent for switching the input data bus of CSDR2.

The above is an explanation of the microprogram control method shown in FIG. 2 and its operating time. 1st
In the case of the figure, the output result of test matrix 4 is
It is exactly the same except that reading of the control storage begins after input to CSAR5.
Therefore, as mentioned above, if there is sufficient margin for control storage access with respect to the machine cycle, the method shown in Figure 1 is used, and if there is not, the method shown in Figure 2 is used.
The method shown in the figure will be adopted. The following explanation will be based on the system shown in FIG. 2, but even if it is applied to the system shown in FIG. 1, the present invention will not be impeded in any way.

By the way, recent high-integration semiconductor technology (LSI)
With the advancement of technology, the number of logic circuits accommodated per unit mounting area is increased, thereby reducing the signal propagation delay due to wiring between logic circuits within a machine cycle, and thereby improving the machine cycle of information processing equipment. has become possible. On the other hand, it is possible to improve the performance of processing equipment by shortening the machine cycle and increasing the amount of data that can be processed per cycle. Even with high-density semiconductor technology, a considerable amount of mounting space must still be available.

Applying this to the apparatus having the configurations shown in FIGS. 2 and 3, first, the arithmetic units shown in FIG. 3 are placed in close proximity because it is necessary to process a large amount of data within a standard machine cycle. Similarly, the control storage and peripheral storage shown in Figure 2
CSAR, CSDR, etc. are also installed in a nearby implementation area in order to make storage access time follow machine cycles. Furthermore, the control logic circuitry that controls the portions of FIGS. 2 and 3 will be located in adjacent areas.

As is well known, arithmetic units pass through a large number of logic circuit stages within a unit time, and control storage requires long wiring due to the need to drive a large number of storage elements using address register outputs. The close proximity arrangement and use of highly integrated logic circuit elements are beneficial in reducing wiring delays and thereby improving machine cycles. However, it is difficult to expect that the wiring between logic configuration units placed in these adjacent areas will be reduced at the same rate as the wiring length expected for the arithmetic unit and control storage section.
As an example of such a place, refer to Figure 2.
Examples include the output of the microinstruction field A part of the CSDR 2 and the test condition signal line group 100 which is the input to the test matrix 4. The former is distributed to various resources scattered within the mounting space in order to control the resources of each part of the device, and the latter is conversely necessary to receive signals from various scattered resources, so the input and output signal lines are Since there are many connections in and out, and there are variations in the implementation of the other units, the rate of reduction in the wiring length of the signal line is low compared to the reduction in wiring length achieved in the arithmetic unit section and control storage mentioned above. have.

Based on the above premise, time allocation within the standard machine cycle will be considered with reference to FIG. If the time required for the data to return from the registers 6, 7, 8, 9 shown in Fig. 3 to the registers 6, 7, 8, 9 via the arithmetic unit is taken as a reference machine cycle, then the CSDR2 shown in Fig. 2 is set with enough time to issue a control signal to select the input data of the arithmetic unit, but as mentioned earlier, it is important to note that the delay due to the wiring length will not reach the reduction rate that can be achieved within the arithmetic unit. Taking this into consideration, the microinstruction decoding time that required 1/2 cycle in FIG. 4 will require an additional 3/4 cycle in FIG. 5. CSAR5 may be set earlier than the setting time of CSDR2 by an amount sufficient for storage access, but the following problem occurs in controlling the branch field T in the _E1 cycle following the _E0 cycle. That is, if you try to determine the microinstruction branch destination of E2 cycle in the microinstruction branch field of _E1 cycle based on the operation result of _E0 cycle using the _same settings as shown in FIG.
Since the setting of CSDR2 is earlier than that of FIG. 4, the time margin for the calculation result of the _E0 cycle to reach the set time of CSDR2 of the _E2 cycle via the test matrix 4 is reduced. Furthermore, considering that the reduction rate of the wiring delay of the test condition signal line group 100 of the test matrix 4 is lower than that of a logic unit that can be mounted in the adjacent mounting area such as an arithmetic unit, the calculation result of E ₀ cycle is no longer It becomes impossible to send by the fixed time of CSDR2 of _E2 cycle.

Conventionally, such problems have been solved by the following methods. The first method is to prohibit updating of the resource to be tested in the immediately preceding cycle in a situation where the above problem occurs. That is, in FIG. 5, it is prohibited to test the calculation result in the E ₀ cycle in the E ₁ cycle. The second method is to delay the start time of the next instruction by one cycle by specifying a microinstruction, and then use the CSDR from the operation result.
This method prolongs the time it takes to determine the

In other words, the operation result of _E0 cycle in Figure 5 can be specified in _E1 cycle, but the CSDR _{determination} time of _E2 cycle due to the specification of the E1 cycle microinstruction is delayed by one cycle (but Therefore, the E _1- cycle operation is also delayed by 1 cycle).

By the way, the resources for which test branching is prohibited immediately after an update are limited to a portion of all test cases, so the impact on the performance of the device was small, but if the wiring delay of the test condition signal line group becomes severe, Most tests become unworkable immediately after the update. In such a situation, if the test immediately after updating the resource is prohibited as in the past, it becomes impossible to update the resource every cycle due to branch judgment, and device performance will be significantly impaired.

Therefore, an object of the present invention is to perform the following steps in determining a microinstruction branch immediately after updating a resource in a processing device.
It is an object of the present invention to provide a method that makes it possible to update a resource every cycle and make a branch judgment even when there is no time to judge the status of an updated resource.

Simply put, the feature of the present invention is that when testing the status of resources in a device, the output of the resource is not immediately input to the test matrix, but by installing a suitable delay latch, the resource is updated and tested every cycle. It is possible.

FIG. 6 shows a configuration diagram of an embodiment of the present invention. In the figure, 2 is a CSDR, 3 is a resource group of a processing unit controlled by microinstructions, and 4 is a test matrix. Although omitted in FIG. 6, the configuration of the control storage is the same as that in FIG. 2, and is composed of a plurality of banks. Therefore, the branch field part T of CSDR2 is input to the test matrix 4, and its output selects one of the multiple microinstructions read from the control storage, and selects it as the next cycle's microinstruction. Set to CSDR2.
The above is the same as the conventional technology.

A feature of the present invention is the delay latch on test condition signal line 100, shown at 14. That is, corresponding to FIG. 2, in FIG. 2, the test conditions output from the resource group 3 to the test condition signal line group 100 are directly input to the test matrix 4, but
In the figure, the delay latch group 14 is set once. By installing the delay latch 14, when testing the updated resource information in the next cycle, there is no need to prohibit updating of the same resource in the next cycle as in the past.

The above pattern will be explained with reference to FIG. In FIG. 7, it is assumed that a resource updated in X time zone is tested in Z time zone two times ahead, and that the same resource updated in X is also updated in the next Y time zone. E ₀ , E ₁ , and E ₂ in the figure correspond to microinstruction steps that control the X, Y, and Z time periods. Now, the resource status updated in the X time period is stored in the delay latch 14 in the Y time period. Since the branch field T part of the _E2 cycle refers to this delay latch 14, it is allowed to update the same resource in the Y time zone as it was updated in the X time zone. Furthermore, since it takes more than one machine cycle to communicate the resources updated in the X time zone to the Z time zone, a sufficient amount of time can be taken for branching conditions.

Next, points to be considered when installing the delay latch 14 will be described.

Test conditions Delay latch 1 of signal line group 100
4 must change state in synchronization with the execution cycle of the microinstruction. In Figure 7,
Let us assume that the _E2 microinstruction cannot be executed immediately in the Z time period immediately after the _E1 microinstruction is executed in the Y time period. Something like this, for example, the E ₂ cycle required a stretch operand, but
This occurs when the operand does not arrive by the start time of the Z time zone. In this case, in Z time zone
E Since the execution of the _two- cycle microinstruction is not performed, the contents of the CSDR cannot be updated as shown during the Z time period. If it is updated, Z
If an E _2- cycle microinstruction is permitted after the time period, there will be no E ₂ -cycle microinstruction in the CSDR. Therefore, it is necessary to update the CSDR only during a time period in which execution of microinstructions in a specified cycle is permitted.

Returning to the function of the delay latch 14 _{, in FIG. 7, the update result by the E 0 cycle} microinstruction in time zone The update result is loaded into the delay latch in time zone Z.

Now, if the _E2 cycle cannot be executed in the Z time zone, referring to Figure 7, the setting of the next microinstruction in the _E2 cycle to CSDR will be after the Z time zone. When the contents of the delay latch 14 are updated, when the next cycle after the _E2 cycle is stored in the CSDR after the Z time period, the information referenced by the test matrix will not be the result of the _E0 cycle but the result of the _E1 cycle. Become. Therefore, the loading of delay latch 14, which takes place during the Z time period, must be done when the _E2 cycle is ready to execute. Furthermore, the synchronization of the execution cycles may be performed not with respect to the delay latch 14 but with respect to the test matrix.

In carrying out the present invention, some branching conditions must be changed from conventional ones. For example, in a case where a microprogram that forms a loop subtracts the value of a counter and exits the loop by recognizing in the test conditions that the counter value has reached a predetermined value, the counter is updated every time the loop is executed. In order to implement the present invention in a case where cycles are performed, test conditions are changed from those of the conventional case. In other words, if the conventional test condition was to reduce the value of the counter by "1" and break out of the loop when the value reached "1", in the present invention, the counter value is "2". It is necessary to change it so that it does not get out of the loop. This is because the provision of the test condition delay latch causes a difference between the counter value at the time of test condition determination and the counter value set in the test condition delay latch at the branch determination time.

By the way, when assembling a microprogram, there are some points where the next operation cannot be executed until the determination result of the test conditions is clear. When the present invention is implemented, it is necessary to issue an extra microinstruction for one cycle in order to test the state of the resource by a microprogram after the resource is updated, which is preferable from the viewpoint of effective use of control storage. do not have. As mentioned above, in such cases, there has conventionally been a method of delaying the start of execution of the next instruction by one cycle by specifying a microinstruction.

However, this method cannot be immediately applied to the present invention. That is, in the present invention, either the delay latch of the test condition or the output of the test matrix must be synchronized with the execution cycle. Therefore, applying the conventional method,
Although the machine cycle of the next instruction is delayed, the trigger pulse for synchronizing the delay latch or the machine cycle of the test matrix is also delayed, so that its contents cannot be changed.

In consideration of the above points, an embodiment of the present invention that enables testing using microinstructions immediately after resource update will be described with reference to FIGS. 8 and 9. FIG. 8 shows the control latch that manages the progression of microinstructions and the two-bit control latch introduced by the present invention. FIG. 9 shows a time chart for explaining the operation of FIG. 8.

In Figure 8, latch (A) 105 and latch (B) 1
06 generates control signals that manage the progress of the microprogram, and all resources under the control of the microprogram are connected to these latches 10.
When 5,106 becomes "1", it is allowed to change its state. Normally, during operation, signal line 10
1 becomes "1", and the outputs of latches 105 and 106 become "1". However, if it is necessary to stop the execution of the microinstruction, the latches 105 and 106 are reset by setting the signal line 101 to "0". be done. The latch (W) 107 inputs the signal line 102, which is one of the decoding lines for the microinstruction, and becomes "1" when it is desired to suppress the execution of the next instruction in the microinstruction. The output of latch 107 is latch 10
6 and the AND circuit 108, and then
It is input to the latch 104 via the inversion circuit 109, and the execution of the next instruction of the specified cycle is delayed by one cycle. This is the same as in the conventional case, and FIG. 9 shows this when the next cycle inhibition is specified by the _E1 cycle microinstruction.

Returning to FIG. 8, 110 is a newly added latch (WD). Latch 110 is latch 10
9 and latch 106 becomes "1", and a pulse is generated with the phase shown in FIG. The output of latch 110 is ORed by latch 106 and OR circuit 111, and is led to signal line 103.
The output of signal line 103 is used as a trigger signal for test condition delay latch 14 or the output latch of test matrix 4 in FIG. That is, the signal line 103 makes it possible to stop the next instruction for one cycle and update the contents of the test matrix 4 or the test condition delay latch 14 one cycle ahead.

Referring to FIG. 9, the information from the resource updated in time zone X is triggered by latch (A) 105 and set in delay latch 14 when the _E1 cycle is executed in time zone Y. Then E ₁
When a cycle's microinstruction instructs to stop the execution of the next cycle, latch (W) 107 becomes "1", and latch 105 and latch 1 in the Z time period
06 is suppressed. On the other hand, since the test condition delay latch 14 in FIG. 6 is triggered by the latch (WD) 110 via the signal line 103, the resource status updated in the Y time period can be reflected in the delay latch 14 during the Z time period. I can do it. By the time the microinstruction of the _E2 cycle is executed after the Z time period, the contents of the delay latch 14 are already available to test the state of the _E1 cycle.

As explained above, according to the present invention, in a microprogram-controlled processing device, the time within a machine cycle is sufficient to check the status of an internal resource updated by the microprogram using the branch field of the microinstruction immediately after the update. Even in situations where there is not enough margin, by installing a test condition delay latch and connecting the test condition to the next cycle, microinstruction branches can be made without causing a drop in machine cycles. It is possible to improve the performance of the device.

[Brief explanation of the drawing]

1 and 2 are conventional configuration diagrams of the microprogram branching method, FIG. 3 is a diagram showing an example of resources controlled by microinstructions, and FIGS. 4 and 5 are diagrams of the conventional microprogram branching method. Figure 6 showing a time chart for explaining the operation
7 is a diagram showing a time chart for explaining the operation of FIG. 6, and FIG. 8 is a trigger signal generation circuit for applying to a test condition delay latch according to the present invention. FIG. 9 is a diagram showing a time chart for explaining the operation of FIG. 8. 1... Control storage, 2... Micro instruction data register, 3... Resource group, 4... Test matrix, 5... Control storage/address register, 14... Test condition delay latch, 100... Test condition signal line group.

Claims (1)

[Scope of Claims] 1. The state of a resource controlled by a microinstruction in an information processing device is set as an input to be tested in a test circuit, and the test circuit selects an input to be tested specified in a test field of the microinstruction; In a microprogram branching method that determines whether to branch a microprogram based on its state, a latch circuit that temporarily stores the state of the resource is provided, and after the latch circuit delays the state of the resource for a certain period of time, A microprogram branching method characterized by using the input to be tested of a test circuit. 2. In the microprogram branching method according to claim 1, the execution of the next microinstruction is delayed by one cycle according to the designation of the microinstruction, and only the latch circuit is updated, and the microprogram branch decision is made. A microprogram branching method characterized by: