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JPS6115628B2 - - Google Patents
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JPS6115628B2 - - Google Patents

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Publication number
JPS6115628B2
JPS6115628B2 JP3532180A JP3532180A JPS6115628B2 JP S6115628 B2 JPS6115628 B2 JP S6115628B2 JP 3532180 A JP3532180 A JP 3532180A JP 3532180 A JP3532180 A JP 3532180A JP S6115628 B2 JPS6115628 B2 JP S6115628B2
Authority
JP
Japan
Prior art keywords
switch
screen
channel selection
screens
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3532180A
Other languages
Japanese (ja)
Other versions
JPS56132069A (en
Inventor
Minoru Ueda
Masaaki Fujita
Kazumi Kawashima
Hirosuke Yamamoto
Hidekazu Taira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3532180A priority Critical patent/JPS56132069A/en
Publication of JPS56132069A publication Critical patent/JPS56132069A/en
Publication of JPS6115628B2 publication Critical patent/JPS6115628B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/44Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/45Picture in picture, e.g. displaying simultaneously another television channel in a region of the screen

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Description

【発明の詳細な説明】 本発明は1つの陰極線管を1画面、2画面、4
画面に切替えて使用することができる選局装置に
関するものであり、通常のチヤンネル選局スイツ
チの他に3つのスイツチを設けることによつて種
の選局状態を得ることができる選局装置を提供し
ようとするものである。
Detailed Description of the Invention The present invention allows one cathode ray tube to be used for one screen, two screens, four screens, etc.
This relates to a channel selection device that can be used by switching to a screen, and provides a channel selection device that can obtain various channel selection states by providing three switches in addition to a normal channel selection switch. This is what I am trying to do.

以下本発明の実施例について図面を参照して説
明する。
Embodiments of the present invention will be described below with reference to the drawings.

第1図はその一実施例であり、選局装置はカウ
ンタとデコーダを用い、選局電圧取出用にプリセ
ツト・ボリウムを用いた周知のプリセツト・ボリ
ウム式選局装置である。この選局装置は12局分の
選局が可能であるものとすると、リセツト信号に
より選局ポジシヨンは1になり、1つのチヤンネ
ル、アツプ信号CHuにより選局ポジシヨンは1
つアツプする。12ポジシヨンが受信されている場
合にアツプ信号が入ると1ポジシヨンが受信され
るものである。
FIG. 1 shows one example of this, and the tuning device is a well-known preset volume type tuning device using a counter and a decoder, and a preset volume for extracting the tuning voltage. Assuming that this channel selection device is capable of selecting 12 stations, the reset signal sets the channel selection position to 1, and the channel selection position changes to 1 by the up signal CHu.
tsutsuup. If an up signal is received when 12 positions are being received, 1 position will be received.

選局回路1,2,3,4が前述したプリセツ
ト・ボリウム方式の選局回路であり、5,6,
7,8はチユーナを含む受信回路で、各々の選局
回路によりコントロールされる。9は分配器で、
アンテナ10からのRF信号を分配し各々の受信
回路のRF入力端子に導く。
Tuning circuits 1, 2, 3, and 4 are the aforementioned preset volume type tuning circuits;
7 and 8 are receiving circuits including tuners, which are controlled by respective tuning circuits. 9 is a distributor,
The RF signal from the antenna 10 is distributed and guided to the RF input terminal of each receiving circuit.

11は選局スイツチで1ch〜12chはチヤン
ネルの直接選局用スイツチ、Aは4画面スイツ
チ、Bは2画面スイツチ、Cは入替スイツチ、D
は解除スイツチである。
11 is a channel selection switch, channels 1 to 12 are direct channel selection switches, A is a 4-screen switch, B is a 2-screen switch, C is a replacement switch, D
is a release switch.

12は、選局回路1,2,3,4を制御するた
めのコントローラで、マイクロコンピユータであ
る。
12 is a controller for controlling the channel selection circuits 1, 2, 3, and 4, and is a microcomputer.

今ここで、直接選局スイツチの1chを閉じる
と、コントローラ12中のチヤンネル判別手段2
3で1chの選局が指示されたことを判別し、リセ
ツトパルス発生手段24とチヤンネルアツプパル
ス発生手段25とを制御して第2図aに示すリセ
ツト出力Reset、チヤンネル・アツプ出力CHu
1,CHu2,CHu3,CHu4を出力する。この
場合、選局回路1にはリセツト信号Resetが入る
が、チヤンネル・アツプ信号CHu1は出ないの
で第1ポジシヨンが選局される。選局回路2は、
リセツト信号Resetとチヤンネル・アツプ信号
CHu2が1発入るので第2ポジシヨンが選択さ
れる。同様に、選局回路3は第3ポジシヨン、選
局回路4は第4ポジシヨンが選択される。
Now, if you close channel 1 of the direct channel selection switch, the channel discrimination means 2 in the controller 12
3, it is determined that channel 1 selection has been instructed, and the reset pulse generating means 24 and channel up pulse generating means 25 are controlled to generate the reset output Reset and channel up output CHu shown in FIG. 2a.
1. Output CHu2, CHu3, CHu4. In this case, the reset signal Reset is input to the tuning circuit 1, but the channel up signal CHu1 is not output, so that the first position is selected. The channel selection circuit 2 is
Reset signal Reset and channel up signal
Since CHu2 enters once, the second position is selected. Similarly, the third position is selected for the channel selection circuit 3, and the fourth position is selected for the channel selection circuit 4.

2ch〜12chの選局キーが閉じられた場合も選局
回路1は選局キーと同じポジシヨンが選択され、
選局回路2,3,4は1つづつ大きなポジシヨン
が選択される。この場合の各々の波形を第2図
b,c,d,e,f,g,h,i,j,k,lに
示す。ここで明らかなように選局回路1が第10ポ
ジシヨンの場合、選局回路2は第11ポジシヨン、
選局回路3は第12ポジシヨン、選局回路4は第1
ポジシヨンが選択される。即ち第12ポジシヨンが
最大であり、最大ポジシヨンの次はまた第1ポジ
シヨンから選択される。
Even when the channel selection keys from 2ch to 12ch are closed, the same position as the channel selection key is selected for the channel selection circuit 1,
In the channel selection circuits 2, 3, and 4, the larger positions are selected one by one. The respective waveforms in this case are shown in FIG. 2 b, c, d, e, f, g, h, i, j, k, and l. As is clear here, when the tuning circuit 1 is in the 10th position, the tuning circuit 2 is in the 11th position,
Tuning circuit 3 is at the 12th position, and tuning circuit 4 is at the 1st position.
A position is selected. That is, the 12th position is the maximum, and the next position after the maximum position is also selected from the first position.

ここで説明したように、選局スイツチは1組だ
けで4つの選局回路を選局することができる。
As explained here, only one set of tuning switches can select four tuning circuits.

受信回路5,6,7,8を出た映像信号は切替
スイツチ13に加えられる。この切替スイツチ1
3は第3図cに示すように4つの入力を取出して
メモリー14に蓄積し、これを読み出して陰極線
管15に4画面を出すか、第3図bに示すように
受信回路5の信号と、受信回路6の信号をメモリ
ー16に蓄積し、これを読み出して陰極線管15
に2画面を出すか、あるいは第3図aに示すよう
に受信回路5の出力を陰極線管15に1画面を出
すかを切替えるものである。この切替スイツチ1
3は、たとえば第4図に示すような論理回路で構
成される。この切替はメモリー17よりの出力信
号a,b,cによつて行なわれる。
The video signals output from the receiving circuits 5, 6, 7, and 8 are applied to a changeover switch 13. This changeover switch 1
3 extracts four inputs and stores them in the memory 14, as shown in FIG. 3c, and reads them out to display four screens on the cathode ray tube 15, or outputs the signals from the receiving circuit 5 as shown in FIG. 3b. , the signals from the receiving circuit 6 are stored in the memory 16, read out and transmitted to the cathode ray tube 15.
It is used to switch between displaying two screens on the display, or outputting one screen from the output of the receiving circuit 5 to the cathode ray tube 15 as shown in FIG. 3a. This changeover switch 1
3 is composed of a logic circuit as shown in FIG. 4, for example. This switching is performed by output signals a, b, and c from the memory 17.

スイツチA,B,C,Dよりの信号はコントロ
ーラ12内の検出回路18に加えられ、スイツチ
Aが押されたかBが押されたか、Cが押された
か、Dが押されたかを検出する。Aが押されたと
きメモリー17にその事実を蓄積し、出力aを出
して受信回路5,6,7,8の出力がメモリー1
4に入るように切替スイツチ13を切替える。A
が押されたと伝う信号Aは比較回路19にも加え
られている。このとき、選局回路1,2,3,4
で1チヤンネル、2チヤンネル、3チヤンネル、
4チヤンネルが選局されていると、陰極線管15
の画面に第3図cに示す4画面が得られる。次に
Aスイツチを再び押すと、検出回路18で再びA
が検出され比較回路19で前回のAと比較され、
チヤンネルアツプパルス発生手段25を制御して
選局回路1,2,3,4にすべて4つのパルスを
加える。この結果第3図cの4画面は5,6,
7,8チヤンネルを選局することになる。以後A
スイツチを押す毎に4画面は4チヤンネルづつ変
化する。
Signals from switches A, B, C, and D are applied to a detection circuit 18 in the controller 12 to detect whether switch A, B, C, or D has been pressed. When A is pressed, the fact is stored in memory 17, output a is output, and the outputs of receiving circuits 5, 6, 7, and 8 are stored in memory 1.
4. Change the changeover switch 13 so that it enters 4. A
A signal A indicating that has been pressed is also applied to the comparator circuit 19. At this time, the tuning circuits 1, 2, 3, 4
1 channel, 2 channel, 3 channel,
When channel 4 is selected, cathode ray tube 15
The four screens shown in FIG. 3c are obtained. Next, when the A switch is pressed again, the detection circuit 18
is detected and compared with the previous A in the comparison circuit 19,
The channel up pulse generating means 25 is controlled to apply four pulses to all the channel selection circuits 1, 2, 3, and 4. As a result, the four screens in Figure 3c are 5, 6,
I will be selecting channels 7 and 8. From now on A
Each time you press the switch, the 4 screens change by 4 channels.

次に、この状態でスイツチBを押すと、検出回
路18でBが検出されメモリー17にBが蓄積さ
れる。するとbに出力が出て切替スイツチ13は
受像回路1と2の出力を直接径路20およびメモ
リー16を通つて陰極線管15に加え、第3図b
に示す二画面が得られる。比較回路19ではAと
Bが比較されるので出力は出ない。次に再びスイ
ツチBを押すと比較回路19でBと前回のBとが
比較され、比較信号によつて受像回路2のみに出
力を加え第3図bの小画面のチヤンネル2のみを
3チヤンネルにする。以後スイツチBを押す毎に
第3図bの小画面のチヤンネルが1つづつ増加す
る。
Next, when switch B is pressed in this state, B is detected by the detection circuit 18 and B is stored in the memory 17. Then, an output is output to b, and the selector switch 13 applies the outputs of the image receiving circuits 1 and 2 directly to the cathode ray tube 15 through the path 20 and the memory 16, and outputs the output to the cathode ray tube 15 as shown in FIG.
The two screens shown are obtained. Since the comparison circuit 19 compares A and B, no output is produced. Next, when switch B is pressed again, B is compared with the previous B in the comparison circuit 19, and the comparison signal is used to output only to the image receiving circuit 2, changing only channel 2 of the small screen in Figure 3b to channel 3. do. Thereafter, each time switch B is pressed, the channel on the small screen shown in FIG. 3b increases by one.

第3図bに示すようにチヤンネル1とチヤンネ
ル2の画面が出ている状態において、スイツチC
が押されたとき、検出回路18でCが検出され、
メモリー17のメモリー内容BがCに変化する。
メモリー17の蓄積内容Cになつた場合には切替
スイツチ13にCと前回の蓄積内容Bとを比較し
て得られた信号がcラインを通つて加えられ、受
信回路5の出力をメモリー16へ、受信回路6の
出力を直接径路20へ加わるように切替える。こ
の結果、第3図bの画面の状態が入れ替ることに
なる。
With the channels 1 and 2 displayed as shown in Figure 3b, switch C
When is pressed, the detection circuit 18 detects C,
The memory content B of the memory 17 changes to C.
When the stored content of the memory 17 reaches C, a signal obtained by comparing C with the previous stored content B is applied to the changeover switch 13 through the c line, and the output of the receiving circuit 5 is transferred to the memory 16. , the output of the receiving circuit 6 is switched directly to the path 20. As a result, the state of the screen shown in FIG. 3b is switched.

また、第3図cに示す画面状態において、スイ
ツチCを押した場合、Cと前回の蓄積内容Aとが
比較され、パルスが1つ出て各選局回路1,2,
3,4に加えられる。この結果第3図Cの画面の
状態が2〜5チヤンネルとなる。
In addition, when switch C is pressed in the screen state shown in FIG.
Added to 3 and 4. As a result, the state of the screen shown in FIG. 3C becomes 2 to 5 channels.

スイツチDを押すとメモリ17にDが蓄積さ
れ、dに出力が出て受像回路5の出力が直接径路
21を通つて陰極線管15に加わり、第3図aの
1画面となる。1画面の状態でスイツチCを押す
と、比較回路でCとDとが比較されてパルスが出
選局回路1にパルスを1つ加えてチヤンネル2が
選局されるようにする。
When switch D is pressed, D is stored in the memory 17, output is output to D, and the output of the image receiving circuit 5 is directly applied to the cathode ray tube 15 through the path 21, resulting in one screen as shown in FIG. 3A. When switch C is pressed in the state of one screen, C and D are compared in a comparator circuit, and one pulse is applied to channel selection circuit 1 so that channel 2 is selected.

画面の状態が第3図b,cとの状態であつても
スイツチ1ch〜12chが押されると径路22よ
りメモリー17にDが蓄積されるようになつてお
り、画面状態は1画面となる。従つて、スイツチ
Dはあえて設けなくてもスイツチ1chを利用す
ることができる。
Even if the screen state is as shown in FIGS. 3B and 3C, when the switches 1ch to 12ch are pressed, D is stored in the memory 17 through the path 22, and the screen state becomes one screen. Therefore, switch 1ch can be used without intentionally providing switch D.

以上のように本発明によれば1組のチヤンネル
スイツチと三つのスイツチA,B,Cを設けるだ
けで、1画面、2画面、4画面の状態をチヤンネ
ル送り動作も含め実現することもできるものであ
る。
As described above, according to the present invention, by simply providing one set of channel switches and three switches A, B, and C, it is possible to realize 1-screen, 2-screen, and 4-screen states, including channel forwarding operations. It is.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例における選局装置のブ
ロツク線図、第2図a,b,c,d,e,f,
g,h,i,j,k,lは同装置説明のための波
形図、第3図a,b,cは同装置の画面の状態を
示す平面図、で第4図はその切替スイツチ13の
具体回路図である。 11……選局スイツチ、12……コントロー
ラ、1,2,3,4……選局回路、5,6,7,
8……受信回路、13……切替スイツチ、14,
16,17……メモリー、15……陰極線管、2
0,21……直接径路、19……比較回路、18
……検出回路、A,B,C……スイツチ。
Fig. 1 is a block diagram of a channel selection device in an embodiment of the present invention, Fig. 2 a, b, c, d, e, f,
g, h, i, j, k, l are waveform diagrams for explaining the device, Fig. 3 a, b, c are plan views showing the state of the screen of the device, and Fig. 4 is the changeover switch 13. FIG. 11...Tuning switch, 12...Controller, 1, 2, 3, 4...Tuning selection circuit, 5, 6, 7,
8... Receiving circuit, 13... Selector switch, 14,
16, 17...Memory, 15...Cathode ray tube, 2
0, 21... Direct path, 19... Comparison circuit, 18
...Detection circuit, A, B, C...Switch.

Claims (1)

【特許請求の範囲】[Claims] 1 チユーナを含む4つの受信回路と、これらの
受信回路に選局電圧を与えるものであつて、パル
スが1つ加えられるごとにチヤンネルが1つ増加
するように制御する4つの選局回路と、上記4つ
の受信回路の出力を入力信号とし、陰極線管画面
に1画面、2画面、あるいは4画面を映出するよ
うに切替える切替スイツチと、複数の直接選局用
スイツチ、4画面スイツチ、2画面スイツチ、入
替スイツチ、解除スイツチを持つ選局スイツチ
と、上記直接選局用スイツチの任意のものを操作
することによつて上記4つの選局回路にそれぞれ
異なる数のパルスを与えてそれぞれ異なるチヤン
ネルを選局するように制御し、4画面スイツチ、
2画面スイツチ、解除スイツチの操作によつて上
記切替スイツチを制御して陰極線管画面に4画
面、2画面、1画面を映出するように制御し、か
つ上記入替スイツチの操作によつて2画面時画面
を入替え、4画面時チヤンネルを1つ送るように
制御するコントローラとを備えたことを特徴とす
る選局装置。
1 four receiving circuits including tuners; four tuning circuits that apply tuning voltage to these receiving circuits and control the number of channels to increase by one each time one pulse is applied; A changeover switch that uses the outputs of the four receiving circuits as input signals to display one, two, or four screens on the cathode ray tube screen, multiple direct channel selection switches, a four-screen switch, and a two-screen switch. By operating any one of the channel selection switch, which has a switch, exchange switch, and release switch, and the above-mentioned direct channel selection switch, a different number of pulses are applied to each of the four channel selection circuits to select a different channel. Control to tune, 4 screen switch,
By operating the 2-screen switch and release switch, the changeover switch is controlled to display 4 screens, 2 screens, and 1 screen on the cathode ray tube screen, and by operating the changeover switch, the changeover switch is controlled to display 4 screens, 2 screens, and 1 screen. A channel selection device characterized by comprising: a controller that controls to change the time screen and send one channel when 4 screens are displayed.
JP3532180A 1980-03-19 1980-03-19 Channel selection device Granted JPS56132069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3532180A JPS56132069A (en) 1980-03-19 1980-03-19 Channel selection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3532180A JPS56132069A (en) 1980-03-19 1980-03-19 Channel selection device

Publications (2)

Publication Number Publication Date
JPS56132069A JPS56132069A (en) 1981-10-16
JPS6115628B2 true JPS6115628B2 (en) 1986-04-25

Family

ID=12438541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3532180A Granted JPS56132069A (en) 1980-03-19 1980-03-19 Channel selection device

Country Status (1)

Country Link
JP (1) JPS56132069A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2534985B2 (en) * 1985-12-28 1996-09-18 ソニー株式会社 Television receiver

Also Published As

Publication number Publication date
JPS56132069A (en) 1981-10-16

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