JPS6116999B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic musical instrument using digital technology, and more particularly to an electronic musical instrument capable of generating musical tones having fixed formant characteristics. The applicant of the present application previously proposed an electronic musical instrument that utilizes digital technology and is capable of simultaneously producing a large number of musical tones with a simple configuration. For example, patent application Japanese 52-
No. 150895, the title of the invention "Electronic Musical Instrument" is one example, and the outline of the invention is as follows. 1st
The figure shows its configuration, and the illustrated electronic musical instrument mainly includes a key switch circuit 1 having a large number of key switches arranged in a matrix and provided corresponding to each key on a keyboard (not shown). A key switch scanning circuit 2 that sequentially scans each key switch of this key switch circuit 1 and outputs a time division multiplexed signal TDM representing the open/closed state of each key switch, that is, the pressed state of each key; A timing signal generation circuit 3 generates a timing signal for controlling the operation of the circuit 2 and the time-division waveform generation circuit 4, which will be described later. A time-division waveform generation circuit 4 that generates a waveform signal (sound source signal or musical tone signal) S in a time-division manner and a time-division multiplexed signal TDM output from the key switch scanning circuit 2 are input, and this signal TDM is delayed by a predetermined time. and a coupler control circuit 30 which weights the delayed signal and the signal TDM in a predetermined manner and outputs this weighted signal (hereinafter referred to as weighted data) K; weighting data K and the time-division waveform generation circuit 4
A multiplier 5 that multiplies the waveform signal S output from the
, an accumulator 6 to which the output signal of the multiplier 5 is input, and which cumulatively adds up the above output signals within one scanning period from the start of one scan to the end of one scan of the key switch circuit 1; A latch circuit 7 that receives and latches the contents of the accumulator 6 at the end of a period, and a D/A that converts the output signal (digital signal) of this latch circuit 7 into an analog signal.
It consists of a converter 8, an amplifier 9 that amplifies the output signal of the D/A converter 8, and a speaker 10 that generates the output signal of the amplifier 9 and a musical tone. The coupler control circuit 30 includes eight shift registers 31 to 38 connected in series, the output side of the key switch scanning circuit 2, and each shift register 31 to 38.
nine weighting circuits 39 to 47 respectively connected to the output side of the weighting circuits 39 to 47;
adder 48 that adds all the output signals K ₁ to _{K 9} of
It consists of Shift register 31, 32, 33, 34, 3
5, 36, 37, and 38 have capacities of 12 stages/1 bit, 7 stages/1 bit, 5 stages/1 bit, 7 stages/1 bit, 5 stages/1 bit, 4 stages/1 bit, and 3 stages/1 bit. A time division multiplexed signal that has 5 stages and 1 bit, is driven by a clock pulse φ, and is input to the first shift register 31.
TDM sequentially on the subsequent shift register side 32 to 38
It is designed to shift the Therefore, at a certain bit time, the first bit of the shift register 31
The time division multiplexed signal TDM input to the stage is
After 12 bit time, the shift register 31
The signal DTDM (signal TDM) is output from the 12th stage and input to the first stage of the next stage shift register 32, and further input to this shift register.
(delayed by 12 bit times) is output from the seventh stage after 7 bit times and input to the first stage of the shift register 33 in the next stage. In this way, after inputting the signal TDM to the coupler control circuit 30, the signal TDM is input to the coupler control circuit 30 and then transferred for a predetermined time by each shift register 31 to 38, that is, 12 bit time, 7 bit time, 5 bit time, 7 bit time, 5 bit time, 4 bit time, 3 bit time, 5 bit time. Each shift register 31 is delayed by bit time.
It is output from ~38. Here, the bit time corresponds to the time slot of the time division multiplexed signal TDM, and one bit time corresponds to the time for one time slot. Each of the weighting circuits 39 to 47 has the same structure, consisting of a slide type changeover switch 49, an encoder 50, and three AND gates 51, 52, and 53. In FIG. 1, only the configuration of the weighting circuit 39 is shown in detail, and other circuits 4
The illustration of the configurations 0 to 47 is omitted. Here, the input terminal of the shift register 31 is a point A, and the output terminals of the shift registers 31 to 38 are B, C, D, E, F,
Name them G, H, and I points. Note that there are 16 feet at point A (hereinafter, feet are indicated by darts).
16′))
9 is connected, similarly B, C, D, E, F,
8', 5 1'/3, 4' at G, H, and I points, respectively.
Weighting circuits 41, 42, 43, 44, 45, 46, and 47 corresponding to 2 2'/3, 2', 1 3'/5, 1 1'/3, and 1' are connected. In the weighting circuit 39, a changeover switch 49
For example, if the switching contact is set to "5", the encoder 50 outputs the 3-bit "101" representing the numerical value "5", that is, the AND gates 51, 53.
A “1” signal is output to the first input terminal of the AND gate 52, and a “0” signal is output to the first input terminal of the AND gate 52. This opens only AND gates 51 and 53, so
The time division multiplexed signal input to point A at this time
If TDM is a "1" signal, the data group "101" representing the numerical value "5" is inputted to the adder 48 from the weighting circuit 39. In this way, the time division multiplexed signal TDM and the delayed signal of the time division multiplexed signal TDM delayed and output from the shift registers 31 to 38 have values corresponding to the setting positions of the changeover switches 49 in each weighting circuit 39 to 47. are weighted and output from weighting circuits 39 to 47 for each foot as 3-bit weighted signals K ₁ to K ₉ for each foot, and sent to an adder 48 . Adder 48 receives these signals.
K ₁ to _{K 9} are added at each bit time and the adder is used as a 6-bit weighted data group to be sent to the multiplier 5.
It is now output to . In the prior electronic musical instrument having the above configuration, the player can freely set the weighting of each foot by appropriately operating the changeover switch 49 provided in each of the weighting circuits 39 to 47, thereby producing various tones. It has the advantage of being able to be synthesized and generate musical tones with a wide variety of tones. However, the same can be said of the human vocal organ, and it is known that the oscillating body part and the resonating body part of the musical instrument are elements that influence the sound emitted when playing a natural musical instrument. The waveform of the sound emitted from such a musical instrument, which has two main parts, an oscillator section and a resonator section, is generally very complex. However, in this case, the waveform itself emitted from the oscillator section is often a relatively simple waveform. For example, the waveform emitted by a bowed stringed instrument such as a violin or ciero is a sawtooth wave, and the waveform emitted by a reed instrument or human voice is a pulse wave. . Even if the pitch of the waveform emitted from this oscillator section changes up or down, the spectrum itself does not change significantly. On the other hand, the reason why the harmonic components of the sound emitted from a specific musical instrument change greatly as the pitch changes is due to the unique fixed filter characteristics of the resonator of the musical instrument. A fixed formant specific to the instrument is given. Therefore, the formant of a musical instrument is determined by the structure and function of the resonating body of the musical instrument, and the unique sound of that musical instrument is formed. For this reason, the resonator part plays a large role. Therefore, it is important to reconsider the characteristics of the oscillating body and resonating body from an acoustic standpoint in electronic musical instruments that artificially produce various sounds of natural musical instruments. . However, since the electronic musical instrument of the prior application does not have a configuration for obtaining the formants of the various musical instruments described above, the electronic musical instrument of the prior application was not sufficient to produce tones similar to those of natural instruments.
That is, in FIG. 1, the time-division waveform generation circuit 4 and the coupler control circuit 30 constitute the oscillator section of the electronic musical instrument of the prior application, and the weighting data K from the coupler control circuit 30 is output from the time-division waveform generation circuit 4. The multiplier 5 multiplies the waveform signal S obtained by the multiplier 5 to obtain a musical tone. However, in this earlier application, a circuit is provided to give the output signal of the multiplier 5 a fixed formant for each type of musical instrument. Therefore, it is not possible to produce various musical instrument sounds. The present invention has been made in consideration of the above circumstances, and its purpose is to sequentially scan a plurality of key switches at a predetermined speed to generate a time-division multiplexed signal indicating the pressed state of a key, and to An electronic musical instrument that time-divisionally generates a waveform signal corresponding to each pitch in synchronization with the key switch scanning, and generates a musical tone signal from this waveform signal and the time-division multiplexed signal, or a plurality of key switches in a predetermined manner. generating a time-division multiplexed signal indicating the pressed state of each key by sequentially scanning at a high speed, and then delaying the time-division multiplexed signal by a predetermined time to generate a plurality of delayed time-division multiplexed signals; weighting the signal and the delayed time-division multiplexed signal to generate a weighted signal corresponding to each foot, and time-divisionally generating a waveform signal corresponding to each pitch in synchronization with the key switch scanning,
It is an object of the present invention to enable an electronic musical instrument that generates a musical tone signal from this waveform signal and the weighted signal to generate musical tones that are very close to various musical instrument sounds and human voice sounds having fixed formant characteristics. Therefore, in the present invention, the electronic musical instrument is provided with a memory storing formant data (numeric data) representing the amplitude level for each frequency (each pitch) in accordance with the desired formant characteristics, and the above-mentioned A musical tone having desired formant characteristics is generated by reading out formant data in synchronization with the waveform signal and controlling the amplitude of the waveform signal in accordance with its frequency using the read out formant data. It is done like this. Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is an overall schematic block diagram showing a first embodiment of an electronic musical instrument according to the present invention. In the figure, a key switch circuit 1, a key switch scanning circuit 2, a timing signal generation circuit 3, a time division waveform generation circuit 4, a multiplier 5', an accumulator 6, a latch circuit 7,
The D/A converter 8, amplifier 9, speaker 10, and coupler control circuit 30' correspond to those shown in FIG. The major difference between the electronic musical instrument shown in Figure 2 and the one shown in Figure 1 is that the ROM functions as the resonator mentioned above.
60 is newly provided. this
The ROM 60 stores formant data (numeric data) FD representing the amplitude level for each frequency corresponding to the formant characteristics of a desired musical instrument sound. The ROM 60 is addressed by the timing signal output from the timing signal generation circuit 3, and outputs formant data FD for each frequency in a time-division manner in synchronization with the waveform signal S output from the time-division waveform generation circuit 4. do. A waveform signal S output from the waveform generation circuit 4,
Formant data FD output from ROM60
The weighting data K output from the coupler control circuit 30' are multiplied by each other at each bit time in a multiplier 5'. As a result, the amplitude level of the waveform signal S is controlled by the formant data FD corresponding to its frequency, so that the generated musical tone has fixed formant characteristics. Hereinafter, this electronic musical instrument will be explained in detail based on FIG. FIG. 3 shows a specific example of the configuration of the electronic musical instrument shown in FIG. In FIG. 3, the key switch circuit 1 contains each key C ₁ to C ₆ of the first to sixth octave from pitch C ₁ to C ₆ (61 keys in total).
It is assumed that 61 key switches are provided, each corresponding to a different key. These 61 keys C ₁
61 key switches corresponding to _C6 are arranged in a matrix in the key switch circuit 1 as shown. That is, the column lines _l1 to _l6 of the key switch circuit 1 correspond to the first to sixth octaves, respectively, and the row lines _L1 to _L12 correspond to the pitch names C, C#, ..., B of each octave. Compatible. For example, a key switch for the first octave key _E1 is disposed at the intersection of the column line _l1 and the row line _L5 . The timing signal generation circuit 3 is driven by a clock pulse φ generated at a predetermined period.
Bit-configured hexadecimal counter 15 (this counter 1
Contents of 5 “0000” to “1011”; Decimal display “0”
- "11" corresponds to each pitch name C to B, respectively) and a 4-bit configuration 10 driven by the bit output signal _N4 of the most significant bit (4th bit) of this decimal counter 15. A decimal counter 16 (contents of this counter 16 "0000" to "1001"; decimal representations "0" to "9" correspond to the 1st to 10th octaves, respectively) and a decimal counter 15
The 1st, 2nd, and 4th bit output signals N ₁ , N ₂ , N ₄ of the decimal counter 16 and the 1st, 4th bit output signals B ₁ , B ₄ of the decimal counter 16 are directly inputted, and the output signals of the decimal counter 15 are directly inputted. The output signal N ₃ of the third bit and the output signal B ₂ of the second and third bits of the decimal counter 16,
B ₃ corresponds to inverters 65, 66,
67, and an AND gate 17 inputted thereto. The output signal of the AND gate 17 is called a signal SYC, and one scanning period, which will be described later, is defined by this signal SYC. In this case, since the counters 15 and 16 constitute a 120-decimal counter, the one scanning period consists of 120 bit times. Each bit output signal N ₁ to _{N 4} of the counter 15
is decoded by the decoder 11 in the key switch scanning circuit 2, and the output terminals O ₁ to _{O 12} of the decoder 11
A "1" signal is output to one of them. For example, when the content of the hexadecimal counter 15 is content 7 (in decimal notation) corresponding to the pitch name G, a "1" signal is output only from the output terminal _C8 of the decoder 11.
The bit output numbers _B1 to _B4 of the decimal counter 16 are:
It is decoded by another decoder 12 in the key switch scanning circuit 2, and its output signal is output as a "1" signal to any one of the column lines _l1 to _l6 of the key switch circuit 1. . The output signals of the row lines L ₁ to _{L 12} of the key switch circuit are input to the first input terminals of corresponding AND gates 13 ₁ to 13 ₁₂ in the key switch scanning circuit 2, respectively. The output terminal O ₁ of the decoder 11 is connected to each second input terminal of the AND gates 13 ₁ to 13 ₁₂ .
~O ₁₂ output signals are input respectively. Further, the output signals of the AND gates 13 ₁ to 13 ₁₂ are inputted to the coupler control circuit 30' via the OR gate 14 as a time division multiplexed signal TDM. Also, the bit output signal of the hexadecimal counter 15
Both N ₁ -N ₄ and the bit output signals B ₁ -B ₄ of the decimal counter 16 are input to the frequency number memory 18 in the time-division waveform generating circuit 4 as addressing signals. Here, the configuration of the time-division waveform generation circuit 4 will be explained. This circuit 4 generates frequency numbers (digital data represented by 17 bits, proportional to the frequency of each pitch) R corresponding to pitches C ₀ to C ₉ , respectively.
and the bit output signals N ₁ to _{N 4} ,
A frequency number memory 18 that inputs B ₁ to _{B 4} as addressing signals and outputs the corresponding frequency number R, and inputs the frequency number R output from this frequency number memory 18 to the first input terminal A, An adder 19 inputs output data qR of a shift register 20, which will be described later, to a second input terminal B and adds them, and an adder 19 corresponding to the bit time number.
Adder 1 has a capacity of 120 stages (each stage: 20 bits) and is driven by clock pulse φ.
A shift register 20 inputs and sequentially shifts the sum value data of 9, and a desired musical tone 1 waveform (in the following explanation, it is a sine wave waveform, but of course other waveforms may be used) at a plurality of (for example, 64) sample points. It stores data S representing the waveform amplitude value (sine amplitude value) at each sample point, and inputs the upper 8 bits of the output data qR (20 bits) output from the shift register 20 as an address designation signal. The sine table 21 outputs the corresponding sine amplitude value data S. Therefore, the frequency number memory 18 of the time-division waveform generation circuit 4 corresponds to each content of the 120 counters and is addressed in synchronization with the scanning of the key switch of the key switch circuit 1. Frequency numbers R corresponding to each pitch are sequentially input to the first input terminal A of the adder 19 in a time-division manner. In this case, from the frequency number memory 18, when the contents of the hexadecimal counters 15 and 16 are "0", the frequency number R corresponding to the pitch C ₀ is read out, and the frequency number R corresponding to the pitch C ₀ is read out from the frequency number memory 18 in order.
The frequency numbers corresponding to D ₀ , D#, ...... are read out, and the content of the 120-decimal counter is "108".
Then, the frequency number R corresponding to pitch _C9 is read out. Note that keys C ₀ to B ₀ and C# ₆ to C ₉ (48
The reason why the frequency number R corresponding to the pitch of each key (key) is stored is for each key C ₁ to _{C 6} as described later.
In response to the keys being pressed, musical tones with pitches of keys C ₁ to _{C 6} are generated, and musical tones one octave below and several octaves (1 to 4 octaves) above the pitch are also generated at the same time as coupler sounds. This is because it is generated as follows. The adder 19 adds the frequency number R and the output data qR of the shift register 20, and inputs the added value to the shift register 20 again. In this case, the frequency number R input to the adder 19 and the output data qR of the shift register 20 are related to the same pitch, so the adder 19 and the shift register 20 are sequentially time-shared from the frequency number memory 18. This means that the frequency numbers R of each pitch output are independently accumulated.
Output data (accumulated value) qR (q=1,
2, 3, ......), the upper 8 bits are input to the sign table 21 as an address designation signal,
From the sine table 21, sine amplitude value data S (for example, 12 bits) corresponding to each tone pitch C ₀ to _{C 9} is outputted in a time-division manner sequentially for each bit time. The coupler control circuit 30' includes shift registers 31 to 38 and a weighting circuit 39, which have exactly the same configuration as the coupler control circuit 30 in the electronic musical instrument shown in FIG.
47 and an adder 48, it further includes a plurality of storage devices M ₁ to _Mo switch devices S ₁ to _{S 9} . That is, this circuit 30' has a configuration in which storage devices M _{1 -Mo} and switch devices S ₁ -S ₉ are added to the coupler control circuit 30 of FIG. 1. Each of the storage devices M ₁ , M _{2 ,} . There is. In this case, the drawbar data group corresponds to the output of the encoder 50 in each weighting circuit 39-47. That is,
Nine types of drawbar data groups (3 bits) corresponding to feet 16', 8', . . . 1' are stored in each of the storage devices _M1 to _M0 . The drawbar data corresponding to each foot stored in each of the storage devices M ₁ to _{M o} is appropriately retrieved by operating settings of switch devices S ₁ to _{S 9} provided corresponding to each feed. There is. Each switch device S ₁ , S ₂ ......S ₉ has a contact S ₁
-0, S ₁ -1, S ₁ -2, ......S ₁ -n; S ₂ -0,
S ₂ -1, S ₂ -2,...S ₂ -n;...S ₉ -0,
S ₉ -1, S ₉ -2, ......S ₉ -n,
Each contact S ₁ -1 to _{S 9} -1 corresponds to the storage device M ₁ ,
Each contact S ₁ -2 to _{S 9} -2 corresponds to the storage device M ₂ ,
In the same manner, each contact S ₁ -3 - S ₉ -3,...
S ₁ -n to S ₉ -n correspond to the storage devices M ₃ to _{M o} , respectively. All of these switch devices S ₁ to _{S 9} are configured to work together. Therefore, for example, when each switch device S ₁ to _{S 9} is set to the contact point S ₁ -1 to _{S 9} -1, the drawbar data of each feed stored in the storage device M ₁ is retrieved and the contact point _S1-2 ～ _S9-
When set to 2, the drawbar data of each foot stored in the storage device _M2 is retrieved, and when set to the contacts _S1 -n to _S9 -n, the drawbar data is stored in the storage device _M0. The drawbar data for each foot that is present will now be retrieved.
Note that each switch device S ₁ to _{S 9} has a contact point S ₁ −
When set to 0 to S ₉ -0, none of the storage devices M ₁ to _{M o} is selected and no drawbar data is retrieved. In this way, the switch device S ₁
The drawbar data of each foot stored in the desired storage devices M ₁ to _{M o} can be retrieved by the operation settings in steps S 9 to S ₉ . Then, the extracted drawbar data of each foot is sent to the AND gate 51 of the weighting circuits 39 to 47 of the corresponding foot.
~53 is given to one input. Therefore,
The time division multiplexed signal TDM input to each weighting circuit 39-48 and each signal obtained by delaying this signal TDM by the shift registers 31-38 are respectively weighted by the drawbar data. By configuring the coupler control circuit 30' as described above, when setting the timbre of the generated musical sound, the changeover switch 49 in the weighting circuits 39 to 48 of each foot does not have to be operated and set each time _. ~ S ₉ operations) allows you to instantly set the tone. In this case, it goes without saying that the tone color can be set by operating the changeover switch 49 in the same manner as in the coupler control circuit 30 of FIG. FIG. 5 shows the electronic musical instrument of the embodiment shown in FIG.
The time division multiplexed signal TDM output from the key switch scanning circuit 2 when the keys C ₁ , D ₂ , and G# ₅ of the high notes C ₁ , D ₂ , and G# ₅ are pressed at the same time, and Split multiplex signal TDM coupler control circuit 3
0' shows signals delayed by the shift registers 31 to 38 (outputs at each of the points A to I). The numbers A to I in FIG. 5 indicate the contents of the hexadecimal counters 15 and 16 when the time division multiplexed signal TDM and its respective delayed signals are output to each point A to I. Each point A~
The time division multiplexed signal TDM outputted to I and its delayed signal are applied to the drawbar data of each foot stored in any of the selected storage devices _M1 to _M0 by the switch devices _S1 to _S2 . Therefore, each signal is weighted and sent to an adder 48. Note that when the drawbar data stored in the storage devices M ₁ to _{M o} is not used, the changeover switch 4 is set as described above.
9 is used for weighting. On the other hand, the ROM 60 stores amplitude levels for each frequency as shown in FIG. 4 in response to the formant characteristics of a desired musical instrument sound (usually the same as the musical instrument sounds set in the storage devices _M1 to _M0 ). A plurality of sets of formant data FD are stored, and the bit output signals from the counters 15 and 16 described above are
N ₁ to N ₄ and B ₁ to _{B 4} are input as addressing signals, and amplitude value data corresponding to the content of the addressing signals, that is, formant data FD is output. That is, when the contents of the hexadecimal counters 15 and 16 are "0", the formant data FD corresponding to the frequency of the high note C ₀ is read out from the ROM 60, and thereafter, the pitches C# ₀ , D ₀ , D# ₀ ,……
The formant data FD for the frequency of pitch C9 are read out sequentially, and when the content of the hexadecimal counter reaches "108", the formant data FD for the frequency of pitch _C9 is read out. Therefore,
The formant data FD outputted from this ROM 60 and the sine amplitude value data (waveform signal) S outputted from the time-division waveform generation circuit 4 are completely _{synchronized.} When the sine amplitude value data S is output, formant data FD for the frequency of this pitch C ₁ is output from the ROM 60. Note that the ROM 60 includes the coupler control circuit 3.
A switch device Sv that operates in conjunction with the switch devices S ₁ to _{S 9} of ROM 60 is provided, and the switch device Sv is configured to specify a set of formant data FD to be read from the ROM 60.
Therefore, from the ROM 60, the switch devices S ₁ to
Formant data FD (which realizes formant characteristics of the musical instrument sound) corresponding to the musical instrument sound selected by _S9 and Sv is read out. Now, in this way, the time division waveform generation circuit 4
The sine amplitude value data (waveform signal) output from
The weighting data K output from the coupler control circuit 30' and the formant data FD output from the ROM 60 are input to a multiplier 5' and are configured to be multiplied by each other. This multiplier 5'
consists of a first multiplication circuit 56 and a second multiplication circuit 57, in which the sine amplitude value data S and the weighting data K are multiplied, and this multiplication output is sent to the second multiplication circuit 57. It is further multiplied by the formant data FD at . The output of this multiplier 5' is then supplied to an accumulator 6. The accumulator 6 has a gate circuit 22, an adder 23, and a register 24, and the output of the register 24 is input to the B input of the adder 23.
is given through. Also, A of the adder 23
The output data of the multiplier 5' is applied to the input, so the adder 23 adds both input data, and the added value is input to the register 24 as 15-bit parallel data. This register 2
4 is driven by the aforementioned clock pulse φ,
The read data is delayed by one bit time and outputted to the gate circuit 22 and latch circuit 7 as 15-bit parallel data. A signal obtained by inverting the signal SYC by an inverter 25 is input to the gate circuit 22 as a control signal so that the gate circuit 22 is always open except at the end of one scanning period, that is, when the signal SYC is output. Further, the latch circuit 7 is provided with a signal SYC as a data read signal. Therefore, the adder 23 in the accumulator 6 starts to cumulatively add the output value of the multiplier 5' from the start of one scanning period (when the contents of the 120-decimal counters 15 and 16 are "0"), and When the contents of the decimal counters 15 and 16 reach "118", the adder 23 performs the final addition. Then, when the contents of the 120-decimal counters 15 and 16 become "119", the signal SYC is output, and the last accumulated value of the adder 23 (this accumulated value is stored in the register 24) is sent to the latch circuit 7. Latch. The latched data is further sent to a D/A converter 8, an amplifier 9, and a speaker 10, as explained with reference to FIG. As described above, in this first embodiment, the memory device provided in the coupler control circuit 30'
M ₁ , M ₂ , M ₃ , ...... A switch device S ₁ ...... S ₉ that reads the drawbar data stored in M _o ,
By linking the switch device Sv of the ROM 60 and operating and setting these switch devices S ₁ to S ₉ and Sv as appropriate, a drawbar corresponding to a desired musical instrument sound can be selected from any of the storage devices M ₁ to _{M o} . The data is read out, and the type and level of the coupler sound (so-called harmonic component) included in the generated musical sound are set using this drawbar data.
read out formant data FD representing the formant characteristics of the musical instrument sound, and apply a fixed formant data FD effect to the generated musical sound;
This produces musical sounds that are very similar to the sounds of natural musical instruments. Next, a second embodiment of the electronic sound device according to the present invention will be described. FIG. 6 shows its configuration. This electronic musical instrument is capable of generating sounds corresponding to male and female human voices as musical sounds. Also, in this electronic musical instrument, there are, for example, 48 keys (pitch C ₁ to B ₄ ), and these keys are divided into 2.
The 24 keys on the bass side (pitch C ₁ - _{B 2} ) are assigned to play musical tones corresponding to male voices, while the 24 keys on the treble side (pitch C ₃ - B ₄ ) are assigned to play musical tones corresponding to female voices. A ROM 60' (corresponding to the ROM 60 of the first embodiment) is provided for use in performance and for forming musical tones corresponding to male and female human voices. This ROM 60' stores eight types of formant data FD representing formant characteristics corresponding to vowels a (a), o (o), u (u), and HM (humming) of male voices and female voices. The formant data FD of any one vowel can be selectively retrieved by a switch device SW provided for the ROM 60'. Furthermore, a male voice coupler sound control circuit 59 and a female voice coupler sound control circuit 70 are provided to control the coupler sounds included in each musical tone of the male voice and the female voice. It should be noted that the same reference numerals will be given to the same or almost the same constituent parts of the electronic musical instrument of the second embodiment and the electronic musical instrument of the first embodiment, and detailed explanation thereof will be omitted. It is also assumed that the frequency number memory 18 of the frequency example of this embodiment stores frequency numbers R corresponding to pitches C ₁ to D# ₆ . Further, in this embodiment, the sine amplitude value data S output from the sine table 21 and the ROM 6
The formant data FD output from 0' is logarithmically expressed data using the minus log notation method. Correspondingly, a linear/logarithmic converter 82, which will be described later, is provided in order to convert the data output from the coupler control device 30' into logarithmic display data. As described above, since the data in this embodiment is logarithmically displayed data, the adder 5 is used in place of the multiplier circuits 56 and 57 in the case of FIG.
6', 57' are provided, but the multiplier circuits 56,
The functions of 57 and adders 56' and 57' are substantially the same. A log/linear converter 29 is provided to send the addition result (logarithm display data) of the adder 57' to the sound system 25 as linear display data. To explain the minus log display method here, the maximum value of the signal amplitude value (level) is defined as 0 dB, and the amplitude values below that are defined as the maximum amplitude value (0 dB).
For example, with respect to the maximum amplitude value (0 dB), -0.75 dB, -
1.5dB, -3dB, -6dB, -12dB, -24dB, -48dB...
... are defined, and these are made to correspond to each bit of data consisting of a plurality of one bits. That is, -0.75 dB is represented by the least significant bit (LSB), -1.5 dB is represented by the second bit, -6 dB is represented by the third bit, and so on. Therefore, when all bits of data representing the amplitude value of a signal are "1", the amplitude value is minimum, and on the other hand, when all bits are "0", the amplitude value is maximum.
Also, in order to express whether the amplitude value of a signal is on the plus side or the minus side with respect to the reference level (“0” level), like the sine amplitude value data S,
One sign bit is provided in addition to the plurality of bits of amplitude value data. When the amplitude value of the signal is on the plus side, a "0" signal is given to the sign bit, and when it is on the minus side, a "1" signal is given. Therefore, one bit of the sine amplitude value data S output from the sine table 21 is used as a sine bit. The configuration of the second embodiment will be explained in detail below. The 64-decimal counter 15' receives a clock pulse 2φ (eighth clock pulse) output from a pulse generator (not shown).
(see the waveform diagram in the figure) is input and counted. Bit output signals N ₀ to _{N 6} of the 64-decimal counter 15' are input to a timing signal generator 3' and used to generate various timing signals to be described later. Also, among the bit output signals N ₀ to N ₆ , bit output signals N ₁ to _{N 6}
is inputted to the frequency number memory 18 as an address designation signal, and also inputted to the key switch scanning circuit 2 and used for key switch scanning of the key switch circuit 1. Note that the clock pulse 2φ is inputted to the first input terminal of the AND gate 103 via the inverter INV8, and the bit output signal _N0 is inputted to the second input terminal. As a result, the AND gate 103 outputs a clock pulse φ having a frequency 1/2 of the clock pulse 2φ, as shown in FIG. The timing signal generator 3 outputs various timing signals _{0 to 7} Y ₆₃ , _{0 to 8} Y ₆₄ , MFS, as shown in FIG.
₁ Y ₂ , ₆₃ M ₆₃ is output. timing signal
_{0 to 7} Y ₆₃ indicates that the contents of the 64-decimal counter 15' are "0" to "63" in one scanning period of this embodiment (64-bit time period in which the contents of the 64-decimal counter 15' are "0" to "63"). The timing signal _{0 to 8 Y63} is a signal that becomes a "1" signal only during the period when the content of the 64-decimal counter 15' is "0" to "8". and the timing signal
For MFS, the content of 64-decimal counter 15' is "0" ~
A time-division multiplexed signal output from the key switch scanning circuit 2, which is a signal that is “1” only during the “23” period.
It is now possible to distinguish whether TDM concerns keys in the male voice range or keys in the female voice range. Timing signal ₁ Y ₂ is 64-decimal counter 1
The first half of each content of 5' is a "1" signal, and the second half is a "0" signal. This is because in this embodiment, it is necessary to process male and female voices at each bit time.
Each bit time is divided into two, the first half being _a time slot for male voice processing, and the second half being a time slot for female voice processing, and the timing is controlled by timing signals _1Y2 . Timing signal ₆₃ Y ₆₃
is a signal output as a "1" signal at the end of each scanning period (when the content of the 64-decimal counter 15' is "63"). Now, in FIG. 6, the timing signal MFS is input directly to the first input terminal of the AND gate 62, and is also input to the first input terminal of the AND gate 63 via the inverter _INV1 . Further, a time division multiplexed signal TDM is input to each second input terminal of the AND gates 62 and 63. Therefore, the AND gate 62 can operate only during the period when the contents of the 64-decimal counter 15' are "0" to "23" within one scanning period, and during this period, the key switch scanning circuit 2
The time-division multiplexed signal TDM for the key in the male voice range outputted from the signal register SR2-1 and the adder 48b is sent as a signal _M1 to the shift register _SR2-1 and the adder 48b. Also, the AND gate 63 is operable only during the period when the content of the 64-decimal counter 15' is "24" to "63" within one scanning period, and during this period (particularly when the content of the 64-decimal counter 15' is "24" to "47"). period)
The time division multiplexed signal TDM for keys in the female voice range output from the key switch scanning circuit 2 is passed through and sent as a signal _F1 to the shift register _SR1-1 and read-only memory (ROM) 48a. Shift registers SR _{1 -2} and SR ₁ -3 are connected in series after the shift register SR 1 -1. Shift registers SR ₁ -1 to SR ₁ -3 each have a capacity of 12 stages/1 bit, 7 stages/1 bit, and 5 stages/1 bit, and are driven by a clock pulse φ. Therefore, the signal input to shift register _SR1-1
F1 is a signal (delayed time division multiplexed signal) from each final stage of shift registers _SR1-1 , _SR1-2 , and _SR1-3 at the 12th, 19th, and 24th bit times from the input point, respectively.
Output as F ₂ , F ₃ ′, F ₄ ′. Signals F ₁ and P ₂ can be sent directly to the ROM 48a, and signals F ₃ ′ and F ₄ ′ can be sent to the ROM 48a through AND gates 104 and 105, respectively.
F ₃ and F ₄ and sent to the ROM 48a. this
The ROM 48a has a function as an adder, and for each state of the signals F ₁ to F ₄ , the signals F ₁ to _{F 4} are
The added value of is memorized. And this ROM48
Signals F ₁ to _{F 4} are input as address designation signals to a, and corresponding to the contents of these signals F ₁ to _{F 4} , addition value data FL ₁ , FL ₂ , FL ₃ (FL ₃ is MSB, FL ₁ is
The 3-bit data (LSB) is read out.
This situation is shown in the table below.

[Table] Of course, in this case, an adder may be used instead of the ROM 48a. Note that the AND gates 104 and 105 are gate-controlled by the inverted signal _0-763 of the timing signal _0-7Y63 , so that the contents _of the ₆₄ -decimal counter 15' are "0"--
It is said to be inoperable for a period of ``7'', but if a high-pitched key (pitch E <sub>4</sub> to <sub>B 4</sub> ) is pressed among the keys (24 keys) belonging to the female voice range, the male voice range will be disabled. This is to prevent musical tones in the low range C <sub>1</sub> to G <sub>1</sub> from being produced. In this way, the female voice coupler sound control circuit 59 is constituted by the shift registers SR <sub>1</sub> -1 to SR <sub>1</sub> -3, the ROM 48a, and the AND gates 104 and 105. Shift registers SR <sub>2</sub> -2 to SR <sub>2</sub> -15 are connected in series after the shift register SR <sub>2</sub> -1. Shift register SR <sub>2</sub> -1 to <sub>SR 2</sub> -15
12 stages/1 bit, 7 stages/1 bit, 5 stages/1 bit, 4 stages/1 bit, 3 stages/1 bit, 3 stages/1 bit, 2 stages/1 bit, 2 stages/1 bit , 2 stages/1 bit, 2 stages/1 bit, 1 stage/1 bit, 2 stages/1 bit, 1 stage/1 bit, 1 stage/1 bit, 1 stage/1 bit, and both clock pulses φ Driven by
Therefore, the signal <sub>M1</sub> inputted to the shift register <sub>SR2-1</sub> is output at the 12th bit time, 19th bit time, 24th bit time, 28th bit time, 31st bit time, 34th bit time, and 36th bit time from the input time, respectively. , 38th bit time, 40th bit time, 42nd bit time, 43
Signals (delayed time division multiplexed signals) M <sub>1</sub> to SR 2 -1 to SR 2 -15 from the final stages of the shift registers SR <sub>2</sub> -1 to <sub>SR 2</sub> -15 at the 45th bit time, 46th bit time, 47th bit time, and 48th bit time
Output as M <sub>10</sub> , M <sub>11</sub> ′ to M <sub>16</sub> ′. Signal M <sub>1</sub> ~
<sub>M10</sub> is directly input to the adder 48b, and the signal
M <sub>11</sub> ′ to M <sub>16</sub> ′ are inverted signals of timing signals <sub>0 to 3</sub> Y <sub>63</sub>
The signals M <sub>11</sub> to <sub>M 16</sub> are generated through AND gates 64 to 69 which are gate-controlled by <sub>0 to 3 63</sub> , and are input to the adder 48b. The adder 48b adds the input signals M <sub>1</sub> to <sub>M 16</sub> at each bit time, and converts the addition result into 5-bit addition value data ML <sub>1</sub>
(LSB) ~ Output as ML <sub>5</sub> (MSB). In addition,
AND gates <sub>64-69</sub> according to the signals <sub>0-863</sub>
However, the contents of the 64-decimal counter 15' are "0" to "8"
During this period, the keys on the treble side (pitch D# <sub>2</sub> ) of the wall (24 keys) belonging to the male voice range are considered inoperable.
This is to prevent musical tones of high pitches <sub>C3</sub> to G# <sub>3</sub> corresponding to the female voice range from being produced when the keys (keys <sub>.about.B2</sub> ) are pressed. In the case of a male voice, the inputs to the adder circuit 48b are M <sub>1</sub> to M <sub>16</sub> and the inputs of a female voice (F <sub>1</sub> to
<sub>F4</sub> ) This is because male voices have a lower range and a higher number of harmonics, whereas female voices generally have a higher range and a lower number of harmonics than male voices. That's the reason. In this way, shift registers SR <sub>2</sub> -1 to <sub>SR 2</sub> -15,
Adder 48b and AND gates 64-69 constitute male voice coupler sound control circuit 70. Each bit signal ML <sub>1</sub> to ML <sub>5</sub> of addition value data ML <sub>1</sub> to ML 5
AL <sub>5</sub> is an AND gate 71, 74, 77, 80, 81 gated by timing signal <sub>1</sub> Y <sub>2</sub>
and the AND gate 71,
The outputs of 74 and 77 are OR gates 73, 76, 79
and the AND gates 80 and 81, respectively.
The output of is directly input to the linear/logarithmic converter 82. Furthermore, each bit signal of addition value data FL <sub>1</sub> to <sub>FL 3</sub>
FL <sub>1</sub> ~ FL <sub>3</sub> invert the timing signal <sub>1</sub> Y <sub>2</sub>
It is input to AND gates 72, 75, 78 which are gate-controlled by the signal <sub>1 2</sub> inverted by INV <sub>2</sub> , and the outputs of AND gates 72, 75, 78 are linear/logarithmic via OR gates 73, 76, 79. It is input to a converter 82. Since the timing signal <sub>1Y2</sub> has the waveform described above (Fig. 8), the AND gates 71, 74, 77, 80 <sub>,</sub> and 81 are enabled in the first half of each bit time, and the male voice output from the adder 48b is The added value data ML <sub>1</sub> to <sub>ML 5</sub> are sent to the linear/logarithmic converter 82 . Also, in the latter half of each bit time, AND gates 72, 75, and 78 become operable.
Added value data of female voice output from ROM48a
FL <sub>1</sub> -FL <sub>3</sub> are sent to a linear/logarithmic converter 82. The linear/logarithmic converter 82 converts the added value data ML <sub>1</sub> to ML <sub>5</sub> and FL <sub>1</sub> to FL <sub>3</sub> of the linear display data into 8-bit logarithmic display data LG <sub>1</sub> to LG <sub>8</sub> , respectively, and inputs the data to the first comparison input of the comparator 83. Input to terminal A. Note that the logarithm display data LG <sub>1</sub> to LG <sub>8</sub> are data expressed by the above-mentioned minus log display method. Therefore, when all the bits of the input data ML <sub>1</sub> to ML <sub>5</sub> or FL <sub>1</sub> to FL <sub>3</sub> are the minimum value of the "0" signal, the linear/logarithmic converter 82 converts the logarithmic display data LG <sub>1</sub> of which all the bits are "1" signals. ~Output LG <sub>8</sub> ,
Further, when all bits of the input data are at the maximum value of the "1" signal, logarithmic display data LG1 to <sub>LG8</sub> in which all the bits are " <sub>0</sub> " signals are output. Also, the second
A shift register 8, which will be described later, is connected to the comparison input terminal B.
Of the 8 output data PL <sub>1</sub> to PL <sub>10</sub> , the upper 8 bits of signals PL <sub>3</sub> to PL <sub>10</sub> are input. Then, the comparator 83 compares the input data LG <sub>1</sub> to LG <sub>8</sub> and the data PL <sub>3</sub> to
Compare the size relationship with PL <sub>10</sub> , and if data PL <sub>3</sub> to <sub>PL 10</sub> is larger than data LG <sub>1</sub> to <sub>LG 8</sub> , an attack signal is issued.
ATK is output, and the other data LG <sub>1</sub> to LG <sub>8</sub> are data
If it is larger than PL <sub>3</sub> to PL <sub>10</sub> , a release signal RLS is output. Attack signal ATK is data PL <sub>1</sub> to <sub>PL 10</sub>
This is a signal that defines the attack period in the pronunciation envelope waveform of the coupler sound of each pitch of the male voice and female voice expressed by the release signal.
RLS is a signal that defines the decay period after key release. The attack signal ATK is the first input terminal of the AND gate 85 and the first addition input terminal of the adder 87.
It is entered in A <sub>3</sub> to A <sub>10</sub> . The output signals PL <sub>9</sub> and PL <sub>10</sub> of the shift register 88 are input to the second input terminal of the AND gate 85 via the NOR gate 84, and the output thereof is input to the first addition input terminal A <sub>2</sub> of the adder 87 and the AND gate 85. It is input to the first input terminal of gate 86. Also, the second of AND gate 86
The input terminal receives the output signal of the shift register 88.
PL <sub>8</sub> is input via the inverter INV 3 , and its output is input to the first addition input terminal A <sub>1</sub> of the adder 87 . Furthermore, respective bit signals PL <sub>1</sub> -PL <sub>10 of the output data PL 1 -PL 10 of the</sub> shift register 88 are input to second addition input terminals B <sub>1</sub> -B <sub>10</sub> of the adder 87 . Note that the first addition input terminal of the adder 87
Each signal input to A <sub>1</sub> to <sub>A 10</sub> is named x <sub>1</sub> to x <sub>10</sub> . The adder 87 adds the input signals x <sub>1</sub> to <sub>x 10</sub> of the first addition input terminals A <sub>1</sub> to A <sub>10</sub> and the input signals PL <sub>1</sub> to PL <sub>10</sub> of the second addition input terminals B <sub>1</sub> to B <sub>10</sub> , and calculates the addition result. is output as 10-bit data from output terminals S <sub>1</sub> to S <sub>10</sub> and sent to the shift register 88. The shift register 88 has a capacity of 128 stages and 10 bits, and is driven by a clock pulse 2φ to input the adder 8.
The data sent from 7 is sequentially shifted to the subsequent stage side. The reason why the capacity of the shift register 88 is set to 128 stages and 10 bits, and it is driven by a clock pulse of 2φ is that the first half of each bit time is allocated to processing the male voice signal, and the second half is allocated to processing the female voice signal. This is to correspond to the fact that the assignment is based on the assignment. Output data PL <sub>1</sub> ~ of the 128th stage of shift register 88
PL <sub>10</sub> is sent to the input of the adder 87 as described above, as well as to the first adder 56'.
In this case, the adder 87 and the shift register 88 constitute a circulation circuit that cyclically holds the data PL <sub>1</sub> to PL <sub>10</sub> . This cyclic holding operation consisting of 128 time slots is synchronized with the key switch scanning in the key switch scanning circuit 2 and the operation in the time division waveform generating circuit 4. Here, the operation of the adder 87 when the attack signal ATK is output from the comparator 83 will be explained.
When the attack signal ATK is output from the comparator 83, the AND gate 85 becomes operable and the signals x <sub>3</sub> to x <sub>10</sub> become "1" signals. Now, assuming that all bits of the output data PL <sub>1</sub> to PL <sub>10</sub> of the shift register 88 are "1" signals, the signals x <sub>1</sub> and x <sub>2</sub> are both "0" signals, and as a result, the adder 87 outputs "1111111100" ( x <sub>10</sub> ~ x <sub>1</sub> ) and “1111111111” (PL <sub>10</sub>
~ <sub>PL1</sub> ) and outputs "1111111011" from its output terminals <sub>S10</sub> to <sub>S1</sub> . That is, in this case, "4" is subtracted from the data PL <sub>10</sub> to <sub>PL 1</sub> . This addition data "1111111011" is input to the shift register 88, and after 128 time slots, it is output as output data PL <sub>10</sub> to PL <sub>1</sub> and added to the adder 87 again. In this case data PL <sub>10</sub> ~ <sub>H 1</sub>
Since the signals PL <sub>10</sub> to <sub>PL 8</sub> are “111”, the adder 87 outputs the data PL <sub>10</sub> to <sub>PL 1</sub> in the same manner as described above.
“1111110111” is output by subtracting “4” from (“1111111011”). "4" like this
The subtraction operation is repeated until the signals PL <sub>10</sub> to PL <sub>9</sub> of the data PL <sub>10</sub> to PL <sub>1</sub> become "00". Eventually, when the data PL <sub>10</sub> to PL <sub>1</sub> become “0011111111”, the signal x <sub>2</sub> becomes a “1” signal, and accordingly, the adder 87 outputs “1111111110” (x <sub>10</sub> to <sub>x 1</sub> ) and “0011111111” (PL <sub>10</sub>
~PL <sub>1</sub> ) and outputs “0011111101”.
That is, in this case, "2" is subtracted from the data PL <sub>10</sub> to <sub>PL 1</sub> . This "2" subtraction operation is performed on the signals PL <sub>10</sub> , PL <sub>9</sub> , PL <sub>8</sub> of the data PL <sub>10</sub> to <sub>PL 1</sub> .
This is repeated until becomes "000". data
When PL <sub>10</sub> to <sub>PL 1</sub> become “0001111111”, the signals x <sub>2</sub> and x <sub>1</sub> become “1” signals, and the adder 78 outputs “1111111111” (x <sub>10</sub> to <sub>x 1</sub> ) and “0001111111” (PL <sub>10</sub>
~PL <sub>1</sub> ) and outputs “0001111110”. That is, in this case, "1" is subtracted from the data PL <sub>10</sub> to PL <sub>1</sub> . This "1" subtraction operation is repeated while the attack signal ATK is being output. When the attack signal ATK is no longer output, the signals x <sub>10</sub> to x <sub>1</sub> become “0000000000” and the adder 8
7 outputs the data PL <sub>10</sub> to PL <sub>1</sub> as is. That is, when the attack signal ATK is no longer output, the data <sub>PL10</sub> to <sub>PL1</sub> do not change. In this way, when the attack signal ATK is output, the contents of the data PL <sub>10</sub> to PL <sub>1</sub> change sequentially, and the changes are shown in FIG. 7. In FIG. 7, 4R, 2R, and R indicate periods in which the above-described "4" subtraction operation, "2" subtraction operation, and "1" subtraction operation are performed, respectively. Note that since the attack signal ATK is a signal that is output independently in each of the 128 time slots, the above-mentioned operation is performed only in the time slot to which the attack signal ATK is output. Next, the operation when the release signal RLS is output from the comparator 83 will be explained. In addition, the release signal
When RLS is output, the access signal ATK is never output, so the signal to adder 87 is x <sub>1.</sub>
~ <sub>x10</sub> are all "0" signals. When the release signal RLS is output, the AND gate 100 is activated and a pulse signal based on the output of a variable frequency oscillator 89 or 90, which will be described later, is sent to the adder 7.
Data PL <sub>10</sub> added to carry input terminal C of 8
"1" is added to ~PL <sub>1</sub> . This configuration will be explained in detail below. The output pulse of the male voice variable frequency oscillator 89 is input to the first input terminal of an AND gate 95 via delay flip-flops 91 and 93 connected in series. A delay flip-flop 9 is connected to the second input terminal of the AND gate 95.
1 output signal is input via inverter <sub>INV5</sub> . In this case, the delay flip-flop 91,
Since 93 is driven by the timing signal <sub>63</sub> Y <sub>63</sub> (Fig. 8), the AND gate 95 generates a pulse having a pulse width of 64 bit time in response to the falling edge of the output pulse of the variable frequency oscillator 89. A signal (hereinafter referred to as a male voice decay clock pulse) is output. The male voice decay clock pulse output from AND gate 95 is input to the first input terminal of AND gate 97. The timing signal <sub>1</sub> Y <sub>2</sub> is input to the second input terminal of the AND gate 97, and as a result, the AND gate 97 can operate only in the first half of each bit time, that is, in the time slot for male voices. Outputs a clock pulse. On the other hand, the output pulse of the variable frequency oscillator 90 for female voices is applied to a falling differential circuit comprising delay flip-flops 92, 94, an inverter <sub>INV6</sub> and an AND gate 96 constructed in the same manner as described above. Therefore, the AND gate 96 outputs a pulse signal (hereinafter referred to as a female voice decay clock pulse) having a pulse width of 64 bits in response to the falling edge of the variable frequency oscillator 90. This day clock pulse for female voice is ANDGATE 9.
It is input to the first input terminal of 8. and gate 98
The timing signal <sub>1</sub> Y <sub>2</sub> is inputted to the second input terminal of the bit timer via the inverter INV <sub>7.</sub> Therefore, the AND gate 98 can only operate in the second half of each bit time, that is, in the female voice time slot. Outputs a daytime clock pulse. The decay clock pulse for the male voice and the decay clock pulse for the female voice are inputted to the first input terminal of the AND gate 100 via the OR gate 99. The release signal RLS output from the comparator 83 is input to the second input terminal of the AND gate 100, and the AND gate 100 receives the release signal RLS.
The AND gate 10 is activated for each time slot in which the signal is output, and passes the decay clock pulse for a male voice or the decay clock pulse for a female voice that corresponds to that time slot.
2 to the first input terminal. The second input terminal of the AND gate 102 receives signals PL <sub>3</sub> -PL <sub>10</sub> of the higher bits of the output data PL <sub>1</sub> -PL <sub>10</sub> of the shift register 88.
The output signal of the NAND gate 101 is input. Therefore, at each time slot the signal
Except when the contents of PL <sub>3</sub> to PL <sub>10</sub> are all "1" signals, the output signal of the NAND gate 101 becomes a "1" signal, enabling the AND gate 102 to operate in the relevant time slot, and causing the decay pulse output from the AND gate 100 to become a "1" signal. The signal is passed through and added to the carry input terminal C of the adder 87. Therefore, the adder 87 adds "1" to the output data PL 1 to PL <sub>10</sub> of the shift register 88 in the time slot in which the AND gate <sub>100</sub> outputs the decay pulse (decade clock pulse for male voice or decay clock pulse for female voice). '' is added and the addition result is sent to the shift register 88, and in the time slot where the decay pulse is not output, it is set to ``1''.
No addition operation is performed and the output data PL ₁ to _{PL 10} of the shift register 88 is sent to the shift register 88 as is.
send to In this way, when the release signal RLS is output, the contents of the data PL ₁₀ to PL ₁ are incremented by "1" at the cycle of the male voice decay clock pulse or the female voice decay clock pulse. Then, when all of the signals PL ₁₀ to PL ₃ of the data PL ₁₀ to _{PL 1} become "1" signals, the output signal of the NAND gate 101 becomes a "0" signal, which causes the AND gate 102 to become inoperable and release the release signal.
Data at the time slot where RLS occurred
The operation of adding "1" to PL ₁₀ to PL ₁ is stopped. Output data PL ₁ -PL ₁₀ of shift register 88 are also input to adder 56'. The sine amplitude value data S read from the sine table 21 is inputted to this adder 56' from the sine table 21, so the adder 56' adds both input data PL ₁ to PL ₁₀ and S. , and further outputs the added value data to an adder 57'. The formant data FD read from the ROM 60' is input to the adder 57', and therefore the adder 57' further adds the formant data FD to the addition value data output from the adder 56'. are added, and the added value data is output to the logarithmic/linear converter 29. As mentioned above, the ROM 60' records the formant data FD corresponding to four types of vowels separately for male and female voices, and the formant data FD for any one vowel is recorded by switching the switch device SW.
can be selectively read out. In this case, the ROM 60' inputs the signals N ₀ to N ₆ of the bit output signals N ₀ to _{N 6} of the 64-decimal counter 15' and the timing signal ₁ Y ₂ as address designation signals and changes the contents of the address designation signals. Outputs the corresponding formant data FD. Furthermore, formant data FD _M for male voices and formant data FD _F for female voices are output from ROM 60' in accordance with timing signal ₁ Y ₂ (both of these data correspond to the vowel selected by switch device SW).
are read out alternately. Added value data of the adder 57' converted into linear data by the logarithmic/linear converter 29 (in this case, each of the above data PL ₁ to PL ₁₀ , S, FD
Since both are logarithm display data, the contents of this added value data converted into linear data are the values obtained by multiplying the data PL ₁ to PL ₁₀ , S, and FD, respectively. ) is input to an accumulator 6 driven by a clock pulse 2φ. This accumulator 6 has the same structure as the accumulator 6 (FIG. 3) of the first embodiment, and the output data of this accumulator 6 is sent to a latch circuit driven by a timing signal ₆₃ Y ₆₃ . 7, and further D/A converter 8 and amplifier 9.
is configured to be sent to the speaker 10 via the. Next, the operation of the second embodiment will be explained. To simplify the explanation, we will first describe the operation when only the key C ₁ of pitch C ₁ is pressed and released among the keys in the male voice range. The counting operation of the 64-decimal counter 15' is always executed, and its bit output signal
_N1 to _N6 are input to the key switch scanning circuit 2, and the key switches for each key of pitches _C1 to _B4 are sequentially scanned. Furthermore, since the bit output signals N ₁ to _{N 6} are input as address designation signals to the frequency number memory 18 of the time-division waveform generation circuit 4, they correspond to pitches C ₁ to D ₆ # in synchronization with the key switch scanning. As a result, sine amplitude value data S corresponding to pitches C ₁ to D ₆ # are sequentially output as logarithmic display data from the sine table 21 synchronized with the key switch scanning. is sent to an adder 56'. Further, the bit output signal N ₁ ~
Since N ₆ is also input to the ROM 60' as an address designation signal together with the timing signal ₁ Y ₂ , if the switch device SW is now set to the vowel a (A), then the vowel a (A) of the male and female voices. ) formant data FD _M
and _FDF are output alternately in the order of male and female voices in the first half (time slot for male voice) or the second half (time slot for female voice) of each bit time, and are sent to the second adder 57'. On the other hand, when the key is not pressed, the added value data ML ₁ output from the adder 48b and the ROM 48a
The contents of ~ _ML5 and _FL1 ~ _FL3 are all all-bit "0" signals. Therefore, the output data _LG1 to _LG8 of the linear/logarithmic converter 82 are all-bit "1" signals in the male voice time slot and the female voice time slot. The contents of each stage of the shift register 88 are initially all-bit "1" signals. Therefore, the comparator 83 outputs an attack signal.
Neither ATK nor release signal RLS is output. Therefore, in this keyless state, the data PL ₁ to PL ₁₀ output for each time slot (128 time slots in total) are held as all-bit "1" signals. In this case, the data PL ₁ to PL ₁₀ are logarithmic data expressed using the minus log representation method, as described above, and the fact that all the bits are "1" signals represents the minimum amplitude value (substantially zero). , Therefore, in this case, the output of the logarithmic/linear converter becomes zero and no musical tone is produced. Here, when key C ₁ in the male voice range is pressed,
This key C ₁ is pressed at the start of one scanning period (hereinafter referred to as the first scanning period) that starts after the key is pressed, that is, 64
When the content of the advance counter 15' is "0" (at the 0th bit time), it is scanned, and the time division multiplexed signal TDM output from the key switch scanning circuit 2 becomes a "1" signal in synchronization with the 0th bit time. At this time, since the timing signal MFS is output as a "1" signal, the AND gate ₆₂ is enabled to operate.
and sent to adder 48b and shift register SR ₂ -1. Shift register SR _2-1
The signal M ₁ inputted to is sequentially shifted and sent to the subsequent shift registers SR ₂ -2 to _{SR 2} -15. As a result, each shift register SR ₂ -2 ~
From SR _2-15 , the 12th, 19th, 24th, and
31st, 34th, 36th, 38th, 40th, 42nd, 43rd,
At each of the 45th, 46th, 47th, and 48th bit times, "1" signals _M2 to _M10 and _M11 ' to _M16 ' are output. As a result, each bit time 0, 12,
Signals M ₁ , M ₂ , M _{3 , .}
8b. Also, the adder 48b
adds the input signals M ₁ to M ₁₆ for each bit time, and uses the addition result as added value data ML ₁ to _{ML 5}
However, in this case, only one key _C1 is pressed, so the "1" signal input to the adder 48b at each bit time is M1 _{to M1} .
Since there is only one of _M16 , the added value data _ML1 to _ML5 output from the adder 48b at each bit time is "10000" (1 in decimal number).
becomes. The added value data ML ₁ to ML ₅ are applied to the AND gates 71, 74, 77, 80, 81 and the OR gate 73, which can be operated by the timing signal ₁ Y ₂ in the first half of each bit time (time slot for male voice). , 76 to a linear/logarithmic converter 82. Therefore, after pressing key _C1 , each of the bit times 0, 12, 19, . . .
..., 47, in the first half of 48 linear/logarithmic converter 8
The contents of the data LG ₁ to LG ₈ outputted from the circuit 2 are no longer all-bit "1" signals. Therefore the key C ₁
Each of the above bit times 0, 12, 19, . . . after the key is pressed
…, “1” from comparator 83 in the first half of 47, 48
The signal attack signal ATK is now output. This attack signal ATK (“1” signal) is the first addition input terminal of the AND gate 85 and the adder 87.
Since it is input to _A3 to _A10 , the content of the addition result signal of the adder 87 in the first half of the bit time becomes "1111111011" as described above. That is, the key
Each of the above bit times 0, 12, 19 after pressing the _C1 key,
......, 47, 48 (in relation to the time slots formed by dividing the bit time into two, time slots 0, 24, 38, ......, 94, 96), the first The content of the signal input to the stage is "1111111011". Further, the signals input to the first stage of the shift register 88 in this manner are sequentially shifted to the subsequent stages, and outputted as data PL ₁ to PL ₁₀ from the final stage 128 time slots after being input to the first stage. It turns out. After the second scanning period while the key C ₁ is being pressed, similarly to the first scanning period, the “1” signal M ₁ , M ₂ , M ₃ , . . . , M ₁₅ , M ₁₆ are input to the adder 48b, and furthermore, in the first half of each bit time 0, 12, 19, . The operation output from comparator 83 and sent to adder 87 is performed. Therefore, each bit time 0, 12, 19,...
...first half of 47, 48 (time slots 0, 24, 38,...
..., 94, 96), the first shift register 88
The contents of the signals input to the stage (in other words, the data PL ₁ to PL ₁₀ output from the shift register 88) change sequentially according to the curve shown in FIG. Note that while pressing key C ₁ , the corresponding key
Output data of shift register 88 for C ₁ PL ₃
~ When the content (amplitude value) of PL ₁₀ becomes equal to the output data LG ₁ ~ _{LG 8} of the linear/logarithmic converter 82, the attack signal ATK output from the comparator 83 becomes "0", and from then on, that value will be used. is retained in circulation. In this way, all bits in each time _slot 24, 38, . Not data PL ₁ ~ _{PL 10}
(Changes according to the curve shown in Figure 7)
starts to be sent to the first adder 56', so the first adder 56' receives pitches C ₁ , C ₂ , G ₂ , C ₃ , and corresponding to the input data PL ₁ to PL ₁₀ .
. . . and the sine amplitude value data S of _C4 are added, and the added value data is sent to the second adder 57'. Second
The adder 57' corresponds to each time slot 0, 24,
38, ..., 94, 96, formant data FD corresponding to the formant characteristics of the male voice vowel a (a) sent from the ROM 60' is added to the addition value data inputted every 94, 96, The added value data is output to the logarithmic/linear converter 29. For this reason, the logarithmic/linear converter 29 converts the inputted addition value data (logarithmic display data) into linear display data, and sequentially outputs the linear display data to the accumulator 6. In this case, the contents of the linear display data input to the accumulator 6 are the values obtained by multiplying the data PL ₁ to PL ₁₀ , the sine amplitude value data S, and the formant data FD, respectively. Accumulator 6
accumulates 16 kinds of tones (coupler sounds) corresponding to the signals _M1 to _M16 in each scanning period, and the cumulative value is latched in the latch circuit 7 at the end of each scanning period. It is sent to converter 9. Therefore, from the speaker 10, a synthesized sound with a basic pitch of C ₁ , consisting of 16 types of constituent sounds (coupler sounds), and having formant characteristics corresponding to the masculine vowel a (a) is further output as shown in FIG. A musical tone with a volume envelope (attack characteristic) corresponding to the indicated curve will be produced. When the key C ₁ is released, the time division multiplexed signal for the key C ₁ starts from one scanning period starting immediately after the key is released.
TDM changes to “0” signal at the 0th bit time, so the addition value data for key C ₁
The contents of _M1 to _M16 also become "0" signals. Therefore, each bit time after key release is 0, 12, 19, ..., 47, 48.
The contents of the data LG ₁ to LG ₈ outputted from the linear/logarithmic converter 82 are all bit "1" signals, and therefore the comparator 83 outputs the respective bit times 0, 12, 19, ..., 47, In the first half of 48 (time slots 0, 24, 38, . . . , 94, 96), a release signal RLS of a "1" signal is output, enabling the AND gate 100 to operate in that time slot. Therefore, the male voice decay clock pulse (“1” signal) is output from the AND gate 95 in accordance with the oscillation frequency of the low frequency oscillator 89.
is the time slot 0, 24, 38, ..., 94, 96
is added to the carry input terminal C of the adder 87, and the corresponding output data PL ₁ of the shift register 88
~The content of PL ₁₀ increases by +1, and the amplitude value of the envelope waveform decreases. Therefore, the above-mentioned musical tone is given a decay characteristic of a speed (time) corresponding to the oscillation frequency of the variable frequency oscillator 89, and gradually attenuates and is no longer produced. Note that when two or more keys in the male voice range are pressed at the same time, the time division multiplexed signal TDM becomes "1" at two or more bit times within each scanning period. The “1” signal (any of signals M ₁ to _{M 16} ) is input to the adder 48b, but
The comparator 83, adder 87, shift register 8
Since the operation of keys 8 and the like is substantially the same as that of the key _C1 , the explanation thereof will be omitted. Next, a brief explanation will be given of the operation when a key in the female voice range, for example, key C ₃ of pitch C ₃ is pressed. key C ₃
Within one scanning period that starts after the key is pressed, when the content of the 64-decimal counter 15' is "24", that is, at the 24th bit time, the time division multiplexed signal TDM of the "1" signal for key _C3 is generated. , a "1" signal synchronized with the time division multiplexed signal TDM from the AND gate 63 which is enabled to operate at this time.
F ₁ is output and sent to ROM 48a and shift register SR ₁ -1. As a result, signals F _{2 ,} F ₃ ′, and F ₄ ′ of “1” are output from shift registers SR ₁ -1, SR 1 -2, and SR ₁ -3 at the 36th, 43rd, and 48th bit times, respectively. Output. For this reason, the ROM 48a contains the above-mentioned bit times.
When 24, 36, 43, 48, address 1, 2, 4, 8
Addressing signal “0001” indicating each address,
"0010", "0100", "1000" are input, and ROM
Additional value data FL ₁ to FL ₃ indicating the content "1" at the relevant bit time from each designated address of 48a.
"001" is read. Each bit time 24,
Added value data FL ₁ read at 36, 43, 48
~ _FL3 is sent to the linear/logarithmic converter 82 via AND gates 72, 75, 78 and OR gates 73, 76, 79 in the latter half of each bit time 24, 36, 43, 48 (time slot for female voice),
As a result, the linear/logarithmic converter 8
2 to data where all bits are not “1” signal LG ₁ ~
_LG8 is converted and output and sent to the comparator 83. Therefore, the second half of the bit times 24, 36, 43, and 48,
That is, in the time slots 49, 73, 87, and 97, the comparator 83 outputs an attack signal ATK of "1", which is input to the AND gate 85 and the first addition input terminals _A3 to _A10 of the adder 87. Ru. In synchronization with this operation, the adder 87 outputs an addition result signal of "1111111011" for each time slot, and sends it to the first stage of the shift register 88. In this way, the addition result value signal of "1111111011" is input to the first stage of the shift register 88 at the time slots 49, 73, 87, and 97. The subsequent operations are the same as those for the key _C1 , so a description thereof will be omitted. The operations when two or more keys in the female voice range are pressed at the same time, and the operations when keys in the male and female voice ranges are pressed at the same time, can be easily understood from the above explanation, so the explanation thereof will be omitted. . In the above embodiment, the output of the coupler control circuit 30' or the shift register 88 and the sign table 2
1 is first multiplied or added to the output of ROM 60 or 60', and then this multiplied value or added value is multiplied or added to the output of ROM 60 or 60'.
ROM60 or 60' output and sign table 2
1 may be first multiplied or added, and then this multiplied value or added value may be multiplied or added to the output of the coupler control circuit 30' or the shift register 88. As explained above, the present invention stores formant data representing the fixed formant characteristics of various musical instrument sounds and human voice sounds in a memory, and reads desired formant data during performance to improve the amplitude of musical sound signals. Since the level is controlled, it is possible to impart a desired fixed formant effect to the generated musical tones, thereby generating musical tones that are very similar to the sounds of natural instruments, human voices, etc.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing a conventional electronic musical instrument that is the basis of the present invention, FIG. 2 is a schematic block diagram showing a first embodiment of the electronic musical instrument according to the present invention, and FIG. Detailed circuit diagram of Figure 4 is the detailed circuit diagram of Figure 3.
FIG. 5 is a timing chart for explaining the operation of the electronic musical instrument shown in FIG. 3. FIG. 6 is a waveform chart showing an example of formant data stored in the ROM shown in the figure. In the second embodiment, FIG. 7 is a waveform diagram for explaining the operation of the electronic musical instrument shown in FIG. 6, and FIG. 8 is a waveform diagram showing timing signals used in the circuit of FIG. 5. 1... Key switch circuit, 2... Key switch scanning circuit, 3... Timing signal generation circuit, 4... Time division waveform generation circuit, 5'... Multiplier, 6... Accumulator, 60, 60' ...ROM, 30'...
...Coupler control circuit, 59...Female voice coupler sound control circuit, 70...Male voice coupler sound control circuit, 83...Comparator, 87, 56, 57'...Adder, 88...
shift register.

Claims (1)

[Scope of Claims] 1. A plurality of key switches are sequentially scanned at a predetermined speed to generate a time-division multiplexed signal indicating the key depression state of each key, and the signal corresponds to each pitch in synchronization with the key switch scanning. In an electronic musical instrument that generates a waveform signal in a time-division manner and multiplies this waveform signal by the above-mentioned time-division multiplexed signal to generate a musical tone signal corresponding to a pressed key, A memory storing numerical data representing amplitude levels for each frequency is provided, and the numerical data is read from the memory in synchronization with the waveform signal,
An electronic musical instrument characterized in that the amplitude of the waveform signal is controlled by the read numerical data. 2. A plurality of key switches are sequentially scanned at a predetermined speed to generate a time-division multiplexed signal indicating the pressed state of each key, and then the time-division multiplexed signal is sequentially delayed by a predetermined time to generate a plurality of delayed time-division multiplexed signals. The generated time-division multiplexed signal and the delayed time-division multiplexed signal are respectively weighted as desired and outputted as weighted signals, and the waveform signals corresponding to each pitch are time-divisionally output in synchronization with the key switch scanning. occurred in
In an electronic musical instrument that generates a pressed key and a plurality of musical tone signals having a predetermined pitch relationship with the pressed key by multiplying this waveform signal and the weighted signal, each frequency is set according to desired formant characteristics. A first memory stores a plurality of sets of numerical data representing amplitude levels for each weighting signal, and a second memory stores a plurality of sets of data for setting the weighting of each of the weighted signals. reading the set of data groups, generating each of the weighting signals based on the read data group, and reading out the desired set of numerical data from the first memory in synchronization with the waveform signal;
An electronic musical instrument characterized in that the amplitude of the waveform signal is controlled by the read numerical data.