JPS6117148B2 - - Google Patents
Info
- Publication number
- JPS6117148B2 JPS6117148B2 JP14534178A JP14534178A JPS6117148B2 JP S6117148 B2 JPS6117148 B2 JP S6117148B2 JP 14534178 A JP14534178 A JP 14534178A JP 14534178 A JP14534178 A JP 14534178A JP S6117148 B2 JPS6117148 B2 JP S6117148B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- thin plates
- cut
- single crystal
- semiconductor thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28D—WORKING STONE OR STONE-LIKE MATERIALS
- B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/117—Shapes of semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/201—Marks applied to devices, e.g. for alignment or identification located on the periphery of wafers, e.g. orientation notches or lot numbers
Landscapes
- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Dicing (AREA)
Description
【発明の詳細な説明】
本発明は多層構造の半導体素子の製造方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a multilayer structure.
半導体素子例えば半導体整流素子は１個の素子
の耐圧が1000V程度であるために、10KVないし
20KV程度の高耐圧半導体整流素子では、複数個
の素子を直列に接続して所要の耐圧を得ている。 Semiconductor elements, such as semiconductor rectifiers, have a breakdown voltage of about 1000V, so
In high-voltage semiconductor rectifiers of about 20KV, multiple elements are connected in series to obtain the required breakdown voltage.
この高耐圧半導体整流素子の製造方法として
は、次の方法が知られている。（特公昭40−4260
号）。棒状の半導体単結晶（インゴツト）を輪切
りにして多数の半導体薄板（ウエハ）を作る。こ
の半導体薄板に不純物拡散処理を施してPN接合
を形成する。このPN接合が形成された半導体薄
板をろう材（例えば半田）を介して複数枚積み重
ね、加熱接着せしめた後、これを所要の大きさに
切断して多層構造の半導体素子を多数個得てい
る。 The following method is known as a method for manufacturing this high voltage semiconductor rectifier. (Tokuko Showa 40-4260
issue). A rod-shaped semiconductor single crystal (ingot) is sliced into rings to make many semiconductor thin plates (wafers). This semiconductor thin plate is subjected to impurity diffusion treatment to form a PN junction. A plurality of thin semiconductor plates with this PN junction formed thereon are stacked together using a brazing material (for example, solder) and bonded together by heating, and then cut into desired sizes to obtain a large number of semiconductor elements with a multilayer structure. .
この半導体素子の製造に際しては、いろいろな
半導体単結晶から切り出した半導体薄板を任意に
接合しているため、各PN接合の特性にバラツキ
が生じるという欠点がある。すなわち、半導体薄
板の比抵抗は、個々の半導体単結晶によつても異
なり、また同じ半導体単結晶でもその位置によつ
て異なつている。 When manufacturing this semiconductor element, semiconductor thin plates cut from various semiconductor single crystals are arbitrarily joined together, so there is a drawback that the characteristics of each PN junction vary. That is, the specific resistance of a semiconductor thin plate differs depending on each individual semiconductor single crystal, and even in the same semiconductor single crystal, it differs depending on its position.
したがつて、比抵抗が数Ωから数十Ωと大きく
ばらついているPN接合の母材を重ね合せて作つ
た半導体素子は、逆方向ブレークダウン電圧が大
幅にばらついたものになる。このため、整流動作
中に逆方向ブレークダウン電圧の小さいPN接合
が破壊し、ひいては半導体素子全体が破壊されて
しまう。 Therefore, a semiconductor device made by stacking PN junction base materials whose resistivities vary greatly from several ohms to several tens of ohms will have a reverse breakdown voltage that varies widely. For this reason, the PN junction with a small reverse breakdown voltage is destroyed during the rectification operation, and the entire semiconductor element is destroyed.
本発明は上記欠点を解決するもので、各PN接
合の比抵抗のバラツキをなくすことができるよう
にした半導体素子の製造方法を提供することを目
的とするものである。 SUMMARY OF THE INVENTION The present invention is intended to solve the above-mentioned drawbacks, and aims to provide a method for manufacturing a semiconductor device that can eliminate variations in resistivity of each PN junction.
一般に、半導体単結晶の比抵抗は、その位置に
よつて異なつている横断面上の位置が異なると、
比抵抗が大きく変わるが、同じ位置のところで
は、軸方向の位置が多少変わつてもそれほど変化
しない。 In general, the specific resistance of a semiconductor single crystal varies depending on its position.
The specific resistance changes greatly, but at the same location, it does not change much even if the axial position changes slightly.
したがつて、半導体単結晶の横断面上の位置が
同じく、かつ軸方向の位置が近いものであれば、
この部分の比抵抗は非常に近似した値になつてい
る。 Therefore, if the semiconductor single crystals have the same cross-sectional position and are close to each other in the axial direction,
The resistivity values of this part are very similar.
そこで本発明は、半導体単結晶に位置合せ用の
マークを刻設しておいてから、多数の半導体薄板
に切断し、PN接合を形成した後、前記マークを
利用して切断前の位置関係に復元し、これを所要
の大きさに切断することを特徴とするものであ
る。 Therefore, in the present invention, alignment marks are engraved on a semiconductor single crystal, the semiconductor single crystal is cut into a large number of thin semiconductor plates, PN junctions are formed, and then the marks are used to adjust the positional relationship before cutting. It is characterized by restoring it and cutting it to the required size.
こうして、製造した多層構造の半導体素子は、
母材の近接した部分から構成されているから、比
抵抗すなわち逆方向ブレークダウン電圧のバラツ
キがなくなり、信頼性が向上する。 In this way, the multilayer structure semiconductor device manufactured is
Since it is constructed from adjacent parts of the base material, there is no variation in resistivity, that is, reverse breakdown voltage, and reliability is improved.
以下、図面を参照して本発明の実施例について
詳細に説明する。第１図に示す半導体単結晶は、
引上げ法あるいはFZ法によつて棒状に作られ
る。この半導体単結晶１は、直径が約25〜100mm
であり、長さが約10cm〜１ｍである。 Embodiments of the present invention will be described in detail below with reference to the drawings. The semiconductor single crystal shown in Figure 1 is
It is made into a rod shape by the pulling method or FZ method. This semiconductor single crystal 1 has a diameter of approximately 25 to 100 mm.
The length is approximately 10 cm to 1 m.
第２図に示すように、半導体単結晶１の周縁を
研削して平担部２を作る。この平担部２に、不平
行な直線溝３，４をダイヤモンドカツタ等で刻設
する。この２本の溝３，４は位置合せ用のマーク
として用いられるものである。 As shown in FIG. 2, the peripheral edge of the semiconductor single crystal 1 is ground to form a flat portion 2. Non-parallel linear grooves 3 and 4 are cut into this flat portion 2 using a diamond cutter or the like. These two grooves 3 and 4 are used as alignment marks.
第３図に示すように、前記２本の溝３，４を施
してから、ダイヤモンドカツタあるいはワイヤソ
ー等で切断し、厚さ約0.2mm〜0.4mmの多数の半導
体薄板５を作る。図面で符号６はこの切断線を表
わしている。 As shown in FIG. 3, after forming the two grooves 3 and 4, cutting is performed using a diamond cutter or a wire saw to form a large number of semiconductor thin plates 5 having a thickness of about 0.2 mm to 0.4 mm. In the drawing, reference numeral 6 represents this cutting line.
第４図に示すように、これらの各半導体薄板５
に公知の方法で不純物を拡散してPN接合とす
る。このPN接合形成後に両面にオーミツクメタ
ル７をメツキまたは蒸着する。 As shown in FIG. 4, each of these semiconductor thin plates 5
Impurities are diffused using a known method to form a PN junction. After forming this PN junction, ohmic metal 7 is plated or vapor deposited on both sides.
つぎに前記２本の溝３，４を目安にして切断前
の順番に並べて位置を揃え、これから必要な枚数
の半導体薄板５を取り出す。１枚の半導体薄板５
の耐圧が1000Vであるとし、製品の耐圧が10KV
であれば、10枚の半導体薄板を取り出す。 Next, using the two grooves 3 and 4 as a guide, they are lined up and aligned in the order before cutting, and the required number of semiconductor thin plates 5 are taken out. One semiconductor thin plate 5
Assume that the withstand voltage is 1000V, and the product's withstand voltage is 10KV.
If so, take out 10 semiconductor thin plates.
第５図に示すように、これらの半導体薄板５の
間に板状のろう材８を挾み、熱を加えて各半導体
薄板５を接着する。この結果半導体単結晶時の位
置関係に復元される。 As shown in FIG. 5, a plate-shaped brazing material 8 is sandwiched between these semiconductor thin plates 5, and heat is applied to bond each semiconductor thin plate 5. As a result, the positional relationship is restored to that of the semiconductor single crystal.
つぎに、ダイヤモンドカツタ、ワイヤソー等を
用いて、碁盤目状に長さ方向に細断する。なお、
符号９は切断線を表わしている。 Next, using a diamond cutter, wire saw, etc., the pieces are cut into pieces in the length direction in a grid pattern. In addition,
Reference numeral 9 represents a cutting line.
この細断により、角柱状をした多層構造の半導
体整流素子１０が多数得られる。この半導体整流
素子１０は、半導体単結晶の近接した部分から作
られているから、各PN接合はその逆方向ブレー
クダウン電圧が極めて近似した値になつている。 By this cutting, a large number of semiconductor rectifying elements 10 having a multilayer structure having a prismatic shape are obtained. Since this semiconductor rectifying element 10 is made from adjacent parts of a semiconductor single crystal, the reverse breakdown voltages of each PN junction have extremely similar values.
切り出された半導体整流素子１０は、その両端
にリード線１１，１１がろう付けされる。そして
全体を例えばシリコンゴム１２で被覆し、さらに
樹脂１３で密封する。 Lead wires 11, 11 are brazed to both ends of the cut out semiconductor rectifying element 10. Then, the whole is covered with silicone rubber 12, for example, and further sealed with resin 13.
上記構成を有する本発明は、半導体単結晶に不
平行な複数本の直線溝を刻設し、この溝を利用し
て半導体薄板を切断前の位置関係に復元し、これ
ら半導体素子を切り出すものであるから、個々の
PN接合における逆方向ブレークダウン電圧のバ
ラツキを極めて小さくすることができる。したが
つて、動作時に整流素子内部の電界分布が均一に
なり、局部破壊を防止することができる。 The present invention having the above-mentioned configuration is to cut out a plurality of non-parallel straight grooves in a semiconductor single crystal, use these grooves to restore the semiconductor thin plate to the positional relationship before cutting, and cut out these semiconductor elements. Because there is, individual
Variations in the reverse breakdown voltage in the PN junction can be made extremely small. Therefore, the electric field distribution inside the rectifying element becomes uniform during operation, and local breakdown can be prevented.
第１図ないし第７図は本発明の製造方法の工程
を示す図である。
１……半導体単結晶、２……平担部、３，４…
…溝、５……半導体薄板、７……オーミツクメタ
ル、８……ろう材、１０……半導体整流素子、１
２……シリコンゴム、１３……エポキシ樹脂。
1 to 7 are diagrams showing the steps of the manufacturing method of the present invention. 1... Semiconductor single crystal, 2... Flat part, 3, 4...
... Groove, 5 ... Semiconductor thin plate, 7 ... Ohmic metal, 8 ... Brazing metal, 10 ... Semiconductor rectifying element, 1
2...Silicone rubber, 13...Epoxy resin.
Claims (1)
介して複数枚積み重ねて加熱接着した後、これを
所要の大きさに切断する半導体素子の製造方法に
おいて、棒状の半導体単結晶の周辺の一部を平担
にし、該平担部に複数本の直線溝を不平行に刻設
した後、多数の半導体薄板に切断し、該薄板に不
純物拡散処理を施してPN接合を形成し、ろう材
を介して半導体薄板を複数枚積み重ねる際に、前
記刻設溝を利用して薄板切断前の位置関係に復元
し、これを加熱処理した後、所要の大きさに切断
することを特徴とする半導体素子の製造方法。1 In a semiconductor device manufacturing method in which a plurality of semiconductor thin plates with PN junctions formed thereon are stacked and heat-bonded via a brazing material and then cut into a required size, a part of the periphery of a rod-shaped semiconductor single crystal is After making it flat and carving a plurality of straight grooves non-parallelly in the flat part, it is cut into a number of semiconductor thin plates, the thin plates are subjected to impurity diffusion treatment to form PN junctions, and the brazing material is A semiconductor element characterized in that when stacking a plurality of semiconductor thin plates through the groove, the grooves are used to restore the positional relationship before cutting the thin plate, and after heat treating the same, the semiconductor element is cut into a desired size. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14534178A JPS5572034A (en) | 1978-11-27 | 1978-11-27 | Preparing semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14534178A JPS5572034A (en) | 1978-11-27 | 1978-11-27 | Preparing semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5572034A JPS5572034A (en) | 1980-05-30 |
| JPS6117148B2 true JPS6117148B2 (en) | 1986-05-06 |
Family
ID=15382929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14534178A Granted JPS5572034A (en) | 1978-11-27 | 1978-11-27 | Preparing semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5572034A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5230747A (en) * | 1982-07-30 | 1993-07-27 | Hitachi, Ltd. | Wafer having chamfered bend portions in the joint regions between the contour of the wafer and the cut-away portion of the wafer |
| TW230262B (en) * | 1992-12-24 | 1994-09-11 | American Telephone & Telegraph | |
| KR0147672B1 (en) * | 1995-11-30 | 1998-08-01 | 김광호 | Labels to easily distinguish wafers |
| US9640486B2 (en) | 2007-06-13 | 2017-05-02 | Conergy Ag | Ingot marking for solar cell determination |
-
1978
- 1978-11-27 JP JP14534178A patent/JPS5572034A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5572034A (en) | 1980-05-30 |
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