JPS6117173B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to improvements in multiplexers.

A conventional multiplexer selectively outputs output OUT according to the binary level of control signal C, as shown in Fig. 1 for a basic two-input X, Y input.
When trying to output input information from one of two inputs, the other input must be in a state equivalent to being removed from the circuit, and in order to eliminate the influence between each input, Three-state output buffer 1
In many cases, x and 1y are inserted. The use of a three-state output buffer is certainly meaningful. Generally, when the control signal C becomes high level or "1", the output becomes a high impedance state and the output
When looking at this buffer from OUT, it is equivalent to not connecting the buffer, and therefore only the other buffer circuit is involved in signal transmission.

However, in order to do so, one buffer, in the case shown, a buffer 1 related to the second input Y.
A signal obtained by inverting the binary of control signal C by inverter 2 must be applied to y. This is where the drawback of the conventional method arises.

That is, since the inverter 2 always has a time delay of τd, for example, the control signal C is "1" until then.
If you try to switch the input from Y to X by inverting it to "0", the delay of inverter 2 causes the buffer 1y of input Y to transmit a signal, but the buffer 1y of input x 1x also tends to cause an accident in which the signal begins to be transmitted.

Therefore, even though an extra component such as the inverter 2 is required, a circuit that takes measures against the time delay of the inverter 2 is also required.

The present invention has been made in view of the above, and it is an object of the present invention to provide a multiplexer that can eliminate an inverter that has a complicated configuration and is accompanied by a time delay.

FIG. 2 shows an example of a basic two-input multiplexer of the present invention. This figure shows the input and input impedance of the subsequent circuit connected to the output OUT by a resistance R in phantom lines.

Buffers 3 and 4 used in the present invention are three-state output buffers, and outputs are selectively set to a high impedance state or a high impedance state depending on the binary level of the control input C.
That is, it is open when viewed from the rear stage. For the sake of convenience, the explanation will be made assuming that the control signal C is at a high level of "1" and that each buffer is in a high impedance output state, but the reverse is also possible.

First, we will discuss the physical circuit configuration. The first input X and the output OUT are connected via a pair of series resistors r ₁ and r ₂ . A first three-state buffer 3 is connected between the connection point P of the resistor and the ground E,
A second three-state buffer 4 is inserted in series between the output OUT and the second input Y. The control inputs C ₃ and C ₄ of each buffer receive the control signal C in common.

With such a configuration, the control signal “0”,
Depending on "1", the X and Y inputs can be selected rationally and without the problem of time delay.

As shown in FIG. 3A, if the control signal C is now set to "1", the outputs of both buffers 3 and 4 will be in a high impedance state in accordance with the promise made earlier. This is schematically shown in FIG. 3A as a switch being opened. Then, as is clear from the figure, only the X input appears at the output OUT, although it passes through the resistors r ₁ and r ₂ .

Next, when the control signal C is set to “0”, both resistors
The connection point P between r ₁ and r ₂ falls to earth E. This is schematically shown in FIG. 3B with each buffer in the closed state. Input X is grounded via resistor _r1 , and input Y is coupled to output OUT.

In this figure, the two resistors r ₁ and r ₂ are divided at the connection point P, and the buffer 3 is also shown as a switch at two locations, but this is done to make the equivalent circuit easier to understand. be.

As described above, according to the present invention, there is no need for an inverter or the like having a delay element other than the buffers 3 and 4 that operate simultaneously, so problems such as the so-called "glitch" caused by the overlap of both inputs can be solved in principle. There is an advantage that this does not occur. Of course, the circuit configuration is also extremely simple since only resistors r ₁ and r ₂ are added as passive elements in place of the troublesome inverter as an active element.

However, when the X input is selected as shown in Figure 3A, the X input is sent to the output OUT with a voltage division ratio of R/r ₁ +r ₂ +R when viewed as an analog potential, whereas when the Y input is selected, As clearly shown in Figure 3B, the equivalent input impedance of the subsequent circuit is the parallel composite value of R and _r2 , but both are "0" of the X and Y inputs, respectively, when viewed from the circuit input connected to the output OUT. ”,
It is extremely easy to set the values of the resistors r ₁ and r ₂ so that the “1” level can be determined,
It can't be a problem.

The basic two-input multiplexer shown in the second and third figures can easily be made into three inputs by cascading as shown in the fourth figure, and can further increase the number of stages to provide multiple inputs. If we consider the circuit shown in the second diagram as one module 5 as surrounded by imaginary lines, the fourth
The illustrated circuit can be viewed as one in which the first input X of one module 5 is connected to the output OUT' of another module 5' having the same content. Therefore, the same symbol with or without a dash indicates the same constructor.

The operation of this circuit is clear from the previous description.
That is, if the control signal C' of the first stage is "1", X' appears as the output OUT at the X input of the next stage, and at this time,
If the control signal C at the next stage is "1", this X' appears as the final output OUT. Hereinafter, C′=“0”,
When C="1", it becomes Y', and when C="0", it becomes Y.

However, as the number of cascade stages increases, the design
Since the range of determining r ₁ , _{r 2 ,} r ₁ ′, r 2 ′, r ₁ ″, r ₂ ″... becomes narrower or more difficult, for modules that are planned to be cascaded from the beginning,
As shown in FIG. 5, it is preferable to send the signal through a buffer 6 having high input impedance and low output impedance.

As is clear from the above-mentioned operation and control modes, the functions required of the three-state output buffer used in the present invention are not as good as those of a normal analog output buffer.
It also has substantially the same functionality as a switch.

Therefore, the above description of Figure 3 also indicates the possibility of application of analog switches, although some analog switches are Some devices cannot exhibit a high output impedance, and are therefore unsuitable for use in implementing the present invention.

Therefore, in the present invention, in addition to the above-mentioned three-state output buffer, an analog switch that can realize a satisfactory high impedance state especially when off is also included as a device that can be used in the circuit elements 3 and 4 in the embodiment. Conceptually, the term three-state output switch can be used.

Therefore, if we redefine this three-state output switch, it has an input terminal, an output terminal, and a control terminal, and when the control terminal receives a binary level control signal, the logic applied to the input terminal is Outputs the same logic signal as the signal to the output terminal, and when receiving the other binary level control signal, puts the output terminal into a high impedance state regardless of the logic signal applied to the input terminal. It can be said that it is a thing. Of course, as usual, ground E in the embodiment corresponds to a logic "0".

In any case, as described in detail above, the present invention provides a highly reliable multiplexer with a simple circuit configuration and no problems caused by time delays.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of a conventional multiplexer.
FIG. 2 is a schematic configuration diagram of a basic embodiment of the present invention,
3A and 3B are respectively explanatory diagrams of the operation thereof, and FIGS. 4 and 5 are respectively schematic diagrams of the configuration of other embodiments. In the figure, 3 and 4 are three-state output buffers, and r ₁ and r ₂ are resistors.

Claims (1)

[Claims] 1. A multiplexer that selectively couples first and second logic inputs X and Y to a logic output OUT according to the binary level of a control signal C, comprising: an input terminal, an output terminal, and a control terminal C3. , C4, and when one of the binary level control signals is received at the control terminals C3 and C4, it outputs the same logic signal as the logic signal given to the input terminal to the output terminal, and outputs the same logic signal to the output terminal. Two three-state output switches 3, 4 are used that put the output terminal in a high impedance state when receiving a binary level control signal, regardless of the logic signal applied to the input terminal; The input X and the logic output OUT are connected through a pair of series resistors r1 and r2, and the three-state output switch 3, one of 4 3
is inserted so that its output terminal is on the side of the series resistance connection point P; and the other one of the three-state output switches 3 and 4 is inserted between the second logic input Y and the logic output OUT. 4 is inserted so that its output terminal is on the logic output OUT side; and the control signal C is connected to the control terminals C3 and C4 of the two three-state output switches 3 and 4.
A multiplexer characterized by: