JPS6118223B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for a main storage device in a computer system, and particularly to a control method for a storage protection mechanism.

As a mechanism to ensure the reliability of computer systems, a memory protection mechanism is provided to prevent the contents of the main storage (MS) from being inappropriately referenced or rewritten. There is. A memory protection mechanism usually divides the storage area of main memory into blocks called pages (2K bytes,
or 4K bytes), and each block is assigned a several-bit code called a key.
When the central processing unit (CPU) etc. refers to this block, if the code in the central processing unit does not match the key, reference to this area will not be permitted.

Key Storage: A collection of keys assigned to each page in main memory.
KS). Due to the nature of the memory protection mechanism, references to the KS must be made prior to references to the MS.

FIG. 1 shows the configuration of a multiprocessor system.

In a multiprocessing system that combines multiple CPUs with extremely high-speed processing power, shared
In order to efficiently process reference requests to MS,
As shown in the figure, a multiprocessing device (Multiprocessing device)
Control Unit (MCU) 3 controls the MS. Furthermore, input/output devices such as magnetic tapes and disks are called input/output processors (IOPs).
It is connected to the MCU via 2 and 2', and this allows the MS
Data is transferred between

The MS is interleaved in order to process reference requests from the CPU and IOP, and each interleaved bank 5 is configured to be able to operate independently.

Requests from CPU1, 1', IOP2, 2' are
Request Stack within MCU3
RS) 310 to 313, and issues a request to the bank control unit 32 from there. If the requested bank 5 is not busy, the request is sent to that bank of the MS for processing. The CPU and IOP issue requests to the MCU independently, and if there is no contention in the MS bank, requests are sent to multiple banks simultaneously.

Now, as mentioned above, before referring to the MS, it is necessary to refer to KS4 and check whether it is possible to refer to the relevant area of the MS, but in the conventional technology, multiple requests are simultaneously When referring to , it was necessary to take precedence. In this method, even if the processing power of the CPU, IOP, MS, etc. improves, a queue forms at the KS, and the problem arises that it is not possible to make full use of that power.

The purpose of the present invention is to
The objective is to improve the processing efficiency of the entire system without limiting the performance of the IOP or MS, and also to achieve a protection function for the main storage device.

In the present invention, the KS
Its purpose is to independently perform MS memory protection checks. At this time, the problem that arises from having multiple KSs is ensuring consistency between the KSs, which means that the key values for the same page in the MS must be the same in all KSs.

The present invention will be explained below with reference to Examples.

FIG. 2 is a detailed block diagram of the MCU 3.
Requests from the CPU and IOP are stored in request stacks (KS) 310 to 313. In FIG. 2, up to two requests are shown stacked due to the busy state of the MS bank. The requests stored in RSs 310-313 are sent to bank controllers 320-327 corresponding to the bank indicated by the lower bits of the address. A bank control unit is provided for each bank, and manages the busy state of the bank. If multiple requests are concentrated on the solder, it resolves conflicts between them, and if it can be accepted, it handles one request. Storage Request Register:
Set the address, write data, etc. to SRR) 330 to 337, and send it to the MS bank.

In the case of a read request, the data read from the MS bank is stored in the read data register (Fetch
Data Reqister (FDR) 340 to 341 is set, and then sent to the requesting CPU or IOP.

The requests stored in RS310 to RS313 are sent to the bank control unit, and at the same time, the requests are sent to the KS control unit 41.
Requests are also made to check the memory protection.

In Figure 2, there are two CPUs and two IOPs.
An example is shown where it is connected to an MCU, and KS says that there are four sides for each of these request sources.

Now, processing operations in KS can be classified into the following three types.

(1) Memory protection behavior based on MS references from CPU or IOP.

(2) Write operation to KS from CPU.

(3) KS read operation from CPU.

First, when a request for MS reference is issued from the CPU or IOP, the CPU or IOP sends the request address and a key code. The KS reads the key according to the requested address and compares it with the key code sent. If the key code from the CPU or IOP is 0, or if the value matches the key read from the KS, reference to the corresponding MS area is permitted. If this is not the case, the sending of the request to the MS bank is prohibited as a memory protection error, and the state of this memory protection error is reported to the request source.

In general, each data in the KS has a key value for memory protection as well as a reference bit (Reference-bit).
bit: R-bit) and change bit:
C-bit), the R-bit is set to 1 if the reference to the MS is a read, and the R-bit is set to 1 if the reference to the MS is a read.
Set the - bit and C- bit to 1 to record the usage status of the MS.

KS checking for storage protection is performed on one KS for each requester, eliminating the wait caused by competing KSs.

Now, when a write operation from the CPU to the KS is requested, this is usually called SSK (Set Storage Key)
At this time, the request address indicates the address of the KS to be changed.

When making this request, it is necessary to write not only to the KS corresponding to the request source but also to the other three KSs. At this time, the KS may be referenced for MS references from other request sources. Therefore, a write request to KS is RS311 (or 31
2), after all KS references by requests previously accepted by the MCU 3 (that is, stored in RSs 310 to 313) have been completed, writing to the four KSs must be performed simultaneously. The KS control unit 41 performs order control during this time.

Finally, the read operation of the KS from the CPU is typically
Executed by ISK (Insert Storage Key) instruction,
As with the SSK instruction, the requested address indicates the address of KS.

At the time of this request, when this request is stored in RS311 (or 312), the RS
By all requests stored in 310-313
After the KS lookup is complete, read the requested key from the KS. At this time, the KS corresponding to the requesting CPU
It is necessary to read not only from the KS but also from the other three KS. This is because the value of the key is not changed by a normal KS reference (i.e., other than by the SSK instruction), but the R-bit,
This is because the value of the R or C-bit of all KSs may differ depending on the MS reference from each request source. Therefore, when making a reference using an ISK instruction, it is sufficient to OR the key values read from the four KSs and the R and C bits, and send the result to the request source of the ISK instruction.

The order control required when processing the ISK instruction is executed by the KS control unit 41, as in the case of the SSK instruction.

As mentioned above, references to KS are from RS310 to
313 to the KS control unit 41, and then a key request register (Key request register) corresponding to each KS is issued.
Set the address and key code from the requester to Request Register (KRR) 420-423.

When referring to MS, the key codes set in KRR420-423 are sent to comparators 440-443, read out from KS, and sent to key output registers (KOR) 430-433.
is compared with the key value set in .

At the time of the SSK instruction, the key code from the CPU is sent from the KRR 421 (or 422) to all KSs according to instructions from the KS control unit 41.

At the time of ISK instruction, the key value read from all KS is one part, KOR430 to 43 corresponding to each KS.
3 and an OR circuit 450 of their outputs.
(or 451) is sent to the requesting CPU.

Above, we have explained the method of having a KS for each request source to the MS and referring to the KS in parallel.
As can be easily inferred, it is also possible to have multiple KSs corresponding to the banks of the MS and check the memory protection for each bank in parallel.

As explained above, by having multiple KSs for each request source and a KS control unit that controls the order of requests from those request sources, it is possible to eliminate unnecessary queues that may occur due to references to KSs. , CPU, IOP
Alternatively, it becomes possible to utilize the original performance of MS.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a multiprocessor system, Figure 2
The figure is a block diagram showing one embodiment of the present invention. 3...Multi-processing control unit (MCU), 310-3
12...Request stack (RS), 50-57...
MS bank, 41...Memory protection control unit, 440~
443...Comparator, 450 and 451...OR
Circuit, KS...Key storage.

Claims (1)

[Scope of Claims] 1. Key storage means provided for each request source, each including a key storage means for holding data for protecting the memory of the storage device, and capable of communicating between different request sources in response to a request to the storage device. Here, we have multiple storage protection devices that each perform storage protection checks independently and in parallel, and when data is written to or read from the storage protection devices, mutual references are made between requesters to the multiple storage protection devices. A storage protection control method comprising: a storage protection control device that controls the order of requests; and a storage protection control system.