JPS6118346B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a method for manufacturing a semiconductor device with excellent high frequency characteristics.

In bipolar transistors, in order to improve high frequency characteristics, it is necessary to reduce the junction depth, and it is known that arsenic is better than phosphorus as an emitter impurity (for example, solid Solid-State Electronics 1972, 249-258
page). In order to control the former junction depth shallowly, there is a method of forming the base region and emitter region using ion implantation, but in this method, crystal defects are introduced during ion implantation when forming the emitter region, and the emitter region is - The base-to-base breakdown voltage (BV _EBO ) decreases, and it is difficult to control the collector junction depth (Xj _BC ) of transistors with an emitter junction depth of 1000 Å or less using the method of directly implanting B ⁺ ions into the silicon surface. There were drawbacks such as:

On the other hand, in the method of forming the base region by thermal diffusion and the emitter region by thermal diffusion of arsenic, the BV _EBO does not decrease as in the case of the ion implantation method described above, but it is still possible to form the base region by thermal diffusion _{of arsenic} . Formation of the base region is difficult with poor reproducibility.

An object of the present invention is to provide a method for forming a bipolar transistor having an extremely shallow collector junction depth (Xj _BC ) (2000 Å) and having arsenic as an impurity in the emitter region with high precision and high reproducibility.

In this invention, when forming a base region, a thin silicon oxide layer is previously provided on the surface of a silicon substrate, B ⁺ ions are implanted through this silicon oxide layer to form a base region, and then thermal diffusion is performed. This forms an emitter region containing arsenic as an impurity.

According to this invention, by controlling the thickness of the silicon oxide film, the range of B ⁺ ions during B ⁺ ion implantation is controlled, and then arsenic is thermally diffused for a short time to deepen the junction. A bipolar transistor with extremely shallow depth is obtained.

In other words, transistors with shallow junction depths can be fabricated with high accuracy and reproducibility without causing a drop in breakdown voltage (BV _EBO ).

Next, an example of this firing will be described with reference to the drawings.

First, as shown in FIG. 1a, the film thickness formed on the surface of the N-type silicon single crystal substrate 1 is 5000 Å to
Openings 3, 3' are provided in the silicon dioxide layers 2, 2' with a thickness of 10,000 Å, and high concentration P-type impurity regions (graft bases) 4, 4' are formed through these openings 3, 3'.
The surface impurity concentration in regions 4 and 4' is approximately 10 ¹⁹ particles/cm ³
It is formed by thermal diffusion method.

Next, as shown in FIG. 1b, the silicon oxide layer 2' formed on the surface between the P-type impurity regions 4 and 4' is removed to expose the silicon surface, and then thermal oxidation is performed. 600 on the surface of type impurities 4 and 4' and on the surface of silicon region 1' surrounded by regions 4 and 4'.
A thermal oxide film 2'' with a thickness of 1,000 Å to 1,000 Å is formed. This thermal oxidation is performed in a saturated steam atmosphere at 900°C. The thermal oxide film 2 ^is also oxidized, and the film thickness increases slightly. 5 is implanted through the thermal oxide film 2, 2''. The B ⁺ ions have an acceleration energy of 20~
Implantation is performed at a dose of 5×10 ¹³ to 20×10 ¹³ ions/cm ² at 40 keV.

Subsequently, as shown in FIG. 1C, heat treatment is performed at 900° C. for about 15 minutes to form a P-type base region 6 directly under the thermal oxide film 2″.The depth of the region 6 is 500° to 500°.
At 1500 Å, the surface impurity concentration is 1×10 ¹⁸ to 5×
10 ^{to 18} pieces/ ^cm3 . Note that since the oxide film 2 is thick, no P-type region is formed in the region below it.

Next, as shown in FIG. 1d, holes are selectively formed in the thermal oxide film 2'' to selectively expose the surface of the P-type base region 6. A polycrystalline silicon layer 7 containing a high concentration of arsenic is formed on the upper surface and the upper surface of the P-type base region 6 with the above-mentioned surface exposed.
Deposit 3000 to 5000 Å. The polycrystalline silicon layer 7 is deposited using silane (SiH ₄ ) and arsenic trichloride (AsCI ₃ ) at 750° C., and the polycrystalline silicon layer 7 contains 1 to 10% by weight of arsenic. Then, 950℃
Arsenic drive-in at temperatures between 1000℃ and 1000℃
Diffusion is performed to form an emitter region 8 containing arsenic at a high concentration. The depth (Xj _E ) of the emitter region 8 is 1000 to 1500 Å, and the surface impurity concentration is
The number is 1.5×10 ²⁰ to 25×10 ²⁰ pieces/cm ³ . Additionally, the collector junction position moves slightly during arsenic diffusion, and the collector junction depth (Xj _BC ) is approximately 2000 when the arsenic diffusion is completed.
It becomes Å. Furthermore, if arsenic emitter diffusion is performed from a polycrystalline silicon layer, emitter dips will not occur and the base width can be sufficiently narrowed. Therefore, as an arsenic diffusion method, a method using a polycrystalline silicon layer containing arsenic as a diffusion source is an excellent method. There is.

Finally, the oxide film layer on the top surface of the P-type base contact regions 4, 4' is removed, the emitter electrode 9 and the base electrode 2''10 are formed using aluminum electrode wiring, and unnecessary portions of the polycrystalline silicon layer are gradually removed. As a result, a transistor having an extremely shallow junction depth according to the present invention can be obtained.

FIG. 2 is a curve diagram showing the relationship between the current amplification factor (h _FE ) and the silicon oxide film (Å) of the transistor manufactured according to the above embodiment.

Here, “B ⁺ ion implantation is the acceleration energy
As shown in the ^figure , the silicon ^oxide film is 600 Å
When h _FE is about 70, the silicon oxide film thickness is 800
h _FE increases to about 110 at Å. That is, h _FE can be easily controlled by changing the thickness of the silicon oxide film.

According to the method for manufacturing a semiconductor device of the present invention, a semiconductor device having an extremely shallow collector junction depth (2000 Å) and containing a high concentration of arsenic as an emitter impurity can be easily manufactured. Therefore, semiconductor devices with excellent high frequency characteristics can be manufactured with good reproducibility and precision.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the manufacturing process of an embodiment of the present invention, and FIG. 2 is a curve diagram showing the relationship between h _FE and silicon oxide film thickness. 1...N-type epitaxial silicon substrate, 2, 2',
2"...Silicon oxide layer, 4,4'...High concentration P type impurity region (craft base), 5..."B ⁺ ion, 6...P
type impurity region (active base region), 7... polycrystalline silicon layer, 8... N type emitter region, 9... emitter electrode, 10... base electrode.

Claims (1)

[Claims] 1. A step of previously providing a thin silicon oxide film on the surface of a semiconductor substrate, a step of implanting impurity ions into the substrate through the thin silicon oxide film to form a shallow base region, and selectively implanting the silicon oxide film on the base region. a step of exposing the surface of the substrate by forming an opening, a step of depositing a polycrystalline silicon layer containing 1 to 10% by weight of arsenic on the upper surface using silane and arsenic trichloride, and a step of exposing the surface of the substrate by forming an opening through the opening. A method of manufacturing a semiconductor device, comprising the step of diffusing arsenic into the substrate to form an emitter region.