JPS6118772B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input control method suitable for use in an information processing apparatus using a multi-item input device as an information input section.

In recent years, the information input section of an information processing system has an input designation element table composed of a key mat, and a predetermined sheet composed of a plurality of sheets having a plurality of key through holes and an item recording section at a predetermined position on the key mat. Place a book for inputting items with the number of pages, open the desired input item page, and select and specify the key corresponding to the item name to be input. A so-called book-type multi-item input device has been developed that is configured to output unique item code information for information. In an information processing device that uses this type of book-type multi-item input device as an input section, the processing device inputs code information and associated page information for the operated input designation element in the input designation element table, and the operator Although the configuration is such that input processing of input item information is executed by specifying the input item information,
At this time, if the input designation element is operated to input the next item information while the processing device receives code information by operating the input designation element and executes the input processing, that is, the information by the operation of the input designation element If the input interval is shorter than the input information processing time, the processing device will not receive correct item input information associated with the operation of the input designation element, resulting in a so-called timing error.

This invention was made in view of the above-mentioned circumstances, and in an information processing device using a multi-item input device as an input section, when the information input interval by the operation of the input designation element is shorter than the processing time of the input information, It is an object of the present invention to provide an input control method that can reliably detect timing errors using only a simple hardware configuration.

An embodiment of the present invention will be described below with reference to the drawings. Figure 1 shows a multi-item input device book in a predetermined position on the keypad in a two-page spread state (page open state).
In the figure, K ₁ , K ₂
...K _o , are keys for inputting items arranged in a matrix at predetermined intervals, 11 is made of, for example, a plastic plate, and a hole H for passing the key is formed at a predetermined position, and this hole H... A predetermined number of sheets 1 on which item recording sections X are formed corresponding to
2 and 12 are bound by binding fittings 13, 13, etc., which are attached at different positions for each sheet, and one page is formed by a pair of spread-open left and right sheet surfaces. This is an input device book (hereinafter simply referred to as a book). In addition, S ₁ , S ₂ ...S _n are the sheets 12, 12
...provided corresponding to each one of the binding fittings 13..., and each corresponding to the sheets 12, 1.
This is a page detection switch that is subjected to switching control by being pressed and controlled by the binding fittings 13, 13, . . .

FIG. 2 is a block diagram showing the circuit configuration of the main part of the present invention. In the figure, 101 is an input detection circuit for detecting the input of the operated key Ki of the key mat, and 102 is the output signal of this input detection circuit 101. 103 is an encoder that outputs unique code information for the operated key Ki, 103 is a strobe generation circuit that receives the output signal of the input detection circuit 101 and generates a strobe signal ST for information reading control, 104 is this strobe generator a data input register that stores code information output from the encoder 102 based on the strobe signal ST obtained from the strobe generation circuit 103; 105 is a processing control circuit that performs various processing and input/output control;
106 is a data line used for data input/output of this processing control circuit 105. Further, 107 has a function of generating an interrupt request signal for sending out code information, and the next key operation is performed before the processing control circuit 105 finishes inputting the code information stored in the data input register 104. This is a timing error detection circuit that has the function of detecting timing errors when the timing error occurs. This timing error detection circuit 107 includes an inverter 201 to which the strobe signal obtained from the strobe generation circuit 103 is input, and this inverter 20
The set state is reached by the rising edge output of the signal outputted from 1 (the trailing edge timing of the strobe signal ST), and the falling edge output of the read signal R for error determination after the information input processing outputted from the processing control circuit 105. a first D-type flip-flop (hereinafter referred to as D-FFA) 202 that is directly cleared at (leading edge timing); an OR gate 203 that receives the output of the inverter 201 and the read signal R;
The above D-
A second D-type flip-flop (hereinafter referred to as D-FFB) 2 that reads the state of the FFA 202 and is directly cleared by the system clear signal CLR.
04. Therefore, the above D-
The set state signal (Q=“1”) of FFA202 is used as the interrupt request signal ATN, and also as the above-mentioned D-FFB2
The set state signal of 04 is a timing error signal.
Each is sent to the processing control circuit 105 as an ERR.

The operation will now be explained with reference to the time charts shown in FIGS. 3a to 3f. By operating the key Ki corresponding to the item name to be input by referring to the item recording section A signal specific to the key Ki is output, which causes the encoder 102
Code information corresponding to the above-mentioned operation key Ki is output from. On the other hand, based on the output signal of the input detection circuit 101, the sweep lobe generation circuit 103 outputs a strobe signal ST as shown in FIG.
and is sent to the inverter 201 of the timing error detection circuit 107. As a result, code information specific to the operation key Ki output from the encoder 102 is stored in the data input register 104. In addition, FIG. 3b is inverted by the inverter 201.
The strobe signal shown in is sent to the clock terminal CK of the D-FFA202 and also to the OR gate 2.
Clock terminal CK of D-FFB204 via 03
The signal contents of the D terminal are read at the rising edge output (timing of the trailing edge of the strobe signal) of the signal input to the clock terminal CK. At this time D
-FFB 204 reads "0" because the set output terminal Q of D-FFA 202 is still "0", and therefore maintains a clear state as shown in Figure 3 f, but D-FFA 202 has a D terminal Always “1”
Since the level signal _Vcc is supplied, it reads "1", and therefore the inverter 2 outputs "1" as shown in FIG.
It enters the set state in synchronization with the rising output of 01.
This set state signal of the D-FFA 202 is supplied to the D terminal of the next stage D-FFB 204, and is also supplied to the processing control circuit 1 as an interrupt request signal ATN.
Sent to 05. After receiving this interrupt request signal ATN, the processing control circuit 105 reads the code information stored in the data input register 104, and further reads the page information, book information, etc. associated with this code information, and reads the items specified by the operator. Performs information input processing for input. Further, in the processing control circuit 105, when the information input processing is finished, the third
A read signal R for error determination shown in FIG. c is sent out.

Here, if the strobe signal ST is not output by the next key operation before the read signal R is input to the timing error detection circuit 107, the D-FFB 204 maintains the clear "0" state and the processing control Circuit 105 is D-FFB20
It is recognized from the set output terminal signal "0" of No. 4 that no timing error has occurred, and the above-mentioned input processed information is treated as normal item input information.

Next, if the next key operation is performed before the input processing of the code information stored in the data input register 104 is completed, that is, the processing control circuit 104
The read signal R is not output from 5, and D-FFA2
The operation will be described in the case where the strobe signal ST is output from the strobe generation circuit 103 by the next key operation when the interrupt request signal ATN is output from the strobe generator 02 (the D-FFA 202 is in the set state). In this case, D-FFA20
The set state signal (Q="1") of the second stage is the D-
It is supplied to the D terminal of the FFB 204, and when the strobe signal ST is output from the strobe generation circuit 103, this signal ST is supplied to the clock terminal CK of the D-FFA 202 via the inverter 201, and further via the OR gate 203. D-FFB
204's clock terminal CK. At this time, since "1" is always supplied to the D terminal of the D-FFA202, the inverter 2 is connected to the clock terminal CK.
Even if the rising output of 01 is supplied, the set state (Q=“1”) is maintained as shown in FIG. 3d, but
D-FFB204 is the OR gate 2 shown in Figure 3 e.
D-FFA20, which is input to the D terminal by supplying the rising output of 03 to the clock terminal CK.
In order to read the set state content "1" of 2, the stored content changes from "0" to "1" as shown in FIG. 3f. Therefore, D-FFA202, D-FFB204
Both are in the set state, and the timing error signal ERR of the "1" level is output from the set output terminal Q of the D-FFB 204. Thereafter, the processing control circuit 105 outputs the read signal R after the input processing operation, so that the timing error signal ERR is read into the processing control circuit 105 via the data line 106, and the read signal R D-FFA2 at the falling output (leading edge) of
02 is directly cleared, or gate 203
The D-FFB 204 changes the content of the D-FFA 202 to “0” at the rising edge (trailing edge) of the read signal R after passing through the
Load. In this way, if a key operation is performed when the processing control circuit 105 is not ready to input and process the code information corresponding to the next key operation, a timing error is detected.

As described in detail above, according to the present invention, in an information processing apparatus using a multi-item device as an input section, the timing when the information input interval due to the operation of the input designation element is shorter than the processing time of the input information Errors can be detected reliably with a simple hardware configuration,
This ensures highly reliable input information processing.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention, in which Fig. 1 is a plan view showing the arrangement of keys and switches on a key mat, and a book placed on the key mat in a spread state, and Fig. 2 is a main part. FIG. 3 is a block diagram showing the circuit configuration of the circuit, and FIG. 3 is a time chart for explaining the operation. 11...Book, K ₁ , K ₂ ...K _o ...Key, S ₁ , S ₂ ...
S _n ...Switch for page detection, 101... Input detection circuit, 102... Encoder, 103... Strobe generation circuit, 104... Data input register, 10
5... Processing control circuit, 107... Timing error detection circuit. 201...Inverter, 202...First D
203...OR gate, 204...second D-type flip-flop (D-FFB).

Claims (1)

[Claims] 1. An input designation element table in which a plurality of input designation elements are arranged in a matrix, an input detection circuit that outputs a unique signal for the operated input designation element of this input designation element table, and processing of various information and input/output control. a code generation section that outputs code information specific to the input designation element operated based on the output signal of the input detection circuit; and a code generation section that generates a strobe signal based on the output signal of the input detection circuit. a strobe generation circuit; a storage section that stores code information obtained from the code generation section based on the strobe signal obtained from the strobe generation circuit; and a storage section that interrupts the processing control circuit in response to the strobe signal obtained from the strobe generation circuit. a first means for transmitting a signal and canceling the output of the interrupt signal in response to a read signal transmitted from the processing control circuit; and a first means for transmitting the strobe signal when the first means is outputting the interrupt signal. an error detection circuit having a second means for transmitting a timing error signal to the processing control circuit by receiving a timing error signal, and the code generation section includes a second means for sending a timing error signal to the processing control circuit by receiving the code information stored in the signal storage section. An input control method characterized by having a functional configuration that determines an error when code information is output by the next input designation element operation.