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JPS6118864B2 - - Google Patents
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JPS6118864B2 - - Google Patents

Info

Publication number
JPS6118864B2
JPS6118864B2 JP54007968A JP796879A JPS6118864B2 JP S6118864 B2 JPS6118864 B2 JP S6118864B2 JP 54007968 A JP54007968 A JP 54007968A JP 796879 A JP796879 A JP 796879A JP S6118864 B2 JPS6118864 B2 JP S6118864B2
Authority
JP
Japan
Prior art keywords
chip
board
mounting
substrate
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54007968A
Other languages
Japanese (ja)
Other versions
JPS5599752A (en
Inventor
Toshihiko Tsuge
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Original Assignee
CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHO ERU ESU AI GIJUTSU KENKYU KUMIAI filed Critical CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Priority to JP796879A priority Critical patent/JPS5599752A/en
Publication of JPS5599752A publication Critical patent/JPS5599752A/en
Publication of JPS6118864B2 publication Critical patent/JPS6118864B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires

Landscapes

  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 本発明はICチツプの実装構造に関する。[Detailed description of the invention] The present invention relates to an IC chip mounting structure.

近年、ICチツプのLSI化、高密度実装化に伴
い、ICチツプ実装の低熱抵抗化の必要性が増大
してきている。しかるに、従来のICチツプ実装
構造で、ICチツプのフエイスアツプ実装構造に
おいては、実装基板に配線と熱放散の両機能を持
たせていたため、ICチツプの熱放散の程度は基
板材料の熱伝導度に依存し、低熱抵抗化がはかり
にくかつた。
In recent years, with the shift to LSI and higher density packaging of IC chips, there has been an increasing need for lower thermal resistance in IC chip packaging. However, in the conventional IC chip mounting structure, in which the IC chip is mounted face-up, the mounting board has both wiring and heat dissipation functions, so the degree of heat dissipation from the IC chip depends on the thermal conductivity of the board material. Therefore, it was difficult to reduce the thermal resistance.

本発明は上述の従来方法の欠点を除去したIC
チツプ実装構造を提供することにある。
The present invention provides an IC that eliminates the drawbacks of the conventional methods described above.
The purpose is to provide a chip mounting structure.

この発明のICチツプ実装構造は、ICチツプの
フエイスアツプ実装において、ICチツプの熱放
散を実装基板を通さずICチツプ裏面から直接行
うことを特徴とする。
The IC chip mounting structure of the present invention is characterized in that in face-up mounting of an IC chip, heat dissipation of the IC chip is performed directly from the back surface of the IC chip without passing through the mounting board.

第1図はICチツプ実装用基板を示す斜視図で
ある。第1図において、基板1には開口2の貫通
する空胴3があり、開口2の周囲には、ICチツ
プ固定用のエポキシ樹脂、シリコン樹脂等の樹脂
接着剤又ははんだ等の接合剤4がある。また基板
上にはICチツプの接続パツドと接続するための
パターン5がもうけられている。
FIG. 1 is a perspective view showing a board for mounting an IC chip. In FIG. 1, a substrate 1 has a cavity 3 through which an opening 2 passes, and around the opening 2, a resin adhesive such as epoxy resin or silicone resin or a bonding agent 4 such as solder is applied for fixing an IC chip. be. A pattern 5 is also formed on the board for connection to the connection pad of the IC chip.

第2図は本発明の第1の実施例を示す斜視図で
ある。第2図において、基板1は水、フレオン等
の液体金属等の熱伝導性の良い流体6の上にあ
り、基板1上には、接合剤4で固定されたICチ
ツプ7が実装されている。そしてICチツプ7の
接続パツド8とパターン5はワイヤ9で結ばれて
いる。第3図は第2図のA−A′断面図である。
第3図において、ICチツプ7は接合剤4によつ
て基板1に固定され、基板1の空胴3を通して
水、フレオン等の液体、又は液体金属等の熱伝導
性の良い流体6が直接にICチツプ裏面に接する
ため、ICチツプ7の熱放散は有効に行なわれ
る。
FIG. 2 is a perspective view showing a first embodiment of the invention. In FIG. 2, a substrate 1 is placed on a fluid 6 with good thermal conductivity such as water or a liquid metal such as Freon, and an IC chip 7 fixed with a bonding agent 4 is mounted on the substrate 1. . The connection pad 8 of the IC chip 7 and the pattern 5 are connected by a wire 9. FIG. 3 is a sectional view taken along line A-A' in FIG.
In FIG. 3, an IC chip 7 is fixed to a substrate 1 with a bonding agent 4, and a fluid 6 with good thermal conductivity such as water, a liquid such as Freon, or a liquid metal is directly applied through a cavity 3 of the substrate 1. Since it is in contact with the back surface of the IC chip, heat dissipation from the IC chip 7 is effectively performed.

こ実装方法による熱放散の有効性を基板に空胴
がなくICチツプの裏面全面がセラミツク基板、
あるいはエポキシ樹脂基板に接合されている実装
方法と比較してみる。例えばICチツプサイズを
2□mmとし、ICチツプと基板とを接合する接合剤
の熱抵抗を考慮に入れず、しかもICチツプから
放散された熱はICチツプ裏面を通して基板内に
45゜の角度で広がつていくとすると、アルミナ基
板の熱抵抗は3.3℃/Wである。アルミナ基板のか
わりにエポキシ樹脂基板を用いると熱抵抗は1.0
×103℃/Wとなる。一方水、フレオン等の液体を
基板下に流した場合は、おおまかに言つて上記
ICチツプ下部分の基板の熱抵抗分だけ、熱抵抗
が消失したと考えることができ、熱抵抗は下るこ
とになる。
The effectiveness of heat dissipation by this mounting method is demonstrated by the fact that there is no cavity on the board and the entire back surface of the IC chip is made of ceramic.
Or compare it with a mounting method that is bonded to an epoxy resin board. For example, if the IC chip size is 2 □mm, and the thermal resistance of the bonding agent used to bond the IC chip and the board is not taken into account, the heat dissipated from the IC chip is absorbed into the board through the back surface of the IC chip.
Assuming that it spreads at a 45° angle, the thermal resistance of the alumina substrate is 3.3°C/W. Thermal resistance is 1.0 when an epoxy resin substrate is used instead of an alumina substrate.
×10 3 ℃/W. On the other hand, if a liquid such as water or Freon is poured under the board, the above will generally occur.
It can be considered that the thermal resistance has disappeared by the amount of thermal resistance of the substrate below the IC chip, and the thermal resistance will decrease.

第4図は第2の実施例を示す断面図である。第
4図において、基板の空胴は斜めにあけられてい
る。空胴の形状は、このようにさまざまな形をと
りうる。
FIG. 4 is a sectional view showing the second embodiment. In FIG. 4, the cavity of the substrate is diagonally opened. The shape of the cavity can thus take various shapes.

第5図は多数個のICチツプが第2図のように
塔載された基板を冷却のために実装した実施例を
示す斜視図である。第5図において、ICチツプ
7の塔載された基板が筒10の上に2枚塔載され
ている。筒10の中には、水、フレオン等の液体
又は液体金属等の熱伝導性のよい流体が入つてお
り、熱交換器11を通して熱が冷却され、矢印1
2の方向に流体は循環する。
FIG. 5 is a perspective view showing an embodiment in which a board on which a large number of IC chips are mounted as shown in FIG. 2 is mounted for cooling. In FIG. 5, two substrates on which IC chips 7 are mounted are mounted on a cylinder 10. As shown in FIG. The tube 10 contains a liquid such as water or Freon, or a fluid with good thermal conductivity such as a liquid metal, and the heat is cooled through a heat exchanger 11 as indicated by the arrow 1.
The fluid circulates in two directions.

第6図は第5図の状態で基板1間の電気的結合
のため、ボード13にコネクタ14で基板1をと
りつけた場合の断面図である。第6図において
ICチツプ7の裏面に直接水、フレオン等の液体
又は、液体金属等の熱伝導性の良い液体6が触れ
ているのがわかる。
FIG. 6 is a cross-sectional view of the state shown in FIG. 5 when the substrate 1 is attached to the board 13 with the connector 14 for electrical connection between the substrates 1. In Figure 6
It can be seen that the back surface of the IC chip 7 is in direct contact with a liquid such as water, Freon, or a liquid 6 with good thermal conductivity such as liquid metal.

本発明のICチツプ実装構造を用いると、低熱
低抗化がはかられ、高集積化された大電力ICチ
ツプの実装には特に有効に適用できる。
The IC chip mounting structure of the present invention achieves low heat and resistance, and can be particularly effectively applied to mounting highly integrated, high power IC chips.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はICチツプ実装用基板の斜視図、第2
図は本発明の第1の実施例を示す斜視図、第3図
は第2図をA−A′部で切断した断面図、第4図
は本発明の第2の実施例を示す断面図、第5図は
本発明による基板の冷却のための実装斜視図、第
6図は第5図にボードとコネクターを追記した実
装の断面図である。 尚、図において、1……基板、2……開口、3
……空胴、4……接合剤、5……パターン、6…
…水、フレオン等の液体又は、液体金属等の熱伝
導性のよい流体、7……ICチツプ、8……接続
パツド、9……ワイヤ、10……筒、11……熱
交換器、12……矢印、13……ボード、14…
…コネクタをそれぞれ示す。
Figure 1 is a perspective view of the IC chip mounting board, Figure 2
The figure is a perspective view showing the first embodiment of the present invention, FIG. 3 is a sectional view taken along the line A-A' of FIG. 2, and FIG. 4 is a sectional view showing the second embodiment of the invention. , FIG. 5 is a perspective view of a mounting for cooling a board according to the present invention, and FIG. 6 is a sectional view of the mounting with the board and connector added to FIG. 5. In the figure, 1...substrate, 2...opening, 3
...Cavity, 4...Binding agent, 5...Pattern, 6...
...Liquid such as water or Freon, or fluid with good thermal conductivity such as liquid metal, 7...IC chip, 8...Connection pad, 9...Wire, 10...Cylinder, 11...Heat exchanger, 12 ...Arrow, 13...Board, 14...
...Indicates each connector.

Claims (1)

【特許請求の範囲】[Claims] 1 ICチツプ実装面においてICチツプ裏面の外
形寸法より小さな開口の貫通する空胴を有する実
装基板と、ICチツプを該実装基板に固定する接
合剤と、前記実装基板の前記空胴を通して前記
ICチツプ裏面に熱伝導性のよい流体を接触させ
る手段とを具備することを特徴とするICチツプ
の実装構造。
1. A mounting board having a cavity through which an opening smaller than the outer dimensions of the rear surface of the IC chip passes through the IC chip mounting surface; a bonding agent for fixing the IC chip to the mounting board;
An IC chip mounting structure characterized by comprising means for bringing a fluid with good thermal conductivity into contact with the back surface of the IC chip.
JP796879A 1979-01-25 1979-01-25 Structure for fitting ic chip Granted JPS5599752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP796879A JPS5599752A (en) 1979-01-25 1979-01-25 Structure for fitting ic chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP796879A JPS5599752A (en) 1979-01-25 1979-01-25 Structure for fitting ic chip

Publications (2)

Publication Number Publication Date
JPS5599752A JPS5599752A (en) 1980-07-30
JPS6118864B2 true JPS6118864B2 (en) 1986-05-14

Family

ID=11680254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP796879A Granted JPS5599752A (en) 1979-01-25 1979-01-25 Structure for fitting ic chip

Country Status (1)

Country Link
JP (1) JPS5599752A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63317400A (en) * 1987-06-19 1988-12-26 尾池工業株式会社 Transfer sheet

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55165659A (en) * 1979-06-11 1980-12-24 Fujitsu Ltd Semiconductor device
JP3756168B2 (en) * 2004-03-19 2006-03-15 株式会社ソニー・コンピュータエンタテインメント Circuit heat generation control method, apparatus and system
US7348665B2 (en) * 2004-08-13 2008-03-25 Intel Corporation Liquid metal thermal interface for an integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63317400A (en) * 1987-06-19 1988-12-26 尾池工業株式会社 Transfer sheet

Also Published As

Publication number Publication date
JPS5599752A (en) 1980-07-30

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