JPS6118874B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a high frequency diode with improved high frequency characteristics.

As one type of high-frequency diode, an N-type (or P ^- type) semiconductor layer with a low impurity concentration (hereinafter referred to as N There is a structure called a ^normal PIN diode, which includes a P-type (or N-type) semiconductor layer with a high impurity concentration (hereinafter referred to as a P ⁺ -type semiconductor layer). These high-frequency PIN diodes can be roughly divided into two types: planar type and mesa type. Among these, the former planar type PIN diode has a protective film such as an oxide film formed on the junction surface, so its characteristics are highly stable, but the junction surface has a curvature, so the withstand voltage is low, and the current There are problems in that it cannot be used with high power because it tends to concentrate in the periphery, and that the junction capacitance becomes larger than the set value or has large variations due to charges in the protective film or at the protective film-semiconductor interface. Therefore, conventionally planar type
Mesa-type PIN diodes, as shown in Figure 1, were often used to overcome the problems of PIN diodes. This mesa-type PIN diode consists of an N ^- type Si layer 12 and a P ⁺ type Si layer 1 on an N ⁺ type silicon (Si) substrate 11.
3 is provided, and mesa etching is performed from the P ⁺ type Si layer 13 side using the metal layer 14 as a mask until reaching the N ⁺ type Si substrate 11. By the way, the mesa-type PIN diode obtained in this way has high power durability, but since the junction surface including the M ⁺ -N ^- junction is exposed, the state of the mesa surface becomes unstable and leakage current increases. The breakdown voltage fluctuated, and the junction capacitance was often larger than the set value and was unstable. Therefore, there was a problem that production yield and reliability were low. For example, even when the leakage current is small and the breakdown voltage is stable, there are large variations in junction capacitance between elements, and furthermore, there is a large change over time when left at high temperatures. Such a phenomenon is
The lower the impurity concentration of the N ^- type Si layer, the lower the impurity concentration of the N ^- type Si layer.
The effect was more pronounced as the layer width was longer and the bonding area was larger.

The present invention has been made in view of the above-mentioned problems, and specifically provides a manufacturing method that improves the stability of the junction capacitance of a mesa-type PIN diode.

That is, the present invention can be applied to an N ⁺ (or P ⁺ ) type semiconductor substrate.
An N ^- (or P ^- ) type semiconductor layer and a P ⁺ (or N ^- ) type semiconductor layer are formed, and then mesa etching is performed from the P ⁺ type semiconductor layer side to the middle part of the N ^- type semiconductor layer, and this mesa etching is performed. This is a method for manufacturing high-frequency PIN diodes in which the surface is treated with a hydrogen gas system.

The present invention will be described below based on embodiments and with reference to the drawings. FIG. 2 is a cross-sectional view of a PIN diode for explaining a manufacturing method according to an embodiment of the present invention. This PIN diode is made by depositing an N - type Si layer 22 with a donor concentration of about 5×10 ¹³ /cm ² on an N ⁺ type Si substrate 21 with a thickness of about 300 μm and a donor concentration of about 5×10 ^{19 /} cm ² in a vapor phase, for example. A layer of about 8 μm is formed by growth. and this
For example, boron 13 is deposited to a thickness of 1.5 μm on the N ^- type Si layer 22.
Then, a P ⁺ -type semiconductor layer 23 having an acceptor concentration of about 1×10 ²⁰ /cm ² is formed. After this, this P ⁺ type Si
For example, Ti, Pt, and Au are sequentially deposited on the surface of the layer 23,
This vapor-deposited metal layer 24 is patterned, and P ⁺
A part of the type Si layer 23 and the N ^- type Si layer 22 is made of, for example, HF.
Mesa-etch with a mixture of -HNO ₃ -CH ₃ COOH. Thereafter, this mesa-etched surface was treated for 20 minutes in a hydrogen gas atmosphere at 350°C, and this wafer was divided (second wafer).
figure). Thereafter, the chip thus obtained is mounted on a ceramic package, gold wire is bonded to the metal layer 24, and sealing is performed to obtain a limiter diode. Note that the metal layer 24 provided on the P ⁺ type Si layer 23 comes into ohmic contact when processed in a hydrogen gas atmosphere, and the metal layer 24 forms a P ^{+ type} Si layer 23.
This serves as a good electrode for the type Si layer 23. Although not shown, a metal layer serving as an electrode is also provided on the N ⁺ Si substrate 21.

The PIN diode obtained in this way was applied to a mediband (high frequency) waveguide type limiter circuit, and the small signal insertion loss of this circuit at 9.375 GHz was investigated. It was 0.4 dB, and after 1000 hours high temperature (175
℃) There was no change even in the standing test. On the other hand, with the conventional PIN diode shown in Figure 1, the junction capacitance is larger than the set value, and as a result, the small signal insertion loss is not only as large as 0.8 dB, but also the high temperature (175°C) for 1000 hours. In an idle test
This further increased to 1.2dB. Small signal insertion loss 0.4dB
In order to achieve this, the junction area was reduced and the junction capacitance was set to be small, but this resulted in the drawback that the power resistance was approximately halved.

Next, in order to further understand the high frequency PIN diode of the present invention, a detailed explanation will be given below based on experimental data. Figures 3a and b show the conventional PIN diode (Figure 1), with a case where the mesa-etched surface was treated for 20 minutes in a hydrogen gas atmosphere at 350°C as shown in the above example, and b when no treatment was performed.
FIG. 3 is a diagram showing the distribution of junction capacitance at bias. As is clear from Figure 3, the junction capacitance of a at 0 bias was 1.4 pF to 2.1 pF without treatment, but with treatment
The junction capacitance has decreased from 0.7pF to 1.1pF, and the variation has also become smaller, and the design value has decreased from 0.8pF to 1.1pF.
It became almost equal to 0.9pF. When a similar process was performed in an argon gas atmosphere, there was almost no reduction in junction capacitance as described above. Furthermore, an oxide film is formed on the mesa-etched surface.
When a similar process was applied to a PIN diode, the reduction in junction capacitance was small. In addition, the PIN has lead glass formed on the mesa-etched surface.
When the same process was applied to the diode,
In this case as well, the reduction in junction capacitance was small. From these experimental facts, it can be seen that the reduction in junction capacitance due to treatment in a hydrogen gas atmosphere is more pronounced as the junction and the surface of the N ^- type semiconductor layer are exposed. One of the reasons for this is thought to be that when the surface of the junction and N ^- type semiconductor layer is exposed, the surface subjected to unstable mesa etching becomes inactive by being treated in a hydrogen gas atmosphere. On the other hand, if a protection film such as an oxide film or lead glass is formed on the mesa-etched surface, it is thought that this is because the charge at the interface between the protection film and silicon or in the protection film is not sufficiently reduced even when treated in a hydrogen gas atmosphere. .

Based on this experimental fact, when the mesa-etched surface of the PIN diode of the present invention (Fig. 2) was treated in a hydrogen atmosphere at 350°C for 20 minutes as shown in the above-mentioned example, Compared to FIG. 4b), as shown in FIG. 4a, the junction capacitance at 0 bias, which was from 1.3 pF to 2.0 pF, becomes from 0.6 pF to 0.9 pF, and as the junction capacitance decreases, the variation also becomes smaller. This variation is even smaller than that of conventional PIN diodes.

Furthermore, the conventional PIN diode shown in Figure 1,
Regarding the PIN diode of the present invention shown in FIG.
175 when the bonding area is processed in a hydrogen gas atmosphere at 350℃ and when no treatment is applied.
Figures 5a, b, c, and d show changes in junction capacity over time when left at high temperatures at .degree. In this Figure 5, a is a PIN diode of the present invention (Figure 2) without any treatment, b is a PIN diode of the present invention (Figure 2) treated with treatment, and c is a conventional PIN diode. (Fig. 1), which is not processed, and d is the conventional
This is processed using a PIN diode (Figure 1). As is clear from this figure, when the PIN diode of the present invention is processed under the above conditions, it has a diode of 175
It can be seen that the junction capacitance changes little and is stable even when left at high temperatures of °C.

As is clear from the above explanation, since the PIN diode of the present invention has little change in junction capacitance over time, it is possible to improve the most problematic point in diodes incorporated in special high frequency circuits.
For example, the present invention can improve small signal loss increase due to changes in junction capacitance over time when used in a limiter circuit, and changes in diode loss and phase shift when used in a PIN diode phase shifter. is clear.

In the above example, the heat treatment was performed at 350°C for 20 minutes in a hydrogen atmosphere, but the conditions are not limited to this, and the temperature and time of the heat treatment may be changed as long as the junction capacitance is reduced and stabilized. need not be limited to the examples. As a result of the experiment, the hydrogen gas may contain inert gases such as argon and nitrogen gas, and the heat treatment temperature and time range from 300℃ to 500℃ and 10℃, respectively.
Similar results were obtained between minutes and 30 minutes.

In addition, the diode of the above example has an N ^- layer width of 6.5
The width of the N layer was 1.5μm and 3μm.
As a result of comparing the thicknesses of 1.5 μm, 5 μm, 6.5 μm, and 10 μm, it was found that the effect of 5 μm or more was particularly significant compared to that of 1.5 μm and 3 μm.

Moreover, the diode of the above embodiment is P ⁺ −N ⁻ −N ⁺
In the case of a type diode, using a metal mask, mesa-etch at least up to the P ⁺ -N ^- interface junction, but do not mesa-etch up to the N ⁺ type Si layer.
Although mesa etching is carried out so that the N ⁺ type Si layer is not exposed within the mesa etched surface, mesa etching is also used for other types of diodes, and when performing mesa etching using an insulating film such as a resin or oxide film as a mask. can also be applied.

It is also possible to form a protective film of resin or the like on the surface of the PIN diode pellet produced by the method of the present invention.

As described above, mesa type PIN according to the present invention
According to the manufacturing method of the diode, compared to the conventional mesa type PIN diode, which has an unstable junction surface, the mesa type PIN diode reduces the influence of mesa surface instability on the junction capacitance, increases stability, and improves high frequency characteristics.
PIN diodes can be obtained in high yield.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view for explaining the conventional method of manufacturing a high-frequency PIN diode, FIG. 2 is a cross-sectional view for explaining the method of manufacturing a high-frequency PIN diode of the present invention, and FIG. This figure shows the capacitance change of a PIN diode, where a shows the junction capacitance distribution when the mesa-etched surface is treated in a hydrogen gas atmosphere at 350°C, and b shows the junction capacitance distribution when no treatment is applied. Yes, Figure 4 shows the 2nd
This is a diagram showing the distribution of junction capacitance of the PIN diode in the figure, where a shows the distribution of junction capacitance when the mesa-etched surface is treated in a hydrogen gas atmosphere at 350°C, and b shows the distribution of junction capacitance without treatment. Figure 5 shows the change in junction capacitance of a PIN diode with respect to time when it is left at a high temperature of 175°C. b shows the change in junction capacitance when no treatment is performed, b shows the change in junction capacitance when the same diode is treated, and c is when the mesa-etched surface with a conventional diode is not treated in a hydrogen gas atmosphere at 350°C. d shows the change in junction capacitance when the same diode is processed. 21: N ⁺ type Si substrate, 22: N ^- type Si layer, 23:
P ⁺ type Si layer, 24: metal layer.

Claims (1)

[Claims] 1. A step of forming a semiconductor layer of the same conductivity type as the substrate with a low impurity concentration on a semiconductor substrate of one conductivity type with a high impurity concentration, and forming a semiconductor layer of the opposite conductivity type with a high impurity concentration on the semiconductor layer. a step of forming a layer, a step of mesa-etching from the opposite conductivity type semiconductor layer side to the middle of the semiconductor layer with a low impurity concentration, and a step of etching the surface exposed in the step with hydrogen gas or an inert gas containing hydrogen. A method for manufacturing a high frequency diode, comprising the step of surface treatment. 2. A method for manufacturing a high frequency diode according to claim 1, characterized in that mesa etching is performed using a metal as a mask, and the metal layer is used as an electrode of a reverse conductivity type semiconductor layer with a high impurity concentration. 3 The thickness of the one conductivity type semiconductor layer with low impurity concentration is 5
A method for manufacturing a high frequency diode according to claim 1, characterized in that the diameter is .mu.m or more.