JPS6119107B2 - - Google Patents
Info
- Publication number
- JPS6119107B2 JPS6119107B2 JP54135495A JP13549579A JPS6119107B2 JP S6119107 B2 JPS6119107 B2 JP S6119107B2 JP 54135495 A JP54135495 A JP 54135495A JP 13549579 A JP13549579 A JP 13549579A JP S6119107 B2 JPS6119107 B2 JP S6119107B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- glass fibers
- solder
- thin film
- solder bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は半導体素子のボンデイング方法に関
し、更に詳述すると、ボンデイング基板上に半導
体素子の電極パツドを、ワイヤを介することなく
直接接続する、いわゆるダイレクトボンデイング
に関するる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for bonding a semiconductor device, and more specifically, to so-called direct bonding, in which electrode pads of a semiconductor device are directly connected to a bonding substrate without using wires.
従来のダイレクトボンデイングの製造方法は、
第１図及び第２図に示すように、LSIチツプ等の
半導体ウエハ１の電極パツド位置にCr−Cu−Au
の３層薄膜構造のトリメタル２を形成し、そのの
上にメツキ法によりAu又はCuのスタンドオフ３
を形成し、その周囲に半田バンプを作り、ボンデ
イング基板５上の薄膜配線６にボンデイングして
トリメタル２と薄膜配線を半田４で結合する方法
であつた。この方法によればメツキ法によりスタ
ンドオフ３を形成するため、多くの材料費と労務
費を必要とし製造に時間も要する欠点がある。 The conventional direct bonding manufacturing method is
As shown in Figures 1 and 2, Cr-Cu-Au is placed at the electrode pad position of a semiconductor wafer 1 such as an LSI chip.
A trimetal 2 with a three-layer thin film structure is formed, and a standoff 3 of Au or Cu is formed on it by a plating method.
, a solder bump is formed around the solder bump, and the trimetal 2 and the thin film wiring are bonded by solder 4 by bonding to the thin film wiring 6 on the bonding substrate 5. According to this method, since the standoffs 3 are formed by plating, there are disadvantages in that a large amount of material and labor costs are required, and manufacturing time is also required.
本発明の目的は上記欠点を解消するため、スタ
ンドオフを使用しないダイレクトボンデイングの
方法を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a direct bonding method that does not use standoffs in order to eliminate the above-mentioned drawbacks.
本発明は、ボンデイング基板上に所定直径のガ
ラス繊維を散布し、その上に、ウエハの電極パツ
ド上に半田浸し法で半田バンプを形成したものを
載せ、半田バンプとボンデイング基板上の薄膜配
線をボンデイングする。その後、ガラス繊維を除
去してもよい。 In the present invention, glass fibers of a predetermined diameter are scattered on a bonding substrate, and solder bumps formed on the electrode pads of a wafer by a solder dipping method are placed on top of the glass fibers, and the solder bumps and thin film wiring on the bonding substrate are connected. Bonding. The glass fibers may then be removed.
本発明のガラス繊維の直径は９μ乃至12μの範
囲が適当である。９μ以下のものではボンデイン
グの際、溶けた半田がLSIチツプの側部に溢れ出
て好ましくない。また15μ以上のものでは確実な
ボンデイングが行われず好ましくない。 The diameter of the glass fiber of the present invention is suitably in the range of 9μ to 12μ. If the thickness is less than 9μ, melted solder will overflow onto the sides of the LSI chip during bonding, which is undesirable. Further, if the thickness is 15μ or more, reliable bonding cannot be performed, which is not preferable.
次に本発明の実施例を図面に基づいて説明す
る。 Next, embodiments of the present invention will be described based on the drawings.
第３図にボンデイング終了後の状態を示し、第
４図にその部分拡大図を示す。 FIG. 3 shows the state after bonding is completed, and FIG. 4 shows a partially enlarged view thereof.
半導体ウエハ１の電極パツド位置に蒸着法によ
りCr−Cu−Auの３層薄膜構造の正方形のトリメ
タル２を形成した。これ迄は従来方法と同じであ
る。次に、これを半田槽に浸してトリメタル２上
に半田バンプを形成した。実施例において、トリ
メタル２の寸法100μｍ×100μｍのとき半田バン
プの高さは20μｍ程度であつた。 A square trimetal 2 having a three-layer thin film structure of Cr--Cu--Au was formed at the electrode pad position of the semiconductor wafer 1 by vapor deposition. The process up to this point is the same as the conventional method. Next, this was immersed in a solder bath to form solder bumps on the trimetal 2. In the example, when the dimensions of the trimetal 2 were 100 μm×100 μm, the height of the solder bump was about 20 μm.
一方、ボンデイング基板５上に予め所定パター
ンの薄膜配線６を施したものの上に、ガラス繊維
７…７を散布した。このガラス繊維の散布法は、
多数のガラス繊維を空間に舞い上らせボンデイン
グ基板５上に落下させる方法を用いた。半導体ウ
エハ１の寸法が４mm×５mmのとき、ウエハを載せ
る部分に数10本のガラス繊維が並置されるのが適
当である。ガラス繊維の並置状態は、複数本が重
なり合わないことが好ましい。 On the other hand, glass fibers 7 . . . 7 were sprinkled on a bonding substrate 5 on which a predetermined pattern of thin film wiring 6 had been formed in advance. This method of dispersing glass fiber is
A method was used in which a large number of glass fibers were blown up into space and dropped onto the bonding substrate 5. When the dimensions of the semiconductor wafer 1 are 4 mm x 5 mm, it is appropriate that several dozen glass fibers are arranged side by side in the area on which the wafer is placed. When the glass fibers are arranged side by side, it is preferable that a plurality of glass fibers do not overlap each other.
また、ボンデイングすべきき位置の上に散布さ
れたガラス繊維は除去しなくてもよい。なぜな
ら、LSIチツプのパツド寸法は約100μｍ角であ
るのに対し、ガラス繊維の直径は数μｍであり、
ガラス繊維がその間に狭まれたとしても電気的導
通が妨げられず、また、一般に溶解した半田はガ
ラスに対してぬれ性がなく、ボンデイングの際に
半田によつてその付近のガラス繊維がはじかれて
しまうからである。 Furthermore, it is not necessary to remove the glass fibers spread over the positions to be bonded. This is because the pad size of an LSI chip is approximately 100 μm square, whereas the diameter of glass fiber is several μm.
Even if glass fibers are squeezed between them, electrical conduction is not hindered, and melted solder generally does not wet the glass, so glass fibers in the vicinity are repelled by the solder during bonding. This is because
このようにして、ガラス繊維７…７を敷いた上
に半田バンプを設けたウエハ１を載せ、従来と同
様の方法でボンデイングを行ない、トリメタル２
と薄膜配線６を半田８で結合した。ボンデイング
終了後ガラス繊維７…７を除去した。 In this way, the wafer 1 provided with solder bumps is placed on the glass fibers 7...7, bonding is performed in the same manner as before, and the trimetal 2
and the thin film wiring 6 were bonded together with solder 8. After the bonding was completed, the glass fibers 7...7 were removed.
本発明によば、ガラス繊維が従来方法のスタン
ドオフの役目を果たすので、スタンドオフが不要
となり、その結果、製造コストが大幅に低減し、
製造に要する時間が短縮された。 According to the present invention, since the glass fibers serve as the standoffs of the conventional method, no standoffs are required, resulting in a significant reduction in manufacturing costs.
The time required for manufacturing has been reduced.
第１図及び第２図は従来例を示す図、第３図は
本発明によるボンデイング作業直後の状態を示す
側面図、第４図は第３図の部分拡大図である。
１……LSIチツプ、５……基板、７……ガラス
繊維、８……半田。
1 and 2 are views showing a conventional example, FIG. 3 is a side view showing a state immediately after bonding work according to the present invention, and FIG. 4 is a partially enlarged view of FIG. 3. 1...LSI chip, 5...board, 7...glass fiber, 8...solder.
Claims (1)
電極パツドを直接接続するダイレクトボンデイン
グの製造方法において、上記ボンデイング基板上
に所定直径のガラス繊維を散布し、その上に、上
記電極パツドに半田バンプを形成したものを載
せ、上記ボンデイング基板上の導電箔と上記半田
バンプとをボンデイングすることを特徴とする半
導体素子のボンデイング方法。1. In a direct bonding manufacturing method in which electrode pads of a semiconductor element are directly connected to conductive foil on a bonding substrate, glass fibers of a predetermined diameter are scattered on the bonding substrate, and solder bumps are formed on the electrode pads thereon. 1. A method for bonding a semiconductor device, comprising placing a conductive foil on the bonding substrate and bonding the solder bumps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13549579A JPS5660025A (en) | 1979-10-19 | 1979-10-19 | Bonding method for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13549579A JPS5660025A (en) | 1979-10-19 | 1979-10-19 | Bonding method for semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5660025A JPS5660025A (en) | 1981-05-23 |
| JPS6119107B2 true JPS6119107B2 (en) | 1986-05-15 |
Family
ID=15153066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13549579A Granted JPS5660025A (en) | 1979-10-19 | 1979-10-19 | Bonding method for semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5660025A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6021534A (en) * | 1983-07-15 | 1985-02-02 | Seiko Epson Corp | Circuit mounting structure |
| JP4104889B2 (en) * | 2002-03-29 | 2008-06-18 | 株式会社東芝 | Optical semiconductor device |
| US7232740B1 (en) | 2005-05-16 | 2007-06-19 | The United States Of America As Represented By The National Security Agency | Method for bumping a thin wafer |
-
1979
- 1979-10-19 JP JP13549579A patent/JPS5660025A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5660025A (en) | 1981-05-23 |
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