JPS6120024B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing control system, more specifically, a timing control device for a device that processes vector data (vector processor) that transfers data between a device that processes scalar instructions (scalar unit), and a device that processes vector data (vector processor). Regarding.

In vector instructions that process vector data in a vector processor that transfers data to and from a scalar unit, multiple result data are derived from multiple source data and transferred to the general-purpose registers of the scalar unit. I have something to write. For example, Vector Find Max finds the maximum value among the elements of a vector operand and the index of that element. In such an instruction, multiple pieces of data obtained by the arithmetic unit of the vector processor must be transferred to the scalar unit. Since the vector processor and the scalar unit basically operate in synchronization with the clocks that are clock-stopped independently, they are not related to each other and do not know when each other will stop operating.
Therefore, when transferring data from the vector processor to the scalar unit, multiple pieces of data for one instruction obtained by the arithmetic unit are stored in a buffer, ready to be transferred at any time, and then the data is transferred in synchronization with the scalar unit's clock. Let's do it.

The circuit of this part is shown in FIG. In FIG. 1, 1a to 1e (TT0 to TT4) indicate transmit timings, and buffers 2a to 2c (WB0 to TT4) indicate transmit timings.
~WB2) is synchronized with the vector processor clock (CLK V) to specify the writing timing. 3a, 3b, 3c, 3d, and 3e are write timings that specify the timing for transferring data to the scalar unit, and are synchronized with the clock (CLOCK S) of the scalar unit. 4 is a change timing, which is the transition timing from transmit timing to write timing, and is a free clock (CLK F).
It works. 5a, 5b, 5c (RR0~RR2)
is a result data register which writes data obtained by the arithmetic unit 6 to write buffers 2a to 2c.
to be transmitted. Note that the result data register 5b,
5c is essentially unnecessary, but is provided to share the circuit with other control systems, and the result data register is synchronized with the vector processor clock (CLK V). In addition, light buffer 2
a to 2c (WB0 to WB1) store up to three pieces of data obtained by the arithmetic units. This is necessary for the number of data that can be obtained with one instruction, and here the maximum is 3.
There are two. This is synchronized to the vector processor clock (CLK V). 7 (WRQ)
indicates a write request and specifies that data be transferred to the scalar unit in synchronization with the scalar unit's clock (CLOKS). 8 (WR) is a register for inputting data to be transferred to the scalar unit in synchronization with the scalar unit's clock (CLOCK S).

FIG. 2 shows the timing of the operation shown in FIG. The data transfer timing in FIG. 2 can be expressed by a parallelogram as shown in FIG. 3 by simplifying the chart. For example, at the timing of TT3, the clock stop signal (CLOCK
Consider the case where STOP V) is sent from the arithmetic control section. If this signal continues for 2τ, the operation will be as shown in the time chart of FIG. In other words, since the vector processor has stopped even though the calculation has been completed, the data transfer to the scalar unit is delayed by that period, that is, the portion surrounded by the dotted line.

This delay in operation occurs because the timing control circuit uses the vector processor's clock (CLK V).
This is due to the fact that all the parts controlled by it are held by the stop because it is synchronized with the stop.

SUMMARY OF THE INVENTION An object of the present invention is to provide a timing control method that enables data transfer even if a vector processor stops its clock as long as the scalar unit does not stop its clock, thereby reducing delays in data transfer due to clock stops. It's about doing.

According to the present invention, in a first device that transfers data to a second device whose operation is stopped by an independent clock stop signal, a timing control circuit in the first device controls the timing of this transfer. a part that is synchronized with each clock stop signal generated by each clock stop prediction signal of the first and second devices, and a part that constantly transitions the timing without stopping the clock from a specific timing thereof. By having an interface part between the first device and the second device, the interface part between the first device and the second device can be operated without stopping the clock, and data transfer is performed in a pipeline manner, thereby reducing delays in data transfer caused by stopping the clock. A timing control method featuring the following is proposed.

Examples of the system according to the present invention will be described in detail below.

Normally, with an arithmetic unit, even if a clock stop occurs after all result data registers have been output, data transfer is logically possible as long as the scalar unit does not stop the clock.

To achieve this, the transmit timing is limited to instructing the timing at which data is output from the arithmetic unit, and subsequent operations are performed using a timing control circuit that changes state using a free clock (CLK F), that is, a clock that does not stop the clock. It can be controlled by

FIG. 5 shows an example thereof. In FIG. 5, transmit timings 11a to 11c (TT0
₀ to TT2 ₀ ) counts until all data is output from the arithmetic unit 10 in synchronization with the clock (CLK V). Transmit timing 13
a, 13b, 13c (TT0 ₁ , TT1 ₁ , TT2
₁ ) The result data 0 to 2 are stored in the result data register 15 in synchronization with the clock CLK F.
b (RR1) and 15c (RR2). Transmit timing 14a, 14b, 14c (TT0 ₁ to TT2 ₂ )
write result data 0 to 2 to buffers 12a and 12, respectively, in synchronization with the clock (CLK F).
Controls the timing of writing to b, 12c (WB0 to WB2). Furthermore, result data register 15
a (RR0) is synchronized with the clock CLK V and the result data registers 15b, 15c (RR1, RR
2) is operated by the clock CLKF, and the write buffers 12a to 12c (WB0 to WB2) are operated by the clock CLKF.
Operates with CLK F. The parts other than the above are the same as those in FIG.

The timing of the operation of the circuit of FIG. 5 is shown in FIG. As shown in the figure, result data register 1
5b (RR1), 15c (RR2), write buffer (WB0 to WB2) are clock stops CLOCK
Since the data is not stopped by STOP V, the data first enters the data register 15a (RR0) and is then continuously transmitted to the write buffers (WB0 to WB2) in a pipeline manner. Therefore, even if the clock pulse CLOCK V is stopped after transmit timing _TT20 , the operation will not be delayed. Clock stop as shown in Figure 4
Figure 7 shows a time chart when CLOCK STOP V is sent.

Conventionally, transmit timing TT2, TT
3. When the clock pulse stopped at TT4, the operation was delayed by that amount, but by making the data flow a free-flowing pipeline system as in the present invention, the clock pulse stops after the last data is output from the arithmetic unit. Even if a stop occurs, the operation will not be delayed.

Furthermore, according to the present invention, the transmit timing (TT) and the write timing (WT) can exist at the same time due to pipelining (WT0 and TT2 ₂ in FIG. 6), so the timing of data transfer is always more accurate than in the conventional example. There is also the advantage that it is faster by 1τ (Fig. 7).

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional timing control system in a data transfer control section, Figure 2 is a timing chart of data transfer using the system shown in Figure 1, and Figures 3 and 4 are diagrams of the conventional system shown in Figure 1. A timing chart for explaining timing control of data transfer, FIG. 5 is a block diagram of one embodiment of the timing control method according to the present invention, and FIGS.
This figure is a timing chart for explaining the operation of the system shown in FIG. In the figure, 11a, 11b, 11c (TT0
₀ , TT1 ₀ , TT2 ₀ ) is the first transmit timing, 13a, 13b, 13c (TT0
₁ , TT1 ₁ , TT2 ₁ ) is the second transmit timing, 14a, 14b, 14c (TT0
₂ , TT1 ₂ , TT2 ₃ ) is the third transmit timing.

Claims (1)

[Claims] 1. In an information processing device consisting of a first and second device whose operation can be stopped by independent clock stop signals, the first device that transfers data to the second device determines the timing of this transfer. A timing control circuit in the first device to be controlled includes a portion that synchronizes with each clock stop signal of the first and second devices, and a portion that constantly transitions the timing from a specific timing of the clock stop signals without stopping the clock. By having a section that moves between the first device and the second device, the interface section between the first device and the second device can be operated without stopping the clock, and data transfer is performed in a pipeline manner, thereby reducing delays in data transfer caused by stopping the clock. This timing control method is characterized by: