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JPS6120146B2 - - Google Patents
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JPS6120146B2 - - Google Patents

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Publication number
JPS6120146B2
JPS6120146B2 JP52146444A JP14644477A JPS6120146B2 JP S6120146 B2 JPS6120146 B2 JP S6120146B2 JP 52146444 A JP52146444 A JP 52146444A JP 14644477 A JP14644477 A JP 14644477A JP S6120146 B2 JPS6120146 B2 JP S6120146B2
Authority
JP
Japan
Prior art keywords
heat dissipation
semiconductor element
semiconductor
solder
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52146444A
Other languages
Japanese (ja)
Other versions
JPS5478982A (en
Inventor
Takehisa Sugawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14644477A priority Critical patent/JPS5478982A/en
Publication of JPS5478982A publication Critical patent/JPS5478982A/en
Publication of JPS6120146B2 publication Critical patent/JPS6120146B2/ja
Granted legal-status Critical Current

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 本発明は、フエイス・ダウン・ボンデイングさ
れる素子を有する半導体装置及びそれを製造する
場合に適用して好適な方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having elements subjected to face-down bonding and a method suitable for manufacturing the same.

一般にビーム・リード素子、或はフリツプ・チ
ツプ素子等は、基板に実装する場合アツプ・サイ
ド・ダウンにしてボンデイングする所謂フエイ
ス・ダウン・ボンデイング方式が採用されてい
る。その方式を採ると、基板とチツプとの間には
空隙を生じる為、チツプで発生する熱は基板を介
して効率良く放散できないことになる。そこで、
従来チツプで発生する熱をその背面から放散させ
ることが行なわれている。
Generally, when a beam lead element, a flip chip element, etc. is mounted on a substrate, a so-called face-down bonding method is adopted in which the element is bonded from the top side down. If this method is adopted, a gap is created between the substrate and the chip, so that the heat generated in the chip cannot be efficiently dissipated through the substrate. Therefore,
Conventionally, heat generated by a chip is dissipated from the back surface of the chip.

例えば、第1図に見られる従来例は、基板1に
半導体チツプ2をフエイス・ダウン・ボンデイン
グし、セラミツク製のヒート・シンク兼キヤツプ
3を例えば金・シリコン等の低融点ソルダ4を介
して半導体チツプ2に固着するとともに同じく適
当な低融点ソルダ5を介して基板1に固着したも
のである。また、例えば第2図に見られるよう
に、ヒート・シンク兼キヤツプ3として、セラミ
ツク製のものでなく、金属製のものを用いること
も行なわれている。
For example, in the conventional example shown in FIG. 1, a semiconductor chip 2 is face-down bonded to a substrate 1, and a heat sink/cap 3 made of ceramic is bonded to the semiconductor chip via a low melting point solder 4 such as gold or silicon. It is fixed to the chip 2 and also to the substrate 1 via a suitable low melting point solder 5. Furthermore, as shown in FIG. 2, for example, the heat sink/cap 3 is made of metal instead of ceramic.

ところで、前記従来例では、いずれも半導体チ
ツプ2とヒート・シンク兼キヤツプ3とは固着さ
れている。この固着は、半導体チツプ2がシリコ
ンであれば金・シリコンのソルダ4と共晶するの
で極めて強固である。
Incidentally, in all of the conventional examples described above, the semiconductor chip 2 and the heat sink/cap 3 are fixedly attached. This fixation is extremely strong if the semiconductor chip 2 is silicon, since it is eutectic with the gold-silicon solder 4.

そこで若し、実装後に半導体チツプ2が不良品
であることが判明した場合、その交換は、ヒー
ト・シンク兼キヤツプ3を取外さなければならな
いから、甚だ困難な作業となる。従つて、通常で
あれば廃棄処分にしたいところであるが、近年の
半導体チツプはLSI化されていて1チツプといえ
どもかなり高価であるし、特にマルチ・チツプと
呼ばれているもの、即ち、一つの基板に複数個の
半導体チツプを搭載した装置では、1個の半導体
チツプが不良である場合に全部を廃棄してしまう
のは損失が大きすぎる。そして、高速のLSIでは
消費電力も大きく、機能も複雑であつて、発熱等
の点から実際に配線基板に実装したのに近い状態
で電気的試験を行なわなければならず、その場合
上記した問題は一層深刻である。尚、前記ヒー
ト・シンク兼キヤツプ3を接着剤で固着すること
も考えられているが、その場合も同様である。
Therefore, if the semiconductor chip 2 is found to be defective after mounting, replacing it will be an extremely difficult task since the heat sink/cap 3 must be removed. Normally, we would want to dispose of them as waste, but in recent years semiconductor chips have been made into LSIs, and even a single chip is quite expensive. In a device in which a plurality of semiconductor chips are mounted on one substrate, if one semiconductor chip is defective, it would be too much loss to discard all of them. Furthermore, high-speed LSIs consume large amounts of power and have complex functions, so electrical tests must be conducted in conditions similar to those actually mounted on a wiring board due to heat generation, etc. In this case, the problems described above may occur. is even more serious. It has been considered that the heat sink/cap 3 may be fixed with an adhesive, but the same applies in that case.

本発明は、フエイス・ダウン・ボンデイングし
た半導体チツプの背面に放熱手段を施してあるに
も拘わらず、その半導体チツプの取外しを容易に
して、任意に交換できるようにするものであり、
以下これを詳細に記述する。
The present invention enables face-down bonded semiconductor chips to be easily removed and replaced at will, even though heat dissipation means are provided on the back surface of the semiconductor chips.
This will be described in detail below.

第3図乃至第5図は本発明一実施例の工程図で
あり、次にこれ等の図を参照しつつ説明する。
FIGS. 3 to 5 are process diagrams of one embodiment of the present invention, and the following will be described with reference to these figures.

第3図参照 (1) 半導体素子搭載基板11に半導体素子12を
フエイス・ダウン・ボンデイングする。
Refer to FIG. 3 (1) The semiconductor element 12 is face-down bonded to the semiconductor element mounting substrate 11.

(2) スペーサ13、例えば銅(Cu)製の放熱基
板14、螺子15を用意する。
(2) Prepare a spacer 13, a heat sink 14 made of copper (Cu), and a screw 15, for example.

スペーサ13は放熱基板14と基板11との
間を適当な間隔に維持する役目を果す。
The spacer 13 serves to maintain an appropriate distance between the heat dissipation substrate 14 and the substrate 11.

放熱基板14には、半導体素子12を臨み得
る通孔14A及び螺子を挿通する通孔14Bが
形成されている。また、半導体素子12と対向
する面に於ける通孔14Aの近傍には例えば半
田鍍金16が施してある。この半田鍍金16は
ソルダと結合し易ければ他のものでも良く、例
えば錫(Sn)鍍金、予備半田等でも良い。ま
た部分的でなく放熱基板14の全体に施しても
良い。
A through hole 14A through which the semiconductor element 12 can be viewed and a through hole 14B into which a screw is inserted are formed in the heat dissipation substrate 14. Further, in the vicinity of the through hole 14A on the surface facing the semiconductor element 12, for example, solder plating 16 is applied. This solder plating 16 may be of any other material as long as it is easy to bond with solder, such as tin (Sn) plating, preliminary solder, or the like. Further, it may be applied to the entire heat dissipation board 14 instead of partially.

螺子15は放熱基板14及びスペーサ13を
貫通して先端が基板11に螺合されるものであ
る。
The screw 15 passes through the heat dissipation board 14 and the spacer 13 and its tip is screwed into the board 11.

第4図参照 (3) 放熱基板14を基板11に対し螺子15で固
着する。放熱基板14と半導体素子12との間
には若干の空隙gが介在する。
See FIG. 4 (3) Fix the heat dissipation board 14 to the board 11 with screws 15. A slight gap g exists between the heat dissipation substrate 14 and the semiconductor element 12.

(4) インジウム・錫(In・Sn)等の低温半田、
即ちソルダ17を用意する。図示のソルダ17
は円柱状をなしているが、要は通孔14Aに挿
入し得る形状をなしていれば良く、図示のもの
に限定されない。また、その材質としては、半
導体素子12に対して濡れ性の悪いものである
ことが必要であり、しかも、低温で溶融するも
のでなければならない。インジウム・錫はシリ
コンに対する濡れ性が悪く、そして温度117
〔℃〕で溶融する。
(4) Low-temperature solder such as indium/tin (In/Sn),
That is, the solder 17 is prepared. Solder 17 shown
Although it has a cylindrical shape, the shape is not limited to that shown in the drawings, as long as it can be inserted into the through hole 14A. Further, the material must have poor wettability with respect to the semiconductor element 12, and must also melt at a low temperature. Indium and tin have poor wettability to silicon, and the temperature is 117°C.
Melts at [℃].

(5) ソルダ17は通孔14Aに挿入する。(5) Insert the solder 17 into the through hole 14A.

第5図参照 (6) 全体を加熱炉中に入れ、ソルダ17が溶融す
る程度に加熱する。ソルダ17は溶融して図示
の形状になる。
See FIG. 5 (6) Place the whole in a heating furnace and heat to such an extent that the solder 17 melts. The solder 17 melts into the shape shown.

ソルダ17は放熱基板14の少なくとも半田
鍍金16が施された部分に融着しているが、半
導体素子12に対しては当接しているだけであ
る。
The solder 17 is fused to at least the portion of the heat dissipation board 14 on which the solder plating 16 is applied, but it is only in contact with the semiconductor element 12.

前記説明で判るように、ソルダ17は半導体素
子12とは融着していないので、螺子15を除去
することに依り放熱基板14は基板11から容易
に分離できるものであり、従つて半導体素子12
に不良品が在る場合には、それを交換することは
容易である。そして、不良品の交換後は、再び前
記と同様の工程を経て修復することが可能であ
る。
As can be seen from the above description, since the solder 17 is not fused to the semiconductor element 12, the heat dissipating substrate 14 can be easily separated from the substrate 11 by removing the screws 15, and therefore the semiconductor element 12
If there is a defective product, it is easy to replace it. After replacing the defective product, it is possible to repair it again through the same steps as above.

第6図は他の実施例の説明図であり、第3図乃
至第5図について説明した実施例と同部分は同記
号で指示してある。
FIG. 6 is an explanatory diagram of another embodiment, and the same parts as in the embodiment described with reference to FIGS. 3 to 5 are indicated by the same symbols.

本実施例が前記実施例と相違する点は、放熱基
板14に冷却用フイン18を附設してある。この
場合、フイン18の冷却能力が充分であれば、放
熱基板14はフイン・ホルダとしての役目を果せ
ば良いから、放熱基板としては熱伝導率の低い材
質のものであつても使用することができる。
This embodiment differs from the previous embodiment in that cooling fins 18 are attached to the heat dissipation board 14. In this case, as long as the cooling capacity of the fins 18 is sufficient, the heat dissipation board 14 can serve as a fin holder, so even a material with low thermal conductivity may be used as the heat dissipation board. I can do it.

第6図に於いて記号aを附した冷却用フイン1
8は、それを放熱基板14に取付けた状態を説明
するものであり、記号bを附したものは、ソルダ
17を供給した状態を説明するものであり、記号
cを附したものは、加熱後の状態を説明するもの
であり基本的には前記実施例と変りない。尚、本
実施例も前記実施例も、スペーサ13の高さを適
当に選択することに依り空隙gを調節する。
Cooling fin 1 marked with symbol a in Figure 6
8 explains the state in which it is attached to the heat dissipation board 14, the one with symbol b explains the state in which solder 17 is supplied, and the one with symbol c explains the state after heating. This example is basically the same as the previous example. Incidentally, in both this embodiment and the previous embodiment, the gap g is adjusted by appropriately selecting the height of the spacer 13.

本発明による他の実施例を第7図に示す。第7
図では上記実施例における第6図cに対応する状
態での実装構造を示しており、唯上記実施例とは
半導体チツプ12の背面にモリブデン(Mo)の
如き熱伝導性の良好な材料の薄板19がソルダま
たは接着剤20で固着されて成る半導体素子が用
いられている点においてのみ異なつている。この
場合は、モリブデン(Mo)板とソルダ17とが
簡単に剥離され得るようにして接触しているので
ある。
Another embodiment according to the invention is shown in FIG. 7th
The figure shows the mounting structure in a state corresponding to FIG. The only difference is that a semiconductor element in which 19 is fixed with solder or adhesive 20 is used. In this case, the molybdenum (Mo) plate and the solder 17 are in contact with each other in such a way that they can be easily peeled off.

以上の説明で判るように、本発明に依れば、例
えば、半導体素子搭載基板の反り、放熱基板の反
り、半導体チツプの厚さ不均一或は凹凸、放熱基
板やフインと半導体素子との間の空隙の不均一が
在つても、半導体素子背面と放熱基板或はフイン
との間はソルダに依り全て密着されるので、その
放熱効果は良好である。そして、ソルダと半導体
素子とは当接しているだけであるから、基板と放
熱基板は容易に分離することができるので、例え
ばマルチ・チツプ方式の装置を完成した後で不良
チツプが発見された場合、それを交換することは
容易であるから、経済的損失は低減される。
As can be seen from the above description, according to the present invention, for example, warping of a semiconductor element mounting board, warping of a heat dissipation board, non-uniform thickness or unevenness of a semiconductor chip, and gaps between a heat dissipation board or fins and a semiconductor element can be prevented. Even if there is non-uniformity in the air gaps, the back surface of the semiconductor element and the heat dissipation substrate or fins are all tightly bonded by the solder, so the heat dissipation effect is good. Since the solder and the semiconductor element are only in contact with each other, the board and the heat dissipation board can be easily separated, so for example, if a defective chip is discovered after completing a multi-chip device. , it is easy to replace it, so the economic loss is reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は従来例の説明図、第3図乃
至第5図は本発明一実施例の説明図、第6図は他
の実施例の説明図、第7図はさらに他の実施例の
説明図である。 図に於いて、11は基板、12は半導体素子、
13はスペーサ、14は放熱基板、15は螺子、
16は半田鍍金、17はソルダ、18はフイン、
14A,14Bは通孔、gは空隙である。
1 and 2 are explanatory diagrams of a conventional example, FIGS. 3 to 5 are explanatory diagrams of one embodiment of the present invention, FIG. 6 is an explanatory diagram of another embodiment, and FIG. 7 is an explanatory diagram of another embodiment. It is an explanatory diagram of an example. In the figure, 11 is a substrate, 12 is a semiconductor element,
13 is a spacer, 14 is a heat dissipation board, 15 is a screw,
16 is solder plating, 17 is solder, 18 is fin,
14A and 14B are through holes, and g is a void.

Claims (1)

【特許請求の範囲】 1 複数の半導体素子を搭載した半導体素子搭載
基板と、該半導体素子搭載基板に対向して螺子止
めに依り着脱自在に取り付けられている放熱用基
板と、該放熱用基板が前記半導体素子搭載基板に
取り付けられた状態で該放熱用基板側の通孔から
装着され且つ溶融及び固化されて前記各半導体素
子と該放熱用基板との間を密実に埋めると共に該
放熱用基板側に固着されているソルダとを備え、
該ソルダは前記各半導体素子の背面には融着され
ることなく且つ各半導体素子から前記放熱用基板
まで空隙がない状態で密実な放熱経路を形成する
ものであることを特徴とする半導体装置。 2 半導体チツプ背面に熱伝導性の良好な材料か
らなる薄板が固着されて成る複数の半導体素子を
搭載した半導体素子搭載基板と、該半導体素子搭
載基板に対向して螺子止めに依り着脱自在に取り
付けられている放熱用基板と、該放熱用基板が前
記半導体素子搭載基板に取り付けられた状態で該
放熱用基板側の通孔から装着され且つ溶融及び固
化され前記各半導体素子に固着された薄板と該放
熱用基板との間を密実に埋めると共に該放熱用基
板側に固着されているソルダとを備え、該ソルダ
は前記各半導体素子に固着された薄板には融着さ
れることなく且つ各半導体素子に固着された薄板
から前記放熱用基板まで空隙がない状態で密実な
放熱経路を形成するものであることを特徴とする
半導体装置。 3 複数の半導体素子をフエイス・ダウンにして
半導体素子搭載基板に取り付け、該半導体素子搭
載基板に前記各半導体素子の背面を臨む通孔が形
成された放熱用基板を着脱自在に螺子止めに依り
固着し、その後、前記各半導体素子の背面には融
着しないソルダを前記通孔から供給し且つ溶融及
び固化を行つて該ソルダを前記半導体素子に密接
させると共に前記放熱用基板に固着する工程が含
まれてなることを特徴とする半導体装置の製造方
法。
[Scope of Claims] 1. A semiconductor element mounting board on which a plurality of semiconductor elements are mounted, a heat dissipation board that is removably attached to the semiconductor element mounting board by means of screws, and the heat dissipation board is It is attached to the semiconductor element mounting board through the through hole on the heat dissipation board side, and is melted and solidified to tightly fill the space between each of the semiconductor elements and the heat dissipation board, and also on the heat dissipation board side. and a solder fixed to the
A semiconductor device characterized in that the solder is not fused to the back surface of each of the semiconductor elements and forms a tight heat dissipation path from each semiconductor element to the heat dissipation substrate without any gaps. . 2. A semiconductor element mounting board on which a plurality of semiconductor elements are mounted, which is made up of a thin plate made of a material with good thermal conductivity fixed to the back of a semiconductor chip, and a semiconductor element mounting board that is removably attached by screws to face the semiconductor element mounting board. a thin plate that is attached to the semiconductor element mounting substrate through a through hole on the heat radiation substrate side, and is melted and solidified to be fixed to each of the semiconductor elements; and a solder that tightly fills the space between the heat dissipating substrate and the heat dissipating substrate, and the solder is not fused to the thin plate fixed to each of the semiconductor elements, and is not fused to the thin plate fixed to each of the semiconductor elements. 1. A semiconductor device, characterized in that a solid heat dissipation path is formed from a thin plate fixed to an element to the heat dissipation substrate without any gaps. 3. A plurality of semiconductor elements are mounted face down on a semiconductor element mounting board, and a heat dissipation board in which a through hole facing the back side of each semiconductor element is formed is removably fixed to the semiconductor element mounting board by screwing. Then, the method includes a step of supplying a non-fused solder to the back surface of each of the semiconductor elements through the through hole, and melting and solidifying the solder to bring the solder into close contact with the semiconductor element and to fix it to the heat dissipation substrate. A method of manufacturing a semiconductor device, characterized in that:
JP14644477A 1977-12-06 1977-12-06 Semiconductor device and its manufacture Granted JPS5478982A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14644477A JPS5478982A (en) 1977-12-06 1977-12-06 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14644477A JPS5478982A (en) 1977-12-06 1977-12-06 Semiconductor device and its manufacture

Publications (2)

Publication Number Publication Date
JPS5478982A JPS5478982A (en) 1979-06-23
JPS6120146B2 true JPS6120146B2 (en) 1986-05-21

Family

ID=15407777

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14644477A Granted JPS5478982A (en) 1977-12-06 1977-12-06 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS5478982A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63174660U (en) * 1987-03-31 1988-11-14

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1285396B1 (en) * 1996-06-04 1998-06-03 Magneti Marelli Spa DISSIPATOR DEVICE FOR INTEGRATED CIRCUITS.
JP2000031360A (en) 1998-07-08 2000-01-28 Hitachi Ltd Multi-chip module
JP4673949B2 (en) * 1999-11-12 2011-04-20 富士通株式会社 Semiconductor unit and manufacturing method thereof
JP4796653B2 (en) * 2010-04-07 2011-10-19 富士通株式会社 Cooling system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63174660U (en) * 1987-03-31 1988-11-14

Also Published As

Publication number Publication date
JPS5478982A (en) 1979-06-23

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