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JPS6120178B2 - - Google Patents
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JPS6120178B2 - - Google Patents

Info

Publication number
JPS6120178B2
JPS6120178B2 JP55177093A JP17709380A JPS6120178B2 JP S6120178 B2 JPS6120178 B2 JP S6120178B2 JP 55177093 A JP55177093 A JP 55177093A JP 17709380 A JP17709380 A JP 17709380A JP S6120178 B2 JPS6120178 B2 JP S6120178B2
Authority
JP
Japan
Prior art keywords
agc
bias control
apd
circuit
temperature compensation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55177093A
Other languages
Japanese (ja)
Other versions
JPS57101443A (en
Inventor
Koichi Oota
Susumu Hanaoka
Akihiko Ichikawa
Toshuki Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55177093A priority Critical patent/JPS57101443A/en
Publication of JPS57101443A publication Critical patent/JPS57101443A/en
Publication of JPS6120178B2 publication Critical patent/JPS6120178B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B10/00Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/07Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
    • H04B10/075Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
    • H04B10/079Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B10/00Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60Receivers
    • H04B10/66Non-coherent receivers, e.g. using direct detection
    • H04B10/69Electrical arrangements in the receiver
    • H04B10/693Arrangements for optimizing the preamplifier in the receiver
    • H04B10/6931Automatic gain control of the preamplifier

Landscapes

  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Optical Communication System (AREA)
  • Control Of Voltage And Current In General (AREA)

Description

【発明の詳細な説明】 本発明はバイアス制御回路、特に光信号受信回
路内におけるアバランシエ・ホト・ダイオード
(以下APDと称す)に印加されるべきバイアス制
御電圧を供給するためのバイアス制御回路に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bias control circuit, and particularly to a bias control circuit for supplying a bias control voltage to be applied to an avalanche photodiode (hereinafter referred to as APD) in an optical signal receiving circuit.

近年光フアイバによる光通信が実用に供されつ
つある。この場合、考慮されるべき技術的事項の
1つに光レベルの変動の抑圧がある。この光レベ
ルの変動には、主としてライン(光フアイバ)の
状態に起因するものと、APDの温度変動に起因
するものとがある。本発明はこのうち後者の
APDに係る光レベルの変動の抑圧について言及
する。
In recent years, optical communication using optical fibers has been put into practical use. In this case, one of the technical considerations to be taken into account is suppression of light level fluctuations. This variation in light level is mainly caused by the condition of the line (optical fiber), and some is caused by temperature variation of the APD. The present invention focuses on the latter.
We will discuss suppression of light level fluctuations related to APD.

一般に光通信システムは光信号送信回路とライ
ンと光信号受信回路とからなるがこれらの系の光
のレベル変動を監視するため、いわゆるパイロツ
ト信号が導入される。、このパイロツト信号は光
信号信回路内においてAPDに対するAGC(オー
トマチツク・ゲイン・コントロール)信号とし働
き光レベルの変動を抑える。
Generally, an optical communication system consists of an optical signal transmitting circuit, a line, and an optical signal receiving circuit, and a so-called pilot signal is introduced in order to monitor changes in the level of light in these systems. This pilot signal acts as an AGC (automatic gain control) signal for the APD in the optical signal transmission circuit to suppress fluctuations in the optical level.

ところで従来は、APDが大きな温度変動特性
を有するにも拘らず、これを積極的に抑圧しよう
としていなかつた。なぜなら前記AGC信号を処
理するためのAGC回路にそのような変動を抑圧
する効果をもともと備えているからである。然し
ながら、高安定な受信出力を得るためには、積極
的に温度変動に対する補償回路を設けるべきであ
る。一方、前記AGC回路についてみると、一般
に、AGCオン又はAGCオフという状態に置かれ
ることがある。AGCオンの状態は、通常の動作
状態である。AGCオフの状態は、光信号受信回
路をマニユアル操作(定期点検、故障処理等)す
る状態である。特にAGCオフの状態は、前述し
たAGC固有の温度変動抑圧効果がないから、
APDの温度変動は大きく現われる。これを抑圧
すべく、一般にはAGCオフ状態での温度補償手
段を特別に用意してある。かくの如く従来は
AGCオン時、AGCオフ時に個別の温度補償がな
されており、操作上も設計上も不便があつた。
又、AGCオン時における高安定出力の確保とい
う保証もなかつた。
By the way, conventionally, although APD has large temperature fluctuation characteristics, no attempt has been made to actively suppress this. This is because the AGC circuit for processing the AGC signal is inherently equipped with the effect of suppressing such fluctuations. However, in order to obtain a highly stable reception output, a compensation circuit for temperature fluctuations should be proactively provided. On the other hand, regarding the AGC circuit, it is generally placed in an AGC on or AGC off state. The AGC on state is the normal operating state. The AGC off state is a state in which the optical signal receiving circuit is manually operated (periodic inspection, troubleshooting, etc.). In particular, in the AGC off state, there is no temperature fluctuation suppression effect inherent to AGC mentioned above.
APD temperature fluctuations appear significantly. In order to suppress this, a special temperature compensation means is generally provided in the AGC off state. Conventionally, like this
Separate temperature compensation was performed when AGC was on and when AGC was off, which was inconvenient both in terms of operation and design.
Furthermore, there was no guarantee that a highly stable output would be ensured when AGC was turned on.

従つて本発明の目的は、AGCオン時とオフ時
を全く意識することなく、高安定な出力が常に得
られ、しかもハードウエア上殆どその規模を増大
させることがない、APDのバイアス制御回路を
提案することである。
Therefore, an object of the present invention is to provide an APD bias control circuit that can always provide a highly stable output without being aware of when the AGC is on or off, and which hardly increases the scale of the hardware. It is to make a proposal.

上記目的に従い本発明は、光信号を入力として
これを電気信号に変換するAPD(アバランシ
エ・ホト・ダイオード)に対し、AGC(オート
マチツク・ゲイン・コントロール)ループを形成
するように並列接続され、前記APDに対するバ
イアス制御電圧を供給するバイアス制御回路にお
いて、前記AGCループのループ外に前記APDの
温度補償回路を設け、該温度補償回路からの温度
補償電圧を所定の電圧に増幅した後、常に前記バ
イアス制御電圧に加算することを特徴とするもの
である。
In accordance with the above object, the present invention provides an APD (Avalanche Photo Diode) which inputs an optical signal and converts it into an electrical signal, which is connected in parallel to form an AGC (Automatic Gain Control) loop. In a bias control circuit that supplies a bias control voltage to an APD, a temperature compensation circuit for the APD is provided outside the AGC loop, and after amplifying the temperature compensation voltage from the temperature compensation circuit to a predetermined voltage, the bias control circuit is always applied to the APD. It is characterized in that it is added to the control voltage.

以下図面に従つて本発明を説明する。 The present invention will be explained below with reference to the drawings.

第1図は一般的な、APDを用いた光通信シス
テムの概略を示すブロツク図である。本図におい
て、伝送すべき電気信号Eioは電気/光・変換器 (E/O)11において光信号に変換され、光フ
アイバのライン12を経由して、APDを含む
光/電気・変換器(O/E)13において電気信
号Eputに変換される。この場合、変換器11、
ライン12、変換器13を通して生ずる光レベル
の変動を抑圧すべく、発振器14からパイロツト
信号を適宜送り出し、受信側の変換器13におい
てこれを監視することが以前より行なわれてい
る。つまり電気信号Eputの一部を分岐してフイ
ルタ15よりパイロツト信号を抽出し、増幅器1
6で増幅し、整流回路17で整流したのち、バイ
アス制御回路18より前記APDに対するバイア
ス制御電圧eを供給する。このバイアス制御電圧
eは通常100Vを中心とした高レベルの電圧であ
り、APDの電流増幅率Mを変化させる。つま
り、バイアス制御電圧eの変化を電流増幅率Mの
変化に置き換えて、光レベルの変動(パイロツト
信号レベルの変動)を安定化させる。このバイア
ス制御電圧eと電流増幅率Mの関係を例示したの
が第2図のグラフである。本グラフ中の特性曲線
22に関し、電圧e1に対し増幅率M1が一義的
に定まる。ところが、一般的にAPDは温度変動
の影響を受け易く、該曲線22は1V/℃という
オーダーで、温度の高低変化に対し、曲線21又
は曲線23へシフトする。そうなると、電圧e1
に対して正しい増幅率M1が確保されない。
FIG. 1 is a block diagram schematically showing a general optical communication system using an APD. In this figure, an electrical signal E io to be transmitted is converted into an optical signal in an electrical/optical converter (E/O) 11, and is sent to an optical/electrical converter including an APD via an optical fiber line 12. (O/E) 13 converts it into an electrical signal E put . In this case, the converter 11,
In order to suppress fluctuations in the light level occurring through the line 12 and the converter 13, it has been conventional practice to send out a pilot signal from the oscillator 14 as appropriate and monitor it at the converter 13 on the receiving side. In other words, a part of the electric signal E put is branched, a pilot signal is extracted from the filter 15, and the pilot signal is output to the amplifier 1.
6 and rectified by a rectifier circuit 17, a bias control voltage e is supplied from a bias control circuit 18 to the APD. This bias control voltage e is usually a high level voltage around 100V, and changes the current amplification factor M of the APD. In other words, changes in the bias control voltage e are replaced with changes in the current amplification factor M to stabilize fluctuations in the optical level (fluctuations in the pilot signal level). The graph in FIG. 2 illustrates the relationship between the bias control voltage e and the current amplification factor M. Regarding the characteristic curve 22 in this graph, the amplification factor M1 is uniquely determined for the voltage e1. However, APDs are generally susceptible to temperature fluctuations, and the curve 22 shifts to the curve 21 or 23 in response to changes in temperature, on the order of 1 V/°C. In that case, the voltage e1
A correct amplification factor M1 is not ensured for this.

上述したような温度変動に伴う増幅率Mの変動
がありながら、従来はこれを積極的に補償してい
なかつた。というのは、第1図の13→15→1
6→17→18→13というAGCループがその
変動をある程度吸収してくれたからである。とこ
ろが、近年はもつと安定度の良い出力が求められ
ており、積極的な温度補償回路の導入が必要にな
つた。
Although the amplification factor M fluctuates due to temperature fluctuations as described above, conventionally, this has not been actively compensated for. That is, 13→15→1 in Figure 1.
This is because the AGC loop of 6 → 17 → 18 → 13 absorbed the fluctuation to some extent. However, in recent years, there has been a demand for highly stable output, and it has become necessary to proactively introduce a temperature compensation circuit.

然しながら全く温度補償回路が無いわけではな
い。すなわち既述のAGCオフ時には該回路が適
宜導入されていた。従つてこの温度補償回路が
AGCオン時の如何にかかわらず常に態動状態に
あれば、理想的な温度補償が実現される。このた
め、本発明は前記AGCループのループ外から温
度補償電圧を常にバイアス制御電圧eに加算する
ものとする。ここにAGCループのループ外とし
たのは、ループ内であると、本来の温度補償電圧
が、AGCの伝達利得分の1に抑圧されてしまう
からである。
However, this does not mean that there is no temperature compensation circuit. That is, the circuit was appropriately installed when the AGC was turned off as described above. Therefore, this temperature compensation circuit
Ideal temperature compensation can be achieved if it is always in the active state regardless of whether AGC is on or not. Therefore, in the present invention, the temperature compensation voltage is always added to the bias control voltage e from outside the AGC loop. The reason why this is placed outside the AGC loop is that if it were inside the loop, the original temperature compensation voltage would be suppressed to 1/the transfer gain of the AGC.

上述の考え方を実現したのが第3図の実施例で
ある。本回路30は全体として第1図のバイアス
制御回路18に相当する。図中、レベル変動検出
部31とレベル変換部32はほぼ従来どおりであ
り、これらに対して新たに本発明による温度補償
回路33が付加される。整流回路17(第1図)
からの直流レベルのパイロツト信号はスイツチ3
4(本発明の必須部分ではない)を経て演算増幅
器に入力され、基準レベルVrefとレベル比較さ
れる。なお、コンデンサCは一定の時定数をもた
せるためであり、本発明の必須部分ではない。
又、スイツチ35も本発明の必須部分ではない。
かくして、レベル比較した信号はバイアス制御指
定信号V2としてレベル変換部32に至る。この
レベル変換部32は、APDのバイアス制御電圧
として使用しうるレベルまで前記信号V2を増幅
する。すなわち、図中の+VB←→−VEは数100V
のオーダに及ぶ。これらレベル変動検出部31お
よびレベル変換部32は前記AGCループのルー
プ内のものである。これらに対し、ループ外から
温度補償回路33を付加する。温度変動の検出は
ダイオードDが行う。ダイオードDは通常、
2mV/℃という特性であるから、これを演算増
幅器36により所定の電圧まで増幅して、温度補
償信号V1とする。この結果、レベル変換部32
に対するバイアス制御指示信号V3は、これら信
号V1,V2を加算したものとなる。ここで共に抵
抗値Rの抵抗を介してこれら信号V1,V2を加算
すれば、信号V1,V2およびV3の各電圧レベル
v1,v2およびv3の間には、 v3=1/2(v1+v2) の関係が得られる。
The embodiment shown in FIG. 3 realizes the above idea. This circuit 30 as a whole corresponds to the bias control circuit 18 in FIG. In the figure, a level fluctuation detection section 31 and a level conversion section 32 are almost the same as conventional ones, and a temperature compensation circuit 33 according to the present invention is newly added to these. Rectifier circuit 17 (Fig. 1)
The DC level pilot signal from
4 (not an essential part of the present invention), and is input to an operational amplifier, where the level is compared with a reference level V ref . Note that the capacitor C is provided to provide a constant time constant, and is not an essential part of the present invention.
Further, the switch 35 is also not an essential part of the present invention.
The level-compared signals thus reach the level converter 32 as the bias control designation signal V2 . This level converter 32 amplifies the signal V 2 to a level that can be used as a bias control voltage of the APD. In other words, +V B ←→-V E in the figure is several 100V
of the order of . These level fluctuation detection section 31 and level conversion section 32 are included in the AGC loop. A temperature compensation circuit 33 is added to these from outside the loop. Diode D detects temperature fluctuations. Diode D is usually
Since it has a characteristic of 2 mV/°C, this is amplified to a predetermined voltage by the operational amplifier 36 and used as the temperature compensation signal V1 . As a result, the level converter 32
The bias control instruction signal V 3 for the signal V 3 is the sum of these signals V 1 and V 2 . Here, if these signals V 1 and V 2 are added together through a resistor with a resistance value R, each voltage level of the signals V 1 , V 2 and V 3 is
The relationship v 3 = 1/2 (v 1 + v 2 ) is obtained between v 1 , v 2 and v 3 .

ところで、前述のスイツチ34(スイツチ35
と連動)は、AGCオン時で実線の接続位置にあ
り、AGCオフ時で点線の接続位置にある。AGC
オフ時には端子37から所望の電圧を与えるわけ
であるが、この場合、従来はダイオードD′によ
り温度補償を一緒に加えていた。然しこのダイオ
ードD′は本発明により不要となる。本発明の温
度補償回路33がその役目を果してくれるからで
ある。なお、スイツチ35はゲイン制御用のスイ
ツチであり、AGCオフ時にはゲインを下げてお
く。AGCオン時へ向けて再投入する際、このゲ
インが大であると、異常な高レベル出力が信号
V2として現われ、アラームの原因になるからで
ある。
By the way, the above-mentioned switch 34 (switch 35
) is at the connection position indicated by the solid line when AGC is on, and at the connection position indicated by the dotted line when AGC is off. AGC
In the off-state, a desired voltage is applied from the terminal 37, but in this case, conventionally, temperature compensation was also added using the diode D'. However, this diode D' is no longer necessary according to the invention. This is because the temperature compensation circuit 33 of the present invention fulfills this role. Note that the switch 35 is a switch for gain control, and the gain is lowered when AGC is turned off. If this gain is large when re-energizing the AGC to turn it on, an abnormally high level output will occur as a signal.
This is because it appears as V 2 and causes an alarm.

以上説明したように本発明によれば、AGCオ
ン時もAGCオフ時も共に高安定出力を維持で
き、又、設計上もAGCオン時、AGCオフ時の区
別なしにハードウエア構成を考えることができる
から便利である。
As explained above, according to the present invention, a highly stable output can be maintained both when AGC is on and when AGC is off, and in terms of design, it is possible to consider the hardware configuration without distinguishing between when AGC is on and when AGC is off. It's convenient because you can.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は一般的な、APDを用いた光通信シス
テムの概略を示すブロツク図、第2図はバイアス
制御電圧eと電流増幅率Mの関係を例示したグラ
フ、第3図は本発明に基づくバイアス制御回路の
一実施例を示す回路図である。 図において、30はバイアス制御回路、31は
レベル変動検出部、32はレベル変換部、33は
温度補償回路、eはバイアス制御電圧である。
Fig. 1 is a block diagram schematically showing a general optical communication system using an APD, Fig. 2 is a graph illustrating the relationship between bias control voltage e and current amplification factor M, and Fig. 3 is based on the present invention. FIG. 2 is a circuit diagram showing an example of a bias control circuit. In the figure, 30 is a bias control circuit, 31 is a level fluctuation detection section, 32 is a level conversion section, 33 is a temperature compensation circuit, and e is a bias control voltage.

Claims (1)

【特許請求の範囲】[Claims] 1 光信号を入力としてこれを電気信号に変換す
るAPD(アバランシエ・ホト・ダイオード)に
対し、AGC(オートマチツク・ゲイン・コント
ロール)ループを形成するように並列接続され、
前記APDに対するバイアス制御電圧を供給する
バイアス制御回路において、前記AGCループの
ループ外に前記APDの温度補償回路を設け、該
温度補償回路からの温度補償電圧を所定の電圧に
増幅した後、常に前記バイアス制御電圧に加算す
ることを特徴とするバイアス制御回路。
1 Connected in parallel to form an AGC (automatic gain control) loop to an APD (avalanche photodiode) that receives an optical signal and converts it into an electrical signal.
In a bias control circuit that supplies a bias control voltage to the APD, a temperature compensation circuit for the APD is provided outside the AGC loop, and after amplifying the temperature compensation voltage from the temperature compensation circuit to a predetermined voltage, A bias control circuit characterized by adding to a bias control voltage.
JP55177093A 1980-12-17 1980-12-17 Bias controlling circuit Granted JPS57101443A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55177093A JPS57101443A (en) 1980-12-17 1980-12-17 Bias controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55177093A JPS57101443A (en) 1980-12-17 1980-12-17 Bias controlling circuit

Publications (2)

Publication Number Publication Date
JPS57101443A JPS57101443A (en) 1982-06-24
JPS6120178B2 true JPS6120178B2 (en) 1986-05-21

Family

ID=16025002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55177093A Granted JPS57101443A (en) 1980-12-17 1980-12-17 Bias controlling circuit

Country Status (1)

Country Link
JP (1) JPS57101443A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0381066U (en) * 1989-12-11 1991-08-20

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60111540A (en) * 1983-11-21 1985-06-18 Nec Corp Temperature compensating circuit of apd

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0381066U (en) * 1989-12-11 1991-08-20

Also Published As

Publication number Publication date
JPS57101443A (en) 1982-06-24

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