JPS6120959B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a non-volatile semiconductor that can completely prevent the inconvenience of information written in an electrically rewritable non-volatile memory being damaged when power is turned on or off. The present invention relates to a memory control circuit.

With the recent spread of microcomputers, nonvolatile semiconductor memory is opening up a wide range of application fields as peripheral memory. Among them, MIOS (Metal-Insulator-Oxide-
Non-volatile semiconductor memory with a semiconductor structure has a particularly wide range of applications. By the way, when comparing a nonvolatile semiconductor memory and a normal semiconductor memory, they differ in whether or not they maintain a correct storage state when the power is turned off. That is, the former non-volatile semiconductor memory must always be in a correct storage state both when the power is turned off and when the power is turned on.

FIG. 1 is a block diagram showing the configuration of a conventional nonvolatile semiconductor memory control circuit, in which 1 is a nonvolatile semiconductor memory circuit section, 2 is a control circuit that controls the storage state of the nonvolatile memory circuit section, 3 is a drive power supply terminal to which a power supply voltage for driving the control circuit 2 is applied; 4, 5 and 6 are control signal input lines for inputting a control signal to the control circuit 2; and 7. , 8 and 9 are control signal input lines for inputting storage state control signals to the nonvolatile semiconductor memory section 1.

In the conventional nonvolatile semiconductor memory control circuit configured as described above, when the power supply voltage does not reach a predetermined level at power-on or power-off, generally speaking, the control signal input lines 4 to
The signal number 6 is not in the correct logic state. When the logic state of the signals on the control signal input lines 4 to 6 is in this state, if a voltage for driving the control circuit 2 is applied to the drive power supply terminal 3, the correct signal is sent to the control signal input lines 7 to 9. A storage state control signal that is not in a logical state is output from the control circuit, and in some cases, careless writing or erasing may be performed on the nonvolatile semiconductor memory circuit section 1.
The above-described writing and erasing, which inadvertently changes stored information when power is turned on or off, is unacceptable in nonvolatile memory devices.

The present invention provides a non-volatile semiconductor memory control circuit that can eliminate the above-mentioned disadvantages that existed in conventional non-volatile semiconductor memory control circuits, and which changes the storage conditions of the non-volatile semiconductor memory circuit section. A feature of the present invention is that the power supply control input controls the application and discontinuation of the power required to the nonvolatile semiconductor memory circuit and the control circuit that controls the storage state.

The configuration and operation of the nonvolatile semiconductor memory control circuit of the present invention will be described below with reference to FIG. The following explanation will be given on the assumption that the control circuit shown in FIG. 2 is constituted by a P-channel MOS integrated circuit.

As shown in the figure, a nonvolatile semiconductor memory circuit section 1, a control circuit 2, and control signal input lines 4 to
The connection relationships of 6, 7 to 9 are the same as before, but the MOS transistor 1 has a drain source circuit connected in series between the low level power supply terminal 10 and the ground point.
1 and 12, a terminal 13 into which a power control signal is input;
The power supply control signal input to the same terminal 13 is transmitted in the same phase to the signal line 14 connected to the gate of the MOS transistor 11, and the inverters 15 and 16 and the MOS transistor 12 are connected to the inverters 15 and 16 for level shifting the power supply voltage. A power supply control circuit section 19 is added, which is composed of an inverter 18 that functions to transmit a control signal of opposite phase to the control signal of the signal line 14 to the signal line 17 connected to the gate. The configuration is such that a driving voltage is supplied to the control circuit 2 from a connection point A between MOS transistors 11 and 12 in the unit.

The nonvolatile semiconductor memory control circuit of the present invention having such a configuration performs the following operations.

First, when the terminal 13 is kept at a high level (ground level), the signal line 14 is at a high level, while the signal line 17 is at a low level. Therefore, the MOS transistor 11 is turned off, while the MOS transistor 12 is turned on. Therefore,
The potential at point A is at a high level (ground level), and no driving voltage is applied to the control circuit 2.

Next, when the level of the power supply control voltage applied to the terminal 13 is set to a low level, the signal line 14 becomes a low level, while the signal line 17 becomes a high level, and the MOS
Transistor 11 is turned on and MOS transistor 12 is turned off. As a result,
A drive voltage is supplied to the control circuit 2 from the power supply terminal 10 through the MOS transistor 11 and the point A.

Incidentally, the inverters 15 and 16 arranged between the terminal 13 and the signal line 14 are circuit elements that are unnecessary if the power supply control voltage applied to the terminal 13 is simply transmitted to the signal line 14 in the same phase. , these inverters operate when the voltage level of the power supply terminal 10 reaches a predetermined level, and therefore, when the power supply voltage reaches a predetermined level, the MOS transistors 11 and 12 are activated by these inverters. The effect of applying the power supply voltage to the control circuit 2 when the desired voltage level is reached is produced.

According to the nonvolatile semiconductor memory control circuit of the present invention, as is clear from the above description, the application and interruption of the drive power supply voltage to the control circuit 2 is controlled by the level of the power supply control voltage applied to the terminal 13. When rewriting memory information,
Alternatively, if the voltage level of the terminal 13 is kept at a low level during erasing, the driving power supply voltage is supplied to the control circuit 2 under the condition that the logic states of the control signal input lines 4 to 6 are correct, and the output from the control circuit 2 is Accordingly, the nonvolatile semiconductor memory section 1 can be rewritten or erased without error.

Furthermore, when power is turned on or off to the device, if the level of the power supply control voltage applied to the terminal 13 is kept at a high level, the application of the power supply voltage to the control circuit 2 is blocked, and therefore, this control circuit 2
Even if any signal is carelessly input to the nonvolatile semiconductor memory circuit section 1, the storage state of the nonvolatile semiconductor memory circuit section 1 will not be changed carelessly. Then, if the power supply control voltage level is set to a low level after the power supply voltage level applied to the device becomes an appropriate level and the control signals on the control signal lines 4 to 6 reach the correct logic state,
A power supply voltage is applied to the control circuit 2, and a circuit state is established in which the storage state of the nonvolatile semiconductor memory circuit section can be controlled.

In the nonvolatile semiconductor memory control circuit of the present invention,
In addition to the above effects, the following effects are also produced.

(1) Power consumption can be reduced because one of the MOS transistors is always cut off.

(2) When the power supply voltage to the control circuit 2 is cut off by the power supply control voltage, the power supply point of the control circuit 2
Since it is connected to the ground point via the MOS transistor 12, the power supply point quickly becomes the ground level, and preparation for power supply to the device or power cutoff of the device is completed in an extremely short time.

Although the present invention has been described above assuming that the control circuit is configured with a P-channel MOS integrated circuit, the present invention can be implemented using any of N-channel, CMOS, or bibolar integrated circuits, or individual components.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional example of a nonvolatile semiconductor memory control circuit, and FIG. 2 is a diagram showing a nonvolatile semiconductor memory control circuit section according to the present invention. DESCRIPTION OF SYMBOLS 1...Nonvolatile semiconductor memory circuit section, 2...Control circuit for memory state control, 3, 10...Power terminal, 4-6, 7-9...Control signal input line, 11,
12... MOS transistor, 13... Power supply control voltage application terminal, 14, 17... Signal line, 15, 1
6, 18... Inverter, 19... Power supply control circuit section.

Claims (1)

[Scope of Claims] 1. A power supply control circuit section is added to a nonvolatile semiconductor memory device including a nonvolatile semiconductor memory circuit section and a control circuit that controls the storage state of the nonvolatile semiconductor memory circuit section, and the power supply control circuit section Application and interruption of the power supply voltage required to change the information in the nonvolatile semiconductor memory to the control circuit is controlled by a power supply control voltage level applied to a power supply control voltage application terminal attached to the circuit section. Non-volatile semiconductor memory control circuit. 2. A power supply control circuit unit is connected in series between a power supply and a ground point, and controls first and second switch elements having control electrodes, a power supply control voltage application terminal, and the first switch element. first and second inverters connected in series between the electrodes; and a third inverter connected between the control electrode of the first switch element and the control electrode of the second switch element.
2. The nonvolatile semiconductor memory control circuit according to claim 1, wherein the nonvolatile semiconductor memory control circuit is comprised of an inverter. 3. The nonvolatile semiconductor memory control circuit according to claim 1, wherein the power feeding point of the control circuit is a series connection point of the first and second switch elements. 4. The nonvolatile semiconductor memory control circuit according to claim 1, wherein the first and second switch elements are MOS transistors.