JPS6124654B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor circuit testing method that makes it possible to efficiently and effectively analyze a circuit portion that governs the operating margin characteristics of a semiconductor circuit.

Traditionally, this type of analysis requires simulation under conditions of multiple power supply voltages or clock voltages near the boundary between the operating region and non-operating region (hereinafter referred to as the "operating margin boundary") of the operating margin characteristics of a semiconductor circuit. Then, for each circuit part in the semiconductor circuit, changes in operating speed and changes in operating margin with respect to changes in the power supply voltage or clock voltage are investigated in detail, and based on the results, the overall operating margin of the semiconductor circuit is determined. It is necessary to investigate the parts of the circuit that govern the characteristics.

However, with this conventional method, it takes a long time to investigate the factors governing the operating characteristics of a semiconductor circuit under conditions of one power supply voltage or clock voltage on the boundary of the operating margin, and the analysis area of operating characteristics is wide-ranging. In some cases, the investigation will require even more time.

Furthermore, with conventional methods, the accuracy of simulation is extremely limited, so it is extremely difficult to accurately identify the controlling factors of the operating characteristics of semiconductor circuits, and if the controlling factors are not in the circuit configuration but in the manufacturing process also has the disadvantage that this method cannot be applied.

The semiconductor circuit testing method according to the present invention solves the problems of these conventional methods, and makes it possible to accurately identify circuit parts that control the operating margin characteristics in a semiconductor circuit based on the operating time.

The semiconductor circuit testing method according to the present invention will be explained in detail below based on examples thereof.

FIG. 1 is a diagram showing the operating margin characteristics of a MOS memory.

In the figure, VDD on the horizontal axis represents the power supply voltage that drives the memory circuit, and VBB on the vertical axis represents the substrate voltage applied to the substrate of the memory chip. Further, NA is a non-operating area, AA is an operating area, curve AMS is a curve indicating an operating margin boundary, and the area surrounded by a dotted line AR indicates an operating standard area.

FIG. 2 is a diagram showing an embodiment of applying a power supply voltage or a clock voltage based on the method according to the present invention, where CE is a clock voltage applied from the outside to drive the MOS memory circuit, and the time t _SB During the time interval, the memory circuit is in a standby state, ie, in a dormant state, during time t _CE , the memory circuit is in an enabled state, ie, in an operating state, and at time t ₂ , the MOS memory circuit starts operating.

As shown in Fig. 1, consider the case where there is a defective operating margin near point A, and with the same substrate voltage VBB1 near point A, point P in the operating area AA and F in the non-operating area NA. Take the points and let the values of the respective power supply voltages be VDDP and VDDF.

Next, using the high level power supply voltage value VDDP and the low level power supply voltage value VDDF, the pulse width t _W and the rise time t ₂ of the clock voltage CE are determined as shown in FIG.
The delay time from _tD forms a pulse voltage.

This pulse voltage with pulse width t _W is applied to the substrate voltage.
Apply to the power supply pin of the memory circuit set to VBB1. As a result, between the operation start time t ₂ and the operation end time _{t 3} of the memory circuit, the memory circuit is in the non-operation region with the operation margin characteristics shown in FIG. The voltage condition is the power supply voltage VDDF at point F in NA, and at other times, the voltage condition is the power supply voltage VDDP at point P in the operating area AA.

In this way, by setting the pulse width t _W to a predetermined value and applying the pulse voltage formed as shown in _FIG. The characteristics of the delay time t _D and the access time t _A are shown in FIG. 3. As shown in the figure, the characteristics of the delay time t _D and the access time are t _a and t _b here, and have peak values exceeding the access time t _ACC when measuring the operating margin characteristics. As a result, in the memory circuit, from time t _a to t _a +t _w and from t _b to t _b +
It can be seen that the circuit portion operating during the period _tw enters into a malfunctioning state near point A of the operating margin characteristics shown in FIG. The circuit portion operating between time t _a to t _a +t _w and from t _b to t _b + t _w is the memory circuit under the conditions of the power supply voltage and substrate voltage at point A of the operating margin characteristics in Figure 1. A simulation is performed and the time at which the output signal changes for each circuit part in the memory circuit, that is, the operation time, changes from time t _a to t _a +t _w or from t _b to t _b +
This can be easily detected by checking whether it is between t _w or not.

In the above explanation, an example has been described in which the power supply voltage is applied in pulses to the memory circuit, but in addition to this, it is also possible to apply the clock voltage in pulses at a low level or high level, or to apply various power supply voltages. It is also possible to apply an application method using a plurality of combinations of the clock voltage and the clock voltage.

As explained in detail above, the semiconductor circuit testing method according to the present invention includes a first means for forming a test pulse based on the power supply voltage or clock voltage in the operating region and non-operating region of the semiconductor circuit;
The second method is to apply the test pulse obtained by the above method to the power supply terminal or clock terminal of the semiconductor circuit and change the delay time or pulse width. By employing the third means of detecting and diagnosing a circuit portion that is in an operating state, it is possible to identify a circuit portion that governs the operating margin characteristics of a semiconductor circuit based on its operating time. Therefore, as in the past, by simulation, we examine in detail the changes in operating speed and changes in operating margin in response to changes in the power supply voltage or clock voltage near the operating margin boundary for individual circuit parts in a semiconductor circuit. There is no need to investigate the controlling factors, and it is possible to point out the controlling factors extremely efficiently by simply determining the operating time of each circuit part through simulation. Furthermore, even when the controlling factor is due to something other than the circuit configuration, for example, the manufacturing process, it is possible to analyze the operating characteristics by pointing out the operating time of the circuit portion that controls the operating characteristics.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the operating margin characteristics of a MOS memory, and FIG. 2 is a diagram showing an example of applying a power supply voltage or clock voltage based on the method according to the present invention.
FIG. 3 is a diagram showing the characteristics of delay time and access time based on the method according to the present invention. Explanation of symbols VDD...Power supply voltage, VBB...Board voltage, CE...
...clock voltage, _tD ...delay time, _tA ...access time.

Claims (1)

[Claims] 1. During a period in which a power supply voltage or clock voltage in an operating region is applied to a semiconductor circuit that performs periodic operation, a test pulse is applied to the power supply voltage or clock voltage to bring it to a value in a non-operating region for a predetermined period. and a first means for applying the test pulse to a power supply terminal or a clock terminal of the semiconductor circuit, driving the semiconductor circuit in a predetermined test pattern, and changing the test pulse delay time or pulse width. and a third means for detecting and diagnosing a circuit portion that governs the operating characteristics of the semiconductor circuit at the boundary between the operating region and the non-operating region based on the output signal of the semi-dynamic body circuit obtained by the second means. A method for testing a semiconductor circuit, comprising the steps of: