JPS6126082B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a duty ratio control method for an on-off type solenoid valve used as a drive member in, for example, a control device for an automobile engine. In general, for example, in an engine control device, the central processing unit (CPU) of a microcomputer selects the optimum on/off (ON -OFF) ratio, that is, the target duty, is calculated, and the on/off of the solenoid valve is controlled based on this calculation result. Conventionally, this
When controlling the solenoid valve using the calculated value of the CPU, the 31st
As shown in the figure, the calculated value of the CPU 60 is temporarily stored in the latch 700 in response to a set command signal from the CPU 60, and is output from the control circuit 701 in response to a clock signal (for example, a 50 ms clock) corresponding to a predetermined control cycle (for example, 50 ms). Instructs the down counter 702 to load the memory contents (calculated value) of the latch 700,
Immediately after that, the down counter 7 is sent from the control circuit 701.
02, and when the contents of the down counter 702 are not "0", the flip-flop 703 is set, and the down counter 702 counts down the calculated value with a down count clock of a constant cycle, and then outputs a count end signal. Normally, the flip-flop 703 is reset and the Q output signal of the flip-flop 703 is used to control the solenoid valve. However, this method requires a latch, a down counter, and a control circuit, resulting in a complicated circuit configuration. On the other hand, by eliminating such latches, down counters, and control circuits,
Directly executes the down count function on the CPU,
It is also possible to directly control the on/off of the solenoid valve from the CPU, but this method is impossible in terms of the processing capacity of the CPU because the down-counting cycle is small. There is a problem in that the counting period increases, leading to a decrease in the control response of the solenoid valve. The present invention has been made in view of the above points.
The CPU determines whether the solenoid valve should be turned on or off at predetermined intervals based on a pre-calculated target duty ratio that determines the ratio between on and off of the off-actuated solenoid valve, A method for controlling the duty ratio of a solenoid valve by controlling the solenoid valve to turn on or off at each predetermined period based on the determination result, the method comprising: controlling the duty ratio of the solenoid valve by controlling the solenoid valve to turn on or off at each predetermined cycle, It is determined at each predetermined period whether the solenoid valve should be turned on or off by comparing at each predetermined period whether the ratio of rotation to off rotation is larger or smaller than the target duty ratio. This feature allows the CPU to directly issue on/off control commands for the solenoid valve, which enables the simplification of the circuit and improves the control response of the solenoid valve. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an overall configuration diagram when the present invention is applied to a four-cylinder engine. Reference numeral 1 denotes an intake air amount sensor for detecting the intake air amount of the engine, and for example, in this example, a hot wire type sensor is used. 2 is an intake air temperature sensor, and 3 is a water temperature sensor that detects the temperature of engine cooling water. 13 is a carburetor, which is a solenoid valve for air bleed control (hereinafter referred to as
VSV) 15 is controlled on-off (ON-OFF) based on commands from the microcomputer 6,
In other words, the duty ratio is controlled, thereby controlling the amount of air added to the air bleed 14, that is, the air-fuel ratio of the air-fuel mixture. 9,10,1
1 and 12 are components that control exhaust gas recirculation (hereinafter referred to as EGR), 11 is a vacuum modulator, 10 is an EGR first valve, 9 is an EGR second valve, and 12 is a component for controlling the EGR second valve. This is a negative pressure switching solenoid valve (VSV). 4 is 1 for every 2 revolutions of the engine
This is a conventional rotating distributor with a rotation (angle) sensor 5 built into the housing. The computer 6 detects the engine condition from the outputs of the rotation sensor 5 and the intake air amount sensor 1, reads the optimal EGR rate (EGR amount/total gas amount in the cylinder) at that time from the built-in storage device (ROM), and interpolates it. It is calculated and further corrected according to the output values of the intake air temperature sensor 2, the water temperature sensor 3, and the atmospheric pressure sensor 20 installed inside the computer. In order to achieve this corrected EGR rate with the EGR system shown, the diaphragm chamber 91 of the second EGR valve 9
Turn on the EGR VSV12 (introduce negative pressure) so that the pressure becomes the calculated value corresponding to the target optimal EGR rate.
Turn off (introduce atmosphere) and perform feedback control. The atmospheric chamber 96 of the second EGR valve 9 is in communication with the atmosphere, and depending on the pressure difference between the atmospheric chamber 96 and the diaphragm chamber 91, the diaphragm 92 integrated with the valve 97 reaches a position where it balances the repulsive force of the spring 91. 1, so that the valve 97 moves to the right in FIG. 1, and exhaust gas is introduced from the exhaust passage 95 connected to the exhaust manifold through the constant pressure chamber 94 into the intake manifold. The constant pressure chamber 94 is maintained at a substantially constant pressure (atmospheric pressure) by the actions of the EGR first valve 10 and the vacuum modulator 11. A diaphragm chamber pressure sensor 21 is installed inside the computer and detects the actual EGR rate, that is, the pressure inside the diaphragm chamber 91 of the second EGR valve 9. In this example, the ignition system eliminates the conventional high-voltage distributor and adopts a dayless double coil system using two coils, 8 being the igniter,
7 is the ignition coil. The computer 6 detects the engine condition from the outputs of the rotation sensor 5 and the intake air amount sensor 1, reads out the optimum ignition angle at that point from the built-in storage device (ROM), performs interpolation calculations, and also calculates the optimum ignition angle based on the value of the water temperature sensor and the warm-up angle. The time acceleration state and EGR rate are corrected, and the energization time is read from the ROM based on the battery voltage and calculated by interpolation. In accordance with this calculation result, the computer 6 refers to the signal from the rotation sensor 5 to control the actual ignition timing and energization ON timing in real time. 16 is an engine, 17 is an operation panel for the computer 6, 18 is a power source for the computer, 19 is a battery, and 22 is a starter switch. FIG. 2 shows a block diagram for explaining the microcomputer 6 in detail. 60 is a central processing unit (CPU) that calculates ignition timing, EGR rate (diaphragm chamber pressure), etc., and uses the 9900 series manufactured by TI. 71 is a read-only memory unit (ROM) that stores programs, optimum advance angle values for each engine condition, EGR rate, etc.;
indicates the temporary storage unit (RAM) used during program operation. The rotation sensor 5 shown in FIG. 1 is composed of a disc attached to a distributor shaft that rotates once every two revolutions of the engine crankshaft, and an electromagnetic pickup. The discs are magnetized in the order of N→S→N at equal intervals in the circumferential direction, and two magnets are embedded at 180 degrees from each other for TDC (engine top dead center) detection. Therefore, the outputs of the two pickups 50 and 51 contain 24 pulses as a crank angle signal for one revolution of the distributor.
Two pulses are obtained as the TDC signal. This pickup output waveform shaping circuit is built into the distributor 4, and the computer has a crank angle signal terminal 51 and a TDC signal terminal 50.
, as shown in Figure 3 a and b, respectively.
A TTL level signal is input. The crank angle counter section 61 transfers the current position of the crankshaft to the CPU 60 using these two signals. The CPU 60 calculates the engine rotation speed using this position information and the timer section 62. Analog voltage signals input from the intake air amount sensor 1, intake air temperature sensor 2, engine coolant temperature sensor 3, atmospheric pressure sensor 20, diaphragm room pressure sensor 21, and battery 19 are A/D converted at the analog input port 65, and then converted to DMA. The control unit 66 performs DMA transfer to the RAM 70. Therefore,
In this example, the CPU 60 is not directly involved in A/D conversion, and can utilize the latest data required by accessing a predetermined address in the RAM 70 when necessary for calculation. The digital input port 64 receives a signal from the starter switch 22 indicating that the starter for starting the engine is in operation, and signals from other parameter setting switches 73 installed in the computer, such as a fixed advance angle switch. ing. Based on the program stored in the ROM 71, the CPU 60 calculates the ignition timing and coil energization start timing (energization time) in synchronization with the engine crank position, and based on the results, energizes the energization ignition control section 69 and provides ignition position data. Output. The energization ignition control section 69 outputs ON and OFF signals to the igniter 8 as shown in FIG. 3i in accordance with this data and the crank angle signal. In this example, since the so-called dayless double coil method is used, which does not require distribution of high voltage for ignition, the coil B signal 80 is sent to the first igniter 80 for the first and fourth cylinders among the four cylinders, and the coil B signal 80 is sent to the first igniter 80 for the second and third cylinders. Coil A to 2 igniter 81
It is designed to output a signal. Also, CPU6
0 is the current (actual) EGR determined from the target optimal EGR rate calculated in synchronization with time, the diaphragm chamber pressure PD of the second EGR valve 9, and the atmospheric pressure PA.
for EGR (control of second valve 9) according to the rate.
EGR signal to turn on and off VSV12 and VSV15 for controlling air bleed 14.
It outputs to a VSV drive circuit 68 and an air bleed VSV drive circuit 67, respectively. Interrupt control circuit 63
is for generating an interrupt signal to realize crank angle synchronization and time synchronization processing.
72 is a common bus used for information transfer between the CPU and each of the above circuit sections. Furthermore, in this system,
By using the DMA control unit 66 and connecting the operation (front) panel 17 as necessary,
Writing data to RAM70, ROM71, RAM
70 data can be read. Further, the state of the CPU (RUN, HOLD) can be controlled from the front panel 17. More detailed contents of the above-mentioned circuit section will be sequentially explained below. A detailed circuit diagram of the crank angle counter section 61 is shown in FIG. The crank angle counter section 61 uses two signals 5a and 5b generated by the sensors 50 and 51 of the rotation sensor 5 attached to the shaft of the normal distributor 4, which rotates once every two revolutions of the crankshaft of the engine. This shows the current position in decimal notation. The crank angle signal 5b of the rotation sensor 5 is shaped by low-pass filters 106, 107, a transistor 109, and a semiconductor input NAND element 111, and is shaped by a D-type flip-flop 114 (for example, manufactured by TI).
SN74LS74). flipflop 1
14 is for preventing the contents of the counter 125 from changing due to count-up during data transfer by the crank angle READ command from the CPU 60. During the crank angle READ (signal terminal 401 is logic "0"), the crank angle signal is 5b's input clock 400 is stopped by the AND element 113. The Q output of flip-flop 114 is synchronous.
4bit counter 125 (for example, manufactured by RCA)
CD4520B) is input to the CK (clock) terminal. This counter 125 is a 2-bit counter in the ternary part and a 2-bit counter in the quaternary part by the NAND gate 12.
8,124 connected in series, total (3
×4=) Operates as a decimal counter. The contents of counter 125 correspond to the position of the crankshaft and are counted up at each trailing edge of crank angle signal 51. A crank angle READ command from the CPU 60 causes the contents of the counter 125 to be changed to the buffer 126 (for example, manufactured by TI).
SN74LS244) is output to the data bus 404. The TDC signal 5a of the sensor 50 of the rotation sensor 5 is the TDC of the #1 and #4 cylinders of the crankshaft.
This is a signal indicating the position, and one pulse is output as shown in Fig. 3a every time the crankshaft passes the top dead center of the #1 and #4 cylinders. This TDC
Similar to the crank angle signal 5b, the signal 5a is connected to the resistor 1.
00, capacitor 101, transistor 103,
The waveform is shaped by the Schmitt input NAND element 105, and the D-type flip-flop 118 (for example
It is input to the D (data input) terminal of the RCA CD4013B). A crank angle signal is input to the CK terminal 1 of the flip-flop 118, and the Q output is connected to the D terminal of the D-type flip-flop 119. Therefore, at the trailing edge of the first crank angle signal after the TDC signal 5a is inverted to logic "1", the NAND element 121 of the flip-flops 119 and 120 generates one pulse (the pulse width is equal to the CK2 signal 4).
(determined by the frequency of 07), and counter 1
25 (counter contents = “0000”). In other words, TDC corresponds to "0000" and crank angle 90°CA corresponds to "0100". counter 1
25 is also performed from the T.RESET signal 402, which is a system initialization signal, and the RESET command 406 from the CPU 60. In the circuit diagrams from Figures 4 to 13, the ones marked with an * are TTL logic elements, and the other logic elements are C-MOS.
It uses logic elements. This is because the CPU60 operates at high speed, so the interface is C-MOS.
This is because it is not possible due to time constraints. Next, the timer section 62 will be explained with reference to FIG. A clock CK ₁ with a frequency of 3 MHz supplied from the CPU 60 via the terminal 400 is divided by three by the D-type flip-flops 200 and 201.
This clock CK ₂ is further supplied to a 4-bit counter 202, divided by 8, and then sent to an 8-bit counter 208.
supplied as a clock. 8bit counter 20
7,208 constitutes a 16-bit real-time timer, which counts time from 0 to 524280 μs. This timer is activated by the 8-bit latch 209, 210 by the leading edge of the crank angle pulse of the crank angle counter section 61 through the terminal 403.
(For example, RCA CD4508B) at that time is latched. The latched time is transferred to the CPU 60 through the buffers 211, 212 and the data bus 404 in response to a timer READ command sent from the CPU 60 through the terminal 408. Flip-flops 204 and 205 output a 2 μs wide latch strobe pulse at the leading edge of the signal at terminal 403. 3 input AND206
This is to prevent the count-up time and time latch time of the 16-bit timers 207 and 208 from overlapping, and when the LSB output of the counter 202 is "0", the latch timing is delayed by a maximum of 1 μs. Next, the interrupt control section 63 will be explained with reference to FIG. First, every time a crank angle signal is input from terminal 403, a gear interrupt flag (D-type flip-flop)
302 is set to "1", and an interrupt request signal is output to the CPU 60 through the inverter buffer 306 and the terminal 444. When this interrupt is accepted, the gear interrupt flag is sent from the CPU 60 through the terminal 440 by the gear interrupt processing program described later.
will be reset. Similarly, when the program interrupt port is set to "1" during the gear interrupt program, the program interrupt flag (D flip-flop) 301 is set through the terminal 441, and an interrupt request is sent to the CPU 60. This flag is also reset through the terminal 442 by a command from the CPU 60.
Furthermore, the 16 bit timer 207 of the timer section 62,
208 through terminal 415
The 8.192ms clock sets the 8ms interrupt flag (CD type flip-flop), and the
An interrupt request is transmitted to the CPU 60. That is, this interrupt occurs every 8.192ms and is used as a time base for the software. This interrupt also
It is reset by an instruction from the CPU 60. Next, the DMA control section 66 is shown in FIGS. 7 and 10. Terminals 409, 410, 411, 412, 41
3 is a HOLD request signal (terminal 437) for the CPU 60 to temporarily stop program execution.
The output signal from the timer section 62 shown in FIG. 5 is inputted thereto. of the timer section 62
Bit 2 (terminal 413) and bit 3 (terminal 41) of the 16-bit real-time timers 207 and 208
2) are both "1", the output of the AND gate 603 becomes "1". That is, the waveform becomes as shown in FIG. 8O. Similarly, the output of the 3-input AND 605 is as shown in FIG. 8P. In addition, 618
~622, 644~646 are resistors for CMOS input protection. The DMA shown in this example has 8 channels, and all channels are connected every 1 ms.
Transfers data between RAMs 70. The first 7 channels out of 8 channels (CH0 in O in Figure 8)
-6) are for transferring A/D converted data, and the last channel CH7 is used for data transfer with the operation panel 17. In the case of A/D converted data, A/D conversion is performed in the first 96 μsec and the data is transferred in the next 32 μsec, as shown in FIG. 8O. AND gate 60
3 becomes "1", if there is no external HOLD request signal from the operation panel 17 to the computer (terminal 427 is "1"), the output of AND gate 605 becomes "0" (therefore, the output of 608 becomes "0"). 1”), so register 624 (for example, 74LS175 manufactured by TI)
The D input of becomes "1". CK of register 624
For input, 3MHz clock from CPU60 is connected to terminal 4.
26. Immediately after the D input of the register 624 changes to “1”, the register 624
Since the Q output of 4 is “0”, AND gate 6
The output of NAND gate 601 becomes “0”, the output of NAND gate 601 becomes “1”, and 3M is input to the CK input of register 624.
The Hz clock is added as is, and the D input of register 624 changes to "1" at the next clock.
is stored in the register 624, and the Q output becomes "1" as shown in FIG. 8q. When the Q output of 624 becomes "1", the output of AND gate 642 changes to "1", and the output of tri-state output NAND gate 643 (for example, 74LS38 manufactured by TI) becomes "0", which causes the CPU 60 to Outputs a HOLD request signal (“0”) for starting DMA. (See Figure 8 t) The CPU 60 receives this signal from the terminal 431.
The HOLD request signal is sent to the receiving terminal 425 after the end of the machine cycle currently being executed.
Outputs signal “1”. (Figure 8 u). terminal 437
is “0” and the HOLD request signal is output.
Until the HOLDA terminal 425 signal becomes “1”
3MHz because the output of NAND gate 601 is “0”
The clock (terminal 426) is the CK of register 625.
Not supplied to terminal. When HOLDA becomes "1", a clock is input to the CK terminal of the register 625, "1" is taken into the register 625, and the Q output becomes "1". Further, at the next clock, the Q output of the register 626 becomes "1", and at the next clock, the output of the register 627 becomes "0". When the output of the register 627 becomes "0", the output of the NAND gate 643 becomes "high impedance",
The HOLD request is released and the DMA cycle is completed. When the HOLDA signal becomes "1", the AND gate 638 becomes "1" and the tri-state output
The output of the NAND gate 641 becomes "0" only while the HOLD request signal is "0" and the HOLDA signal is "1", and as shown in FIG.
Memory use selection signal to 0 (, 436)
issue. Furthermore, only when the Q output of the register 625 is "1" and the output of the register 626 is "1", the AND gate 639 becomes "1", and while CH0 to CH6 are selected, the output of the 3-input AND gate 605 is Since it is “0”, the output of the inverter 612 is “1”, and the tristate NAND gate 64
0 is the memory RAM7 as shown in Figure 8 w.
The WRiTE signal (, terminal 435) to 0 is output. In addition, while the memory use selection signal is "0", the output of the NAND gate 628, that is, the READ signal to the memory (DBiN, terminal 43
1) is “0”. While the HOLDA signal is "1" (during a DMA cycle), the CPU 60 is stopped, and the drives from the CPU side of control lines such as , DBiN, address bus, and data bus are in a "high impedance" state. Therefore, during this period, data is transferred directly from the DMA control unit 66 to the RAM 70. A/D of CH0~CH6
In the case of transfer of conversion data, the output of the inverter 606 is “1” and the output of the inverter 606 is “1”, and the output of the inverter 606 is “1”,
The output of the gate 629 is a signal similar to that shown in FIG.
D conversion data registers 518 and 519 are added to strobe inputs 1 and 2 of A/D conversion address registers 530 and 531 in FIG. In other words, the A/D converted data is output on the data bus 404 during the period when the
Addresses corresponding to CH0 to CH6 are output onto address bus 440. The data output on these buses is written into the RAM 70 by signals. CH0 when there is an external HOLD request signal (terminal 427) from the operation panel 17 (“1”)
~CH6 A/D conversion DMA cycle is not performed. In other words, the output of the NAND gate 607 becomes "0" and the output of the AND gate 603 becomes "1".
Even so, the D input of register 624 remains in the "0" state, so the DMA cycle is not started. Next, the operation (front) panel 17 and RAM 7
The DMA cycle of CH7 that performs data transfer with 0 will be explained. Terminal 428 is an R/W signal from the front panel, terminal 429 is a data transfer request signal,
Terminal 430 is a continuous READ signal, and terminal 414 is a 128 ms clock signal supplied from timer section 62. First, when a data write request occurs from the operation panel 17 to the RAM 70, the terminals 428, 4
29,430 becomes "0". AND gate 60
The outputs of 5 and 603 become "1" (O, P in FIG. 8), and the DMA cycle of CH7 is started. The registers 615 and 616 set the terminal 429 to “1”.
One positive pulse with a width of 10 ms is generated at the output of the AND gate 617 at the rise from to "0".
This pulse becomes a 128μs negative polarity pulse at the NAND gate 609, and the NAND608, AND604
The signal is then input to the D input of the register 624 as a 32 μs positive pulse. From the operation panel 17
In the case of a WRITE request to RAM70,
Each of the control lines HOLDA, . (Fig. 8 t to w) Furthermore, for the operation (front) panel 17, the RAM
During the period when the signal terminals 434 and 432, which output the contents of the register storing the address and data to be transferred to the address bus and the data bus respectively, are "0", the polarity is positive as shown in FIG. 8x. outputs a pulse of When a data read request is received from the operation panel 17 to the RAM 70 or ROM 71, the terminal 42
9,430 becomes "0" and 428 becomes "1". In the DMA cycle in this case, the signal (terminal 435) on the computer control line is set to "0" as the memory use selection signal (terminal 436).
Instead of remaining “1” for a period of time,
Since the output of AND gate 611 is “1”,
The DBiN signal (terminal 431) is "1". The other control lines HOLDA, . . . are the same as the A/D conversion data transfer cycle and the data write cycle from the front panel. When the continuous READ signal (terminal 430) is "1", the output of the NAND 613 generates a 128 ms clock. This is NAND gate 614
From front panel 17 every 128ms
This is equivalent to a data read request to RAM70 and ROM71, so once every 128ms, RAM70 and ROM
A DMA data transfer cycle from 71 to front panel 17 occurs as described above. Incidentally, the DMA cycle from the front panel 17 is executed even if there is an external HOLD request signal (terminal 427). Next, the analog input port 65 will be explained with reference to FIG. Filters 500 to 513 made of resistors and capacitors connected immediately after the input terminals 1 to 3 and 19 to 21 of each sensor are for removing noise components superimposed on the signal line. The six sensor inputs are connected to an eight-channel multiplexer 514 (e.g. CD4051B).
are connected to inputs C0 to C5, respectively, and one of the inputs is selected by the level of address inputs A, B, and C. That is, for example, A, B, C
When is “0”, “0”, “0”, C0 input is set,
When it is "1", "0", or "0", the C1 input is selected. The address inputs A, B, and C of the multiplexer 514 pass through a level converter (for example, CD40109B) 515 and are connected to the real-time timer 2 of the timer section 62.
It is connected to 07,208. Therefore,
The selected channels are switched in the order C0→C1→C2→...C0 every 128 μs, and one channel is selected once every 1 ms. Terminal 421 is also connected to real time timers 207 and 208 and generates a 64 μs clock. That is, at the same time as the address of multiplexer 514 is switched, terminal 412 rises from "0" to "1". At that time, inverters 520, 524,
NAND element 523, resistor 521, capacitor 52
2, an A/D start pulse of several μs is generated, and the sequential comparison type A/D converter 517 (e.g.
It is input to the CONV/CMD terminal of Bur Brown's ADC80AG) and A/D conversion begins. One input selected according to the values of address inputs A, B, and C is output as is to the output of the multiplexer 514, and the operational amplifier 516 (for example, NEC μ
After current amplification by the PC 151A), the current is input to the analog input terminal of the A/D converter 517. A/D
After the conversion start signal is applied to the CON/CMD terminal, the converter 517 converts the analog input into 12-bit digital data in about 40 μs,
Output to B0 to B11. The converted digital data is transferred to buffers 518, 519 of 12 bit data of B0 to B11 at the address corresponding to the selected channel of P.AM 70 in a DMA data transfer cycle starting 96 μs after application of the conversion start signal by the DMA control unit 66. written through. Next, the energization ignition control section 69 will be explained in detail with reference to FIGS. 11, 12, and 3. The CPU 60 calculates the current position of the crankshaft by using information from the crank angle counter 61 and an interrupt (gear interrupt) that occurs every time a crank angle signal is input.
It is recognized with the accuracy of CA). How to achieve the optimal energization timing and ignition timing calculated by the program will be explained for the #1 and #4 cylinders. The same explanation can be given for #2 and #3 cylinders.
First, regarding energization, the optimum energization angle θ is decomposed as shown in the following equation.

[Table] θ: Energization angle θ ₁ : Crank angle at which energization starts that can be recognized by the CPU in units of 30° CA (0 to 11 (30° CA), corresponding to each gear position of the rotation angle sensor 5) θ ₂ : 30° CA or less Fraction τ: The fraction θ ₂ less than 30° CA is converted into time in units of 8 μs based on the rotation speed N at that time.Then, the gear position one position before the gear position θ ₁ calculated by the above formula When the gear interrupt occurs at (θ ₁ -1), the CPU 60 outputs the #1 and #4 coil energization command (terminal 453) and the energization down counter value set command (terminal 450) as shown in FIG. 3C. The applied pulse is inverted by an inverter 908 and the flip-flop 90
Set 9. Also, the pulse applied to terminal 450 causes data bus 404 to be simultaneously
The contents of i output from CPU are set in 16-bit energization down counters 900 and 901. 90
0 and 901 are each connected in series with an 8-bit down counter (for example, RCA CD40103B).
It constitutes a 16bit down counter. This 16bit
The down count value is 0 to 8 μs precision.
A value of 0.52428sec is possible. Therefore 3rpm
It is possible to count down to a certain number of rotations without overflow. When flip-flop 909 is set, the output becomes “0”.
The output of the NAND gate 910, that is, the D input of the D-type flip-flop 911 becomes "1". Since the CK (clock) input of the flip-flop 911 is connected to the crank angle signal through the terminal 403, the flip-flop 911 is set at the next crank angle pulse after the #1 and #4 coil energization command and the energization down counter value set command are output. be done. FIG. 3d shows the signal waveform of the Q output of flip-flop 911. When the flip-flop 911 is set, the output becomes "0", so the down counters 900 and 901 can count down, and since the reset input of the 4-bit frequency divider 925 is released, the CK of the down counters 900 and 901 is reset.
A down-count clock is supplied to the input, and down-down is started. Frequency divider 925 (e.g.
RCA CD4520B) is 2 μs from the 4-bit down counter 202 of the timer section 62 via the terminal 455.
clock is supplied, and the frequency is divided by 4 to 8μ.
s down count clock is generated.
Directly from real time timer 207, 208 8
The reason why a μs clock is not used is to ensure accuracy, especially when τ=0, 1. Now, 16bit down counter 900,901
When the down counter ends, the end signal “0” is output from the CO/ZD terminal of the down counter 900, and the inverter 904 and the AND gate 90
6. Pass through the NAND gate 915 to reset the flip-flops 909 and 911 (see Figure 3 d), and further pass through the inverter 914 to reset the down counters 900 and 901, so CO/ZD
The terminal returns to "1" again. Therefore, the output of AND gate 906, ie, terminal 456, becomes a negative pulse as shown in FIG. 3l. Further, since the output of the flip-flop 911 becomes "1", the counting of the down counters 900 and 901 is stopped, and the supply of the count down clock is also stopped. Note that the down count clock is connected to the other input of the AND gate 906 by the inverter 9.
05 is applied, and the output of the AND gate 906 becomes "1" 4 μs later than the down count end signal. This occurs immediately after the countdown clock is applied, when the down counter 900
This is to prevent malfunctions caused by negative pulses (about 200ns) that may occur at the CO/ZD terminal. The output pulse of AND gate 906 is passed through terminal 456 to AND gate 93 in FIG.
Add to 3,935. Now, the Q output of the flip-flop 909 in FIG. 11 is "1" until the R (reset) input is inverted to "1", and the Q output of the flip-flop 909 in FIG.
The input of AND gate 933 is via terminal 457.
Since it is connected to the Q output of flip-flop 909, the output of AND gate 933 is connected to terminal 456.
The pulses applied to the #1 and #4 coils (coil B) control flip-flop 938 are set. When the output of the inverter buffer 938 changes to "1", the output of the inverter buffer 939 becomes "0", so the transistors 942 and 947 change to "1".
OFF, the transistor 952 turns ON, and current flows between the input terminal of the first igniter 80 and the IGGND terminal 82, and the coils for the #1 and #4 cylinders start energizing. Note that the diodes 948 and 953 are for transistor protection, and the resistors 940, 941, 943 to
946,949 to 951,954 are solid resistors for attenuating ignition noise. Figure 11
One input of NAND gate 907 is frequency divider 925
It is connected to a terminal that supplies a 2 μs clock. Therefore, even if the output of the AND gate 906 changes to "1", the down counters 900, 9
01, flip-flops 909 and 911 are reset with a delay of 2 μs. This is to ensure the pulse width of the set pulse of flip-flop 938. The ignition angle (timing) θ _B x is also decomposed in the same manner as in equation (1).

[Table] θ _BX : Ignition angle of #1 and 4 coils (coil B) θ _BX1 : Ignition crank angle that can be recognized by CPu in 30° CA units, (0 to 11 x 30° CA) θ _B x ₂ : 30° Fraction τ _x below CA: 30° Fraction θ _Bx below CA is converted into time in units of 8 μs based on the rotational speed N at that time. The crank angle signal of the rotation sensor 5 (sensor 51) that is generated when the engine crankshaft reaches the gear position (θ _{BX −1} ) one position before the gear position (θ _B x 1 ) calculated by equation (2) CPU60 issues an ignition command (terminal 45) due to the gear interrupt caused by the rising edge of
4. Output the signal f in FIG. 3 and set τx in the 16-bit ignition down counters 902 and 903. When the crankshaft position reaches θ _B x ₁ , flip-flop 922 is set. The 16-bit down counters 902 and 903 start counting down with an 8 μs clock, and at the same time as the down counting ends, a positive pulse as shown in FIG.
Occurs on 9th. FIG. 3g is a flip-flop 922
This is the waveform of the Q output of , and becomes "1" only during down-counting. The A and B inputs of the decoder 930 (for example, RCA CD4556B) shown in FIG. 12 are connected to the counter 1 of the crank angle counter section 61 shown in FIG.
Terminal 40 is connected to the upper two bits (bits 2 and 3) of 25.
5. Therefore, when the crank angle is 0~90°CA, 270~360°CA), NAND
The output of the gate 931 becomes "1", and the output of the NAND gate 932 becomes "1" when the angle is 90 to 270 degrees CA.
The ignition crank angle for #1 and 4 cylinders is usually 290 to 360°.
It is CA, and the ignition crank angle of #2 and 3 cylinders is 110
゜～180゜CA. Therefore, as for ignition, even if there is no identification signal from the CPU, it is possible to determine which coil the ignition command is for as long as the crank angle is known, as described above. Well, in this case
The output of NAND gate 931 becomes “1”
A pulse from terminal 459 is generated at the output of AND gate 934, resetting flip-flop 938, and the output changes to "1" as shown in FIG. 3i. Therefore, transistors 942 and 947
ON, the transistor 952 turns OFF, the current flowing between the input terminal of the first igniter 80 and the GND terminal 82 is cut off, and high pressure is generated in the spark plug of either #1 or #4 cylinder that is in the compression process. Then, ignition takes place. The coil B igniter signals for the #1 and #4 cylinders have been described above, but the coil A igniter signals for the #2 and #3 cylinders are also controlled in exactly the same manner. Next, the 13th section regarding the EGR-VSV drive circuit 68.
This will be explained in detail with reference to the drawings. CPU60 uses VSV12 for EGR control by its built-in program which will be described later.
When it is determined that the switch should be turned on, it outputs "0" to the terminal 470. Then the transistor 802,
806 turns ON, and coil excitation current flows between the EGRVSV12 terminal and battery GND terminal 19.
The EGR control VSV12 is turned on. On the contrary, CPu60
outputs “1” to terminal 470, transistors 802 and 806 turn off, and EGRVSV12
No current flows between the terminal and the battery GND terminal 19, and the EGR control VSV 12 is turned off. The air bleed VSV drive circuit 67 is exactly the same as that shown in FIG. 13, and turns the air bleed control VSV 15 ON and OFF with the outputs of "0" and "1" from the CPU 60. This completes the explanation of the hardware of the system that represents an example of the present invention, and the control algorithm, ie, software, will be explained below. The example system has three interrupts, each with its own priority. This is shown in FIG. The three interrupts are gear interrupt, program interrupt, and 8ms interrupt in descending order of priority level. The main routine is executed when these interrupts are not being processed. Intake air amount Ga, water temperature Tw, intake temperature Ta, diaphragm room pressure P _D , atmospheric pressure P _A , battery voltage V
For _B , after A/D conversion, each
The CPU 60 is stopped for several microseconds once every 1 ms, and during that time, the data is directly transferred to a predetermined memory address in the RAM 70 by the DMA control unit. Therefore, the program is not involved in A/D conversion at all, and only needs to access a predetermined address when the above data is needed. Each program will be explained in turn below. First, the flowchart of the main routine that is executed when there is no interrupt is shown in Fig. 15.
As shown in the figure. The main routine is started by turning on the power of the computer 6 or pressing the RESET switch on the front panel 17, and in step 1001 initializes the program (clears RAM, sets predetermined values for parameters, etc.)
(e.g. permission of each interrupt) is executed. Next, in step 1002, base processing, detailed in FIG. 16, is executed. A/D in base processing
Cooling water temperature Tw, intake temperature based on the converted data
Ta is linearly interpolated from the one-dimensional map and step 1
020, 1023, step 1021, 1022
Linear interpolation is performed using a one-dimensional map from the cooling water temperature Tw, and the water temperature advance angle θTw and the EGR water temperature correction coefficient KTw are
is calculated. Further, in step 1026, the acceleration advance angle coefficient γACC is calculated using equation (3), where γAcc=CAccX(80−Tw)−(3) CAcc: a constant. Similarly, in step 1024, the EGR intake temperature correction coefficient KT _A is calculated from the intake air temperature T _A by linear interpolation using a one-dimensional map, and in step 1025, the EGR atmospheric pressure correction coefficient K _P is calculated from the A/D conversion data of the atmospheric pressure P _A. Linear interpolation calculations are performed using a one-dimensional map. After executing the base processing, the main routine advances to condition determination step 1003. This step 1
At step 003, it is checked whether the flag _f8 is 0. If it is 0, the process returns to the base processing step 1002, and if it is not 0, the process proceeds to step 1004. This flag _f8 is incremented by 1 at the 8 ms interrupt shown in FIG. 29, and decremented by 1 each time the 8 ms processing step 1005 is executed in the main routine. Therefore, the 8ms processing step 1005 is normally executed once every 8ms.
Details of the 8ms processing are shown in FIG. Step 10
The required energization time τON is determined from the A/D converted battery voltage _VB at 30 by linear interpolation calculation using a one-dimensional map. At step 1031, the flag 50 is incremented by one. After completing the 8ms processing step 1005, the main routine proceeds to decision step 1006. In step 1006, if flag 50 is 6 or more, step 1007 is executed.
6 is subtracted, followed by 50ms processing step 1
008 is executed. If 50 is less than or equal to 5, the process returns to step 1003. Usually 80ms (6× to be exact)
This 50ms is executed once every 8,192=49.152ms)
Processing step 1008 is illustrated in FIG. Steps 1040 to 46 show calculation of the acceleration advance angle. Acceleration detection is performed using equation (4), △Ga/N = (Ga/N) ₀ - (Ga/N) ₅₀₀ - (4) Ga: intake air amount, N: rotational speed, and the current (Da/N) In step 1040, the difference between 0 and data (Ga/N) 500 500 ms ago is determined, and in step 1041, acceleration is determined based on whether the difference is greater than a certain value C. If it is determined that acceleration is occurring, θAcc' = γAcc x △Ga/N - (5) γAcc: see equation (3) At step 1043, a new acceleration advance angle θAcc is calculated using equation (5). The acceleration advance angle θAcc increases by a certain angle (0.1 to 1°) every rotation after acceleration is detected.
CA) It will be delayed. Therefore, step 104
In step 5, the larger of the current acceleration advance value θAcc and the acceleration advance value θAcc' newly calculated by acceleration detection is set as the new θAcc. Also, if deceleration is detected in step 1042 (step 1042) θ
Acc becomes 0 immediately. Steps 1047-10
51 is an EGR processing step. Shown in this example
As mentioned above, the EGR control method sets the pressure in the diaphragm chamber 91 of the second EGR valve 9 in Fig. 1 to a negative pressure corresponding to the optimum EGR rate determined by the rotation speed N and the intake air amount Ga/N per rotation. This is a method of controlling the list of valves 92 and obtaining the optimum EGR rate. Optimal at step 1047
Negative pressure Pdref corresponding to the EGR rate is calculated using equation (6). Pdref= A+KTw×KTa×Kp×(Pdmap−
A)-(6) Pdmap: Value obtained from (N, Ga/N) by 4-point linear interpolation calculation using a three-dimensional map (negative pressure) KTw: EGR water temperature correction coefficient (see Figure 16) KTa: EGR intake temperature Correction coefficient (see Figure 16) Kp: EGR atmospheric pressure correction coefficient (see Figure 16) A: Preset pressure, pressure in the diaphragm chamber (91 in Figure 1) moves the valve 92 against the repulsive force of the spring 93. Critical pressure to start. Furthermore, the current value Pdreal of the diaphragm chamber pressure (negative pressure) of the EGR second valve 9 is determined in step 1048 (7).
Calculated by the formula. Pdreal=P _A - P _D - (7) P _A : Atmospheric pressure (absolute pressure) P _D : Diaphragm chamber pressure (absolute pressure) In the following steps, the actual diaphragm chamber pressure
The VSV 12 in FIG. 1 is controlled ON and OFF so that Pdreal matches the optimal control value Pdref. That is, if the actual diaphragm chamber pressure Pdreal is smaller than the control value Pdref in step 1049, the EGR VSV12 is activated.
ON, regulated manifold negative pressure is introduced to increase Pdreal, and vice versa.
When it becomes larger than Pdref, VSV is turned off, atmospheric pressure is introduced, and Pdreal is reduced. Next step 1
At 052, the diaphragm chamber pressure Pdreal is determined according to equation (8).
The EGR advance angle value θEGR is calculated from . θEGR=CθEGR×(Pdreal-A) -(8) (However, if Pdreal-A<0, θEGR=0) CθEGR: Constant A: Preset pressure Step 1053 and below are the program steps for controlling the air bleed VSV15 in Figure 1. show. In this case, the higher the EGR rate, the higher the VSV15.
The OFF period becomes longer, the amount of air in the air bleed 14 decreases, and the air-fuel ratio (A/F) is controlled to become smaller. In this case, in step 1053, the target ON-OFF duty ratio Dref of the air bleed VSV 15 is first calculated using equation (9). Dref=CDREF×(Pdreal-A) −(9) (However, if Pdreal-A<0, Dref=0) CDREF: Constant A: Preset pressure 16 bits stored at a predetermined address in RAM 70
Memory contents Each bit of Hair is the past 16 ONs (“1”) of Air Bleed VSV in order from the highest bit to the oldest bit,
Indicates the history of OFF (“0”). NON represents the number of ON (“1”) times in the past 16 history. Therefore, the current duty ratio Dreal is determined by the judgment step 1.
The expected value of this judgment in 057 is both ON and OFF.
Assuming 1/2, it can be calculated as shown in step 1056. To find the latest value of NON, shift Hair by 1 bit to the left, check the oldest bit, subtract 1 if it is "1", and leave it as is if it is "0" (steps 1053 to 1055). EGRVSV12
As with the control of the current duty ratio
If Dreal is smaller than the control target value Dref, turn on the air bleed VSV15 to increase Dreal (step 1059), and in step 1060 set NON to 1.
Increase the latest bit of Hair to 1.
Conversely, if Dreal is larger than Dref, turn off VSV.
Make Dreal smaller. (Step 1058). Therefore, the air-fuel ratio of the mixture supplied to the engine is
It is controlled to a value set according to the amount of EGR. In this example, the ON/OFF duty ratio of the air bleed VSV15 is calculated and the VSV ON/OFF is directly controlled by the CPU, compared to the normal method of controlling the duty ratio using a down counter as shown in Figure 31. Therefore, the hardware (circuit) becomes small-scale, and if the duty ratio control cycles (control periods) of the solenoid valves are selected in the same way, the responsiveness is also improved. In particular, in this example, the current duty ratio is calculated from the history of the past 16 times, and the sample for calculating the duty ratio always uses the latest value for calculations every 50ms. For example, 800ms (50ms x 16)
The response is much better than the method of calculating the target duty ratio only once per month and executing the ON/OFF sequence based on it every 50ms.
This concludes the explanation of the processing program related to EGR, and the gear interrupt and program interrupt will be explained below. First, the gear interrupt will be explained with reference to FIG. Gear interrupts have the highest priority and are processed with the highest priority. Activation of this gear interrupt is performed by a crank angle pulse from the terminal 44 of the interrupt control section 63 shown in FIG. 6 mentioned above. Therefore, the gear interrupt is activated every 30°CA from TDC. When activated, the gear interrupt is reset in step 1100 (resetting the flip-flop 302 in FIG. 6), and the real-time timer 20 is activated by the crank angle pulse in the timer section 62 shown in FIG.
The wrap values latched in the registers 209 and 210 from 7 and 208 are read into the CPU 60. By this operation, the CPU 60 can detect the exact time when the crank angle pulse occurs with an accuracy of 8 μs, and can detect the passing time of the crank position every 30° CA. Further, by the READ operation of the crank angle counter 125 of the crank angle counter section 61 shown in FIG. 4, the CPU 60 can detect the current crank position with an accuracy of 30° CA. However, the current value of the crank position described below is the value obtained by adding 1 to this value. Step 1101 is the first step for energizing ignition processing.
Two calculated value storage table iGT shown in table
This is a judgment step for selecting the newer one among 1 and iGT2. Flag _TAB is “0”
If it is, table iGT1, and if it is not "0", it indicates that table iGT2 is the latest table.

【table】

【table】

【table】

[Table] The calculated value storage table iGT whose contents are shown in Table 1 is calculated by a program interrupt described later. Therefore, a gear interrupt may occur during each data update of table iGT.
Two sets of iGT have been secured: iGT ₁ and iGT ₂ . Current ignition processing step 110 using table iGT1
2 is shown in Figures 20 and 21. The energization ignition processing step 1103 using table iGT2 is also the same as step 1102 except that the data used is table iGT2 instead of table iGT1. The energization ignition process will be explained below with reference to FIGS. 20 and 21. First, in step 1110, the state of coil A (ignition coil for #2 and #3 cylinders) of the ignition coils 7 is checked. Coil A state S _A is 1 of coil control table CCT shown in Table 2.
There are two flags: “0” is before energizing, “2” is when energizing,
“4” represents after ignition. That is, gear position 11 of fixed position processing step 1104 shown in Table 3
(ATDC300°CA with respect to TDC of coil B) S _A
is set to “0” in coil A energization ON processing step 111
2 to “2” Coil A ignition processing step 1123
is set to "4". When coil A state S _A is “0” and is not energized, the latest value θ ₁ of the energized gear position calculated by the program interrupt described later and the current value of coil A (#2, 3 cylinders) with respect to TDC (top dead center) The gear position _A of is compared in step 1111, and if _A ≧ θ ₁ , the process proceeds to step 1112 for coil A energization ON processing, and if _A has not reached the energized gear position, the process proceeds to the processing routine for coil B shown in Fig. 21. . Coil A energization ON processing step 11
12 is shown in FIG. _A at step 1140
> θ ₁ or _A = θ ₁ . _A > θ ₁ is established when the latest value of the energized gear position is earlier than the previous value, such as during acceleration, when the ignition angle θx is greatly advanced, or when the battery voltage suddenly decreases. be. At this time, the current position has already passed the position where the current should be applied, so steps 1142 and 11 are performed.
44, the first coil A is energized at step 1144 with the next crank angle pulse.
The energization down counters 900 and 901 in FIG. 1 are set to "0", and a coil A energization command is output in step 1145. In the normal case where _A = θ ₁ is established, the process proceeds to step 1143, sets the calculated value τ in the energization down counter, and returns to step 1.
At 145, a coil A energization command is output. Then, as described above in the explanation of the circuit operation in Fig. 11, after the down count starts with the next crank angle pulse, the coil A igniter signal is reversed from "1" to "0" as shown in Fig. 3 i. . The coil A energization angle θ _A set in steps 1141 and 1142 represents the latest crank angle at which energization actually started, and is used in the following steps. At step 1146, the aforementioned coil A state S _A is set to "2". Further step 1113
The coil A ignition calculation flag _A is set to "0". This flag _A is set at program interrupt in order to prevent misfires and secure the power ON time.
This flag requests that the ignition angle θx calculated in the ESA calculation step be corrected and calculated using the crank angle _θA at which energization actually started. The request for correction calculation, that is, flag _A , occurs at the start of energization described above and at the time described below.
Set to “0” immediately after execution of ESA calculation.
Next, if the coil A status S _A is "2", that is, it is energized, the process proceeds to step 1114, and it is determined whether the gear position is where ignition processing is performed. Make sure to set the ignition advance angle
Since BTDC is within the range of 0 to 70° CA, coil A ignition processing is performed at gear positions 9 to 11 (i.e., assuming #2 and 3 cylinder TDC is 0° CA, BTDC is 30°, 60°, 90°).
゜CA) is sufficient. Therefore, in this example, θOFF=9. If the current position A of coil _A ≧θOFF is satisfied in step 1114, the process proceeds to step 1115; otherwise, the process proceeds to the processing routine for coil B in FIG. 21. If the coil A ignition calculation flag _A is "0" in step 1115, the aforementioned correction calculation of the ignition angle θx is executed. First step 1
116, the actual energization angle θ _A and the allowable minimum dwell angle calculated from the program interrupt (the minimum energization time required for normal combustion of the engine, converted into a crank angle based on the rotational speed at that time)
From θ'ON, the maximum allowable advance ignition angle in terms of the current-on time is calculated as θ _A x. This value and the optimum ignition angle θx calculated in the ESA calculation step of the program interrupt are compared in step 1119, and θx
If ≦θ _A x, θ _A x, and if θx>θ _A x, θx is rewritten as the actual coil A control ignition angle θ _A x in the coil control table CCT shown in Table 2. In other words, the top priority is to prevent misfires, and if the latest value of the ignition advance is too advanced,
In order to secure the energization time, θ _A x calculated in step 1116 is set as the upper limit of the advance angle. However, as shown in steps 1117 and 1118, if the maximum allowable advance ignition angle comes after top dead center (TDC), the top dead center (θM _A x = 360° CA) is set to the actual ignition angle θ _A x. ing. Generally, when using a computer to calculate and control ignition timing in synchronization with the crank angle, the conventional method is to control one or more energizations and ignitions with one energization ignition calculation, and to control the energization and ignition at least once during the energization ignition calculation. The timing and ignition timing were used as they were for actual control, and a new ignition timing was not calculated by the energization ignition calculation during energization. However, as computers become faster, it has become possible to start two or more energization ignition calculations for one ignition, especially at low engine speeds, and use the latest calculated value. In the case of controlling actual automobile engines, etc., where the rotation speed fluctuates by one order of magnitude from 600 to 6000 rpm, consider that conventionally, the energized ignition calculation was started early due to calculation time constraints for the energized ignition calculation at high rotation speeds. Therefore, the method of starting energization ignition calculation many times for one ignition and adopting the latest calculated value that is in time for actual control will greatly improve transient response during acceleration and improve drivability. Contribute to improvement. In this example, the energization ignition calculation is started four times per crank rotation, but if a faster computer is used, the crank angle pulse will be generated at 30°C.
It is also possible to perform calculations for each A. Although not mentioned in this example, a method in which the energization ignition calculation is performed not in crank angle synchronization but in time synchronization (e.g., the 8ms processing step in this example) or in the main routine (e.g., EEC of the hood) can also be performed at step 1116 in Fig. 20.
It is necessary to recalculate the actual ignition timing shown in ~1121. In particular, by adopting a double coil system as in this example, the energization ON timing is doubled (0 to 360℃A) compared to the normal single coil system (0 to 180℃A).
If it can be set earlier, to take advantage of that advantage, there is a possibility that the energization ON timing and the ignition timing will be far apart.In order to reduce abnormal combustion caused by the energization time such as misfires, readjusting the ignition timing as described above is necessary. It is essential. In step 1121, the control ignition gear position θ _A x ₁ is calculated from the actual coil A control ignition angle θ _A x.
Calculated using formula (2), coil A ignition calculation flag _A
Return to “1”. The process then proceeds to step 1122. Step 111
If _A is not “0” in 5, directly proceed to this step 1.
The program moves to step 122. In step 1122, the coil A control ignition gear position θ _A x ₁ is compared with the current gear position _A. If _A ≧θ _A x ₁ , proceed to coil A ignition processing step 1123, and _A < θ _A x ₁
If so, do nothing and proceed to the processing routine for coil B in FIG. 21. A detailed flowchart of step 1123 is shown in FIG. FIG. 24 is almost the same as FIG. 22, and first, in step 1160, _A > θ _A x ₁
or _A = θ _A x ₁ . _A > θ _A x ₁ holds because the ESA calculation step ended just before this gear interrupt, the new ignition timing value became available, and the new calculated value was advanced compared to the previous calculated value. This is the case. In this case, the current position passes the gear position where ignition should be performed, so step 11
At steps 62 and 1163, the ignition down counters 902 and 903 of the energization ignition control section 69 shown in FIG. A signal is sent to the second igniter 81 of the igniter 8. If _A = θ _A x ₁ , the ignition down counters 902, 90 of the energization ignition control section 69
The ignition down counter value τx set to 3 is (2)
It is calculated in step 1161 using the equation (2A). τx are adjacent as described above. τx = τx (θ _A x - θ _A x ₁ ) - (2A) θ _A x: Coil A controlled ignition angle θ _A x ₁ : Coil A controlled ignition gear position Between the gear positions ( It is expressed as the time required from the smaller gear position to an arbitrary point at an interval of 30°C (A). At step 1163, τx is set in the ignition down counter, and at step 1164, a coil A ignition command is output. As a result, as mentioned above, the down count starts at the next crank angle pulse after the ignition command is output, and when the down count ends, the coil A igniter signal changes from "1" to "0" as shown in Figure 3i. It reverses and ignition occurs. Next, in step 1165, coil A status S _A is set to "4", and the coil A ignition processing step is completed.
This concludes the explanation of the processing routine of coil A.
The process moves to the processing routine for coil B shown in FIG.
The processing routine for coil B is also completely similar to the processing routine for coil A. Gear current position _B is #14
Since it is based on the TDC of the cylinder (coil B), it is shifted by 180°A from the current position _A , and equation (10) holds true. _B = _A + 6 (mod12) (10) The steps for turning on the current to coil B are shown in FIG. 23, and the steps for igniting the coil B are shown in FIG. 25. The above completes step 110 of energization ignition processing in gear interrupt.
After completing the explanation of step 2 and 1103, the fixed position processing step 1104 will be explained next. The fixed position processing routine, whose contents are shown in Table 3 above, calculates the rotation speed, activates a program interrupt, and calculates the ignition delay angle θ _DL.
Y , acceleration advance angle θ _ACC are calculated. The gear positions shown in Table 3 are obtained from the READ operation of the crank angle counter in step 1100, and are exactly _B of the energization ignition processing routine. Since the crank angle pulse is generated every 30°C, or 12 pulses per revolution of the crankshaft, _B takes a value from 0 to 11. Depending on the value of _B , various processes shown in Table 3 are executed. First gear position “0”
(TDC of #1, 4 cylinders) and "6" (TDC of #2, 3 cylinders), the average rotation time τm (60℃A rotation time) is the sum of the past two 30℃A rotation times described below. is required. From this τm, the ignition delay angle θ _DL
Y is determined by equation (11). This is the ignition signal delay caused by the igniter converted into a crank angle. θ _DLY = t _DLY / τm … (11) t _DLY : Delay time of ignition signal by igniter (40 to 100 μs) Furthermore, acceleration advance angle θ _ACC calculated by the 50 ms processing in Fig. 18 is a constant angle ( 0.05~0.5℃
A) Subtract or retard the angle. In this example, the rotation speed is calculated based on the time τ _N required for rotation at 30°C. The measurement interval is _B = 1~2 (30~60℃A), _B = 4~5 as shown in Table 3.
(120-150℃A), _B = 7-8 (210-240℃A),
_B = 10-11 (300-330°C A), 4 sections per revolution. However, the numbers in parentheses indicate the crank angle when the TDC of #1 and #4 cylinders is 0°C. The measurement method of this example will be explained below using rotation time measurement at 30 to 60°C as an example. The transit times t30 and t60 for gear positions 30°C and 60°C correspond to the timer latch of the first step 1100 of the gear interrupt shown in FIG.
Required with READ. Therefore, the rotation time τN can be obtained from equation (12).
However, in the normal rotation speed measurement τ _N =t60-t30 (unit: 8μs)...(12) method, the rotation time measurement timer is reset and started with a crank angle pulse at a gear position of 30℃A.
It is common to stop the timer with a crank angle pulse of 60°C, and read the contents of the timer into the CPU using a rotational speed measurement routine that is started at the same time. An example in which this method is applied to a six-cylinder engine is shown in FIG. In the example shown in FIG. 30, since the rotation time is measured at 120°C, two timer registers are required. Also, reset, start, and stop control circuits and a switching circuit for timer registers 1 and 2 are required. On the other hand, if the method of this embodiment, which has one real-time timer and latches the timer value at that time in a register using a crank angle pulse, is applied to Fig. 30, Rotation time can be measured by subtracting between each latched value, making the circuit extremely simple. In particular, when performing energization ignition calculations many times for one ignition, it is necessary to use the latest rotation speed for each energization ignition calculation, so the rotation speed measurement interval is, for example, 0 to 120℃A, 60 to 180℃. There is a possibility of overlap, such as ℃A. This is because the rotational speed measurement interval cannot be made too short in order to minimize the influence of rotational fluctuations due to the combustion cycle of the engine. In this case, if a method of measuring rotation time by starting and stopping a timer register as shown in FIG. 30 is adopted, the number of timer registers will increase and the switching circuit will become very complex. On the other hand, if the method shown in this embodiment is adopted, it can be implemented using the same circuit as in this embodiment, and has the great advantage that the number of subtractions performed by the program only increases. Another function of fixed position processing is the activation of program interrupts. This is a routine that performs ESA calculation, that is, energization ignition calculation, and as shown in Table 3, gear position "2" ( _B = 60℃A)
“5” ( _B = 150℃A), “8” ( _B = 240℃A),
It is activated when "11" ( _B = 330℃A), that is, immediately after the rotation speed measurement is completed. Activation is realized by setting the flip-flop 301 of the interrupt control section 63 shown in FIG. 6 with a signal from the terminal 441, and the program interrupt request signal (terminal 445) becomes "0". The priority of program interrupts is after gear interrupts, so
Immediately after the gear interrupt processing routine shown in FIG. 9 is completed, a program interrupt occurs, and ESA calculation etc. are executed. The gear interrupt processing routine has been described above, but due to its nature, the processing must be completed within the width of the crank angle pulse (30°A). This is because when the process stalls, accurate gear position is lost. Therefore, the processing time must be kept within 30° C. at a rotation speed of 6000 rpm, which is the most practical limit, or about 800 μs. Finally, the program interrupt processing routine is executed in the 26th step.
As shown in the figure. This program interrupt processing routine is originally a program that should be processed by gear interrupts.
This is because the measurement of the rotational speed N, which is the most important parameter in the energization ignition calculation, is performed at a gear interrupt, and if the energization ignition calculation is started at a step immediately after the rotational speed measurement, the responsiveness of the control will be the best. However, this program interrupt handling routine requires a maximum of about 1.5 ms to execute. Therefore, since the allowable processing time for gear interrupts is 800 μs as described above, the program interrupt processing routine cannot be included in the gear interrupt processing routine. Currently, the processing speed of computers is steadily increasing, so it is expected that the processing time for energization ignition calculations will also become shorter. However, at the same time, in order to more accurately control the ignition timing, the crank angle position signal (crank angle pulse) tends to increase, and the allowable processing time for gear interrupts may accordingly become shorter. Furthermore, as engine control becomes more diverse and more detailed, control contents tend to become more complex, and as a result, processing time tends to increase. Therefore, especially when adopting a control method like this example in which the CPU outputs a command and starts counting down at the next crank angle pulse, there will be a large number of contents to be processed by the gear interrupt. Since this increases processing time, program interrupts are essential. On the other hand, there is a method of processing the energization ignition calculation in a lower-level routine other than the program interrupt, such as the main routine, but with this method, as mentioned above, the reflection of the rotation speed N measured by the gear interrupt is delayed and the responsiveness of the ignition system is affected. Getting worse. Below, according to Figure 26,
The program interrupt processing routine will be explained. First, in step 1200, a reset signal is applied to the terminal 442 of the interrupt control section 63 shown in FIG. 6, the flip-flop 301 is reset, and the program interrupt request signal terminal 445 is set to "1". Return to. Next, proceed to step 1201, check the process identification flag PiP, and if it is "0", that is, the _Q2 process was executed at the previous program interrupt, step 120 is executed.
2, if it is "1", that is, the _Q1 process is being executed, the process advances to step 1204. Steps 1202, 12
In 04, the _Q1 processing flag _Q1 and the _Q2 processing flag _Q2 are checked, and if they are "1", the _Q1 processing step 1203 and the _Q2 processing step 1205 respectively.
If the flag is "0", the program interrupt processing routine is completed. _Q1 processing flag _Q1 is set to "1" at gear position "2" ( _B = 60℃A) and "8" ( _B = 240℃A) in the fixed position processing of the gear interrupts in Table 3. It is reset to "0" by executing _Q1 processing step 1203. _Q2 processing flag _Q2 is gear position “5” ( _B = 150
It is set to "1" at C A) "11" ( _B = 330 C A), and is reset to "0" by executing _Q2 processing 1205. The contents of _Q1 processing step 1203 and _Q2 processing step 1205 are shown in FIG. In the case of the _Q2 process, the energization ignition calculations after step 1211 are executed at low rotation speeds, for example, 4000 rpm or less. In other words, the average rotation time τm and tH (30°C
rotation time) are compared, and in the low rotation region, τm≧tH
When this is the case, the process proceeds to step 1211, where the energization and ignition calculation is executed, and when τm<tH in the high rotation region, the calculation is not executed and the _Q2 process ends. Step 1211 was explained in the above-mentioned gear interrupt fixed position processing. The rotational speed N is determined from the passing time of the crank angle pulse. Gear position “2” ( _B = 60℃
A) In the case of _Q1 processing of startup, N is τN obtained by equation (12)
It is obtained from the reciprocal of , using equation (13). N=8/τN×30/360×60×10 ⁶ (rpm) ...(13) (The unit of τN is 8 μs) Next, in step 1212, the signal from the starter switch 23 shown in FIG. 1 is checked and if it is “ON”. If the fixed value θ _CR is set to the ignition angle θx and it is “OFF”, the process proceeds to step 1213, and the intake air amount Ga written in the predetermined address of the RAM 70 is calculated per rotation using the rotation speed N ₄ and the DMA method. Find the intake air amount Ga/N. In step 1214, the basic advance angle θM _AP given corresponding to the rotational speed N and the intake air amount Ga/N stored in the ROM 71 is determined.
Steps 1211 and 121 from the map representing
Regarding (N, Ga/N) obtained in 3, the following (14),
Values of 4 points on the map that satisfy equation (15) θM _AP1 =
(N ₁ , (Ga/N) ₁ ), θM _AP2 = (N ₁ , (Ga/N)
₂ ), θM _AP3 = N ₂ (Ga/N) ₁ , θM _AP4 =
(N ₂ , (Ga/N) ₂ ) is first read. In this example, the map representing the basic advance angle is from 0.001 (g/cm ³ , rpm) for Ga/N as shown in Table 4.
0.016 (g/cm ³ rpm) to 0.001 (g/cm ³ rpm)
In increments, and for N from 500 (rpm)
1000 (rpm) in 100 (rpm) steps up to 1000 (rpm)
(rpm) to 6000 (rpm), data representing the basic advance angle is stored in steps of 500 (rpm) (detailed values are omitted in Table 4).
16=) It is a two-dimensional map with 256 points.

[Table] N ₁ <N < N ₂ - (14) (Ga/N) ₁ < (Ga/N) < (Ga/N) ₂ - (15) In step 1214, next, from the values of the above four points,
First, N is calculated by linear interpolation using equations (16) and (17). θM _AP5 = θM _AP3 -θM _AP1 /N ₂ -N ₁ × (N-N ₁ ) + θM _AP1 - (16) θM _AP6 = θM _AP4 - θM _AP2 /N ₂ -N ₁ (N-N ₂ ) + θM _AP - (17) Next, perform linear interpolation calculation for (Ga/N) using equation (18) to obtain the basic advance angle θM _AP . Step θM _AP = θM _AP6 - θM _AP5 / (Ga/N) ₂ -
(Ga/N) ₁ {(Ga/N) - (Ga/N)} + θM _AP5 - (18) In 1215, the ignition angle θx is determined by adding various correction advance angles to the basic advance angle using equation (19). θx = TDC - (θM _AP + θEGR + θ _ACC + θ _WT + θ _DLY ) - (19) θEGR: EGR advance angle...see equation (8), 50msec processing θ _ACC : Acceleration advance angle...see equation (5), 50msec processing rotation Position processing θ _WT : Water temperature advance...main routine θ _DLY : Ignition delay angle...see equation (11), fixed Position processing After executing steps 1218 and 1215, the 28th
Proceed to the ESA calculation step 1216 shown in the figure. In the ESA calculation steps shown in FIG. 28, in steps 1230 to 1233, the ignition angle _is
(TDC-70°C A) to θM _A x (TDC). Next, in step 1234, the ignition gear position _θx1 is calculated using equation (2). In step 1235, the energization ON time τ calculated from the battery voltage in the 8ms processing routine shown in FIG.
ON is determined by the rotation speed N calculated in step 1211, the duration angle of energization ON, that is, the dwell angle θON
It is converted to . Step 12 using this θON
At 36, the minimum allowable dwell angle θ'ON is calculated.
In this example, θ'ON is substituted with a value of 75% of θON. Subsequently, in step 1237, the conduction angle θ is calculated from the ignition angle θx and the dwell angle θON. In steps 1238 and 1239, the upper limit of energization is adjusted so that θ≧0. In step 1240, the energizing gear position _θ1 and the energizing down counter value τ are calculated based on the energizing angle θ as shown in equation (1). Finally, the aforementioned ignition calculation flag A _A and ignition calculation flag B _B are set to "0". _Q1 processing,
The calculated value calculated in the _Q2 process is written to the calculated value storage table iGT shown in Table 1. There are two computed value storage tables (iGT
1, iGT2), if flag TAB is “0”, iGT
If 2 is "1", it is written to iGT1, and after the writing is completed, flag TAB is inverted in step 1217. In the above embodiment, the solenoid valve 15 was applied to correct the air flow rate of the air bleed 14 of the carburetor 13;
As a device for controlling the amount of fuel in the fuel passage No. 3,
As a device for controlling the opening degree of the EGR valve 9, as a device for controlling the amount of secondary air supplied to the exhaust system of the engine, further as a device for controlling the amount of air bypassing the throttle valve of the engine, etc. Needless to say, it can be applied to various control devices. Further, in the above embodiment, the CPU 60 executes calculation of the target duty ratio Dref using the 50ms processing program, and according to the calculated value, the solenoid valve is turned on/off (ON,
OFF), but the 8ms
The solenoid valve is turned on and off according to the calculated value Dref of the target duty ratio in the 8ms processing program that is executed every time.
It is also possible to execute OFF discrimination control. The effect of the method of the present invention can be explained in the third example by the effect example in this case.
This will be explained with reference to FIG. In Figure 32, the control period of the solenoid valve is 8.192×6=49.152ms, and the resolution is
It is 8.192ms. Also, the ↓ point in the figure indicates the time point when the control target duty ratio Dref is calculated by the 50ms processing program, and the output for controlling the solenoid valve ON and OFF using two methods for each calculated value is a and b.
Shown below. The method shown in the waveform diagram of Fig. 32a is a method in which the conventional method shown in Fig. 31, which uses a latch, a down counter, and a control circuit, is processed by a program using the CPU, and the target duty ratio Dref is set in the latch. Instead, the 8ms processing program commands the solenoid valve to turn ON and OFF every 8.192ms. On the other hand, FIG. 32b shows a waveform diagram of the method based on the idea of the present invention, in which the control target duty ratio Dref is changed from A to Dref by the 8ms processing program.
The solenoid valve is controlled ON and OFF so that the actual duty ratio Dreal in each section as shown in E is reached. In other words, with the 8ms sulfurization program, the following
The past when the solenoid valve was turned on for 8.192ms
The actual duty ratio Dreal of 49.152ms and the following
Past when the solenoid valve was turned off for 8.192ms
Determine which of the actual duty ratios D′real during 49.152ms is closer to the control target value Dref,
Control the solenoid valves ON and OFF so that they are close to each other. According to Fig. 32, the control target value Dref is from 5/6 to 1/2.
When the value changes to 8.192×5 using the method shown in waveform diagram a.
= 40.96, the target value is reached after 41ms (that is, 5 sections D), whereas in the method of the present invention shown in waveform diagram b,
The target value is reached after 8.192×2≈16ms (that is, section A). As shown in the above example, the method of the present invention has significantly improved responsiveness compared to the method shown in waveform diagram a. However, like the method of the present invention, every 8ms
Even if ON and OFF are not determined based on the target duty ratio Dref and the actual duty ratio Dreal, the control target duty ratio Dref can be compared with the previous calculated value, and if it increases, the next control cycle will start from the solenoid valve ON. , responsiveness can also be improved by starting control from OFF when it decreases, but in this case overshoot and undershoot become a problem.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
The figure is a block diagram of the microcomputer shown in Figure 1, Figures 3 and 8 are waveform diagrams for explaining each part of Figure 2, and Figures 4 to 7 and 9 to 13 are each part of Figure 2. 14 is an explanatory diagram of the operation of the central processing unit (CPu) shown in FIG. 2, FIGS. 15 to 29 are flowcharts showing the contents of the program of the CPu shown in FIG. 2, and FIG. 3
1 and 32 are a configuration diagram and a waveform diagram cited for explaining the present invention. 6...Microcomputer, 60...Central processing unit (CPU), 14...Air bleed, 1
5... Solenoid valve.

Claims (1)

[Claims] 1 A microcomputer determines whether the solenoid valve should be turned on or off at predetermined intervals based on a pre-calculated target duty ratio that determines the ratio between on and off of an on-off type solenoid valve. A method for controlling the duty ratio of a solenoid valve by making a determination using a central processing unit and controlling the solenoid valve to turn on or off at predetermined intervals based on the determination result, the method comprising: Whether the solenoid valve should be turned on or off is determined by comparing whether the ratio of the number of times the solenoid valve is turned on and the number of times the solenoid valve is turned off is larger or smaller than the target duty ratio at each predetermined period. A method for controlling a duty ratio of a solenoid valve, characterized in that the determination is made at each predetermined period.